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/arch/ppc/platforms/ev64260.c

https://bitbucket.org/evzijst/gittest
C | 651 lines | 454 code | 109 blank | 88 comment | 30 complexity | 712a50e33e8cd3629f918de689ee95dc MD5 | raw file
  1/*
  2 * arch/ppc/platforms/ev64260.c
  3 *
  4 * Board setup routines for the Marvell/Galileo EV-64260-BP Evaluation Board.
  5 *
  6 * Author: Mark A. Greer <mgreer@mvista.com>
  7 *
  8 * 2001-2003 (c) MontaVista, Software, Inc.  This file is licensed under
  9 * the terms of the GNU General Public License version 2.  This program
 10 * is licensed "as is" without any warranty of any kind, whether express
 11 * or implied.
 12 */
 13
 14/*
 15 * The EV-64260-BP port is the result of hard work from many people from
 16 * many companies.  In particular, employees of Marvell/Galileo, Mission
 17 * Critical Linux, Xyterra, and MontaVista Software were heavily involved.
 18 *
 19 * Note: I have not been able to get *all* PCI slots to work reliably
 20 *	at 66 MHz.  I recommend setting jumpers J15 & J16 to short pins 1&2
 21 *	so that 33 MHz is used. --MAG
 22 * Note: The 750CXe and 7450 are not stable with a 125MHz or 133MHz TCLK/SYSCLK.
 23 * 	At 100MHz, they are solid.
 24 */
 25#include <linux/config.h>
 26
 27#include <linux/delay.h>
 28#include <linux/pci.h>
 29#include <linux/ide.h>
 30#include <linux/irq.h>
 31#include <linux/fs.h>
 32#include <linux/seq_file.h>
 33#include <linux/console.h>
 34#include <linux/initrd.h>
 35#include <linux/root_dev.h>
 36#if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
 37#include <linux/serial.h>
 38#include <linux/tty.h>
 39#include <linux/serial_core.h>
 40#else
 41#include <linux/mv643xx.h>
 42#endif
 43#include <asm/bootinfo.h>
 44#include <asm/machdep.h>
 45#include <asm/mv64x60.h>
 46#include <asm/todc.h>
 47#include <asm/time.h>
 48
 49#include <platforms/ev64260.h>
 50
 51#define BOARD_VENDOR	"Marvell/Galileo"
 52#define BOARD_MACHINE	"EV-64260-BP"
 53
 54static struct mv64x60_handle	bh;
 55
 56#if !defined(CONFIG_SERIAL_MPSC_CONSOLE)
 57extern void gen550_progress(char *, unsigned short);
 58extern void gen550_init(int, struct uart_port *);
 59#endif
 60
 61static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
 62	18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
 63};
 64static const unsigned int cpu_745x[2][16] = { /* PLL_EXT 0 & 1 */
 65	{ 1, 15, 14,  2,  4, 13,  5,  9,  6, 11,  8, 10, 16, 12,  7,  0 },
 66	{ 0, 30,  0,  2,  0, 26,  0, 18,  0, 22, 20, 24, 28, 32,  0,  0 }
 67};
 68
 69
 70TODC_ALLOC();
 71
 72static int
 73ev64260_get_bus_speed(void)
 74{
 75	return 100000000;
 76}
 77
 78static int
 79ev64260_get_cpu_speed(void)
 80{
 81	unsigned long	pvr, hid1, pll_ext;
 82
 83	pvr = PVR_VER(mfspr(SPRN_PVR));
 84
 85	if (pvr != PVR_VER(PVR_7450)) {
 86		hid1 = mfspr(SPRN_HID1) >> 28;
 87		return ev64260_get_bus_speed() * cpu_7xx[hid1]/2;
 88	}
 89	else {
 90		hid1 = (mfspr(SPRN_HID1) & 0x0001e000) >> 13;
 91		pll_ext = 0; /* No way to read; must get from schematic */
 92		return ev64260_get_bus_speed() * cpu_745x[pll_ext][hid1]/2;
 93	}
 94}
 95
 96unsigned long __init
 97ev64260_find_end_of_memory(void)
 98{
 99	return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
100		MV64x60_TYPE_GT64260A);
101}
102
103/*
104 * Marvell/Galileo EV-64260-BP Evaluation Board PCI interrupt routing.
105 * Note: By playing with J8 and JP1-4, you can get 2 IRQ's from the first
106 *	PCI bus (in which cast, INTPIN B would be EV64260_PCI_1_IRQ).
107 *	This is the most IRQs you can get from one bus with this board, though.
108 */
109static int __init
110ev64260_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
111{
112	struct pci_controller	*hose = pci_bus_to_hose(dev->bus->number);
113
114	if (hose->index == 0) {
115		static char pci_irq_table[][4] =
116		/*
117		 *	PCI IDSEL/INTPIN->INTLINE
118		 * 	   A   B   C   D
119		 */
120		{
121			{EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 0 */
122			{EV64260_PCI_0_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 0 */
123		};
124
125		const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
126		return PCI_IRQ_TABLE_LOOKUP;
127	}
128	else {
129		static char pci_irq_table[][4] =
130		/*
131		 *	PCI IDSEL/INTPIN->INTLINE
132		 * 	   A   B   C   D
133		 */
134		{
135			{ EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 7 - PCI bus 1 */
136			{ EV64260_PCI_1_IRQ,0,0,0}, /* IDSEL 8 - PCI bus 1 */
137		};
138
139		const long min_idsel = 7, max_idsel = 8, irqs_per_slot = 4;
140		return PCI_IRQ_TABLE_LOOKUP;
141	}
142}
143
144static void __init
145ev64260_setup_peripherals(void)
146{
147	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
148		EV64260_EMB_FLASH_BASE, EV64260_EMB_FLASH_SIZE, 0);
149	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
150	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
151		EV64260_EXT_SRAM_BASE, EV64260_EXT_SRAM_SIZE, 0);
152	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
153	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
154		EV64260_TODC_BASE, EV64260_TODC_SIZE, 0);
155	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
156	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
157		EV64260_UART_BASE, EV64260_UART_SIZE, 0);
158	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
159	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
160		EV64260_EXT_FLASH_BASE, EV64260_EXT_FLASH_SIZE, 0);
161	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
162
163	TODC_INIT(TODC_TYPE_DS1501, 0, 0,
164			ioremap(EV64260_TODC_BASE, EV64260_TODC_SIZE), 8);
165
166	mv64x60_clr_bits(&bh, MV64x60_CPU_CONFIG,((1<<12) | (1<<28) | (1<<29)));
167	mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<27));
168
169	if (ev64260_get_bus_speed() > 100000000)
170		mv64x60_set_bits(&bh, MV64x60_CPU_CONFIG, (1<<23));
171
172	mv64x60_set_bits(&bh, MV64x60_PCI0_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
173	mv64x60_set_bits(&bh, MV64x60_PCI1_PCI_DECODE_CNTL, ((1<<0) | (1<<3)));
174
175        /*
176         * Enabling of PCI internal-vs-external arbitration
177         * is a platform- and errata-dependent decision.
178         */
179        if (bh.type == MV64x60_TYPE_GT64260A )  {
180                mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
181                mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
182        }
183
184        mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
185
186	/*
187	 * Turn off timer/counters.  Not turning off watchdog timer because
188	 * can't read its reg on the 64260A so don't know if we'll be enabling
189	 * or disabling.
190	 */
191	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
192			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
193	mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
194			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
195
196	/*
197	 * Set MPSC Multiplex RMII
198	 * NOTE: ethernet driver modifies bit 0 and 1
199	 */
200	mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
201
202	/*
203	 * The EV-64260-BP uses several Multi-Purpose Pins (MPP) on the 64260
204	 * bridge as interrupt inputs (via the General Purpose Ports (GPP)
205	 * register).  Need to route the MPP inputs to the GPP and set the
206	 * polarity correctly.
207	 *
208	 * In MPP Control 2 Register
209	 *   MPP 21 -> GPP 21 (DUART channel A intr) bits 20-23 -> 0
210	 *   MPP 22 -> GPP 22 (DUART channel B intr) bits 24-27 -> 0
211	 */
212	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_2, (0xf<<20) | (0xf<<24) );
213
214	/*
215	 * In MPP Control 3 Register
216	 *   MPP 26 -> GPP 26 (RTC INT)		bits  8-11 -> 0
217	 *   MPP 27 -> GPP 27 (PCI 0 INTA)	bits 12-15 -> 0
218	 *   MPP 29 -> GPP 29 (PCI 1 INTA)	bits 20-23 -> 0
219	 */
220	mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3, (0xf<<8)|(0xf<<12)|(0xf<<20));
221
222#define GPP_EXTERNAL_INTERRUPTS \
223		((1<<21) | (1<<22) | (1<<26) | (1<<27) | (1<<29))
224	/* DUART & PCI interrupts are inputs */
225	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
226	/* DUART & PCI interrupts are active low */
227	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
228
229	/* Clear any pending interrupts for these inputs and enable them. */
230	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
231	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
232
233	return;
234}
235
236static void __init
237ev64260_setup_bridge(void)
238{
239	struct mv64x60_setup_info	si;
240	int				i;
241
242	memset(&si, 0, sizeof(si));
243
244	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
245
246	si.pci_0.enable_bus = 1;
247	si.pci_0.pci_io.cpu_base = EV64260_PCI0_IO_CPU_BASE;
248	si.pci_0.pci_io.pci_base_hi = 0;
249	si.pci_0.pci_io.pci_base_lo = EV64260_PCI0_IO_PCI_BASE;
250	si.pci_0.pci_io.size = EV64260_PCI0_IO_SIZE;
251	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
252	si.pci_0.pci_mem[0].cpu_base = EV64260_PCI0_MEM_CPU_BASE;
253	si.pci_0.pci_mem[0].pci_base_hi = 0;
254	si.pci_0.pci_mem[0].pci_base_lo = EV64260_PCI0_MEM_PCI_BASE;
255	si.pci_0.pci_mem[0].size = EV64260_PCI0_MEM_SIZE;
256	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
257	si.pci_0.pci_cmd_bits = 0;
258	si.pci_0.latency_timer = 0x8;
259
260	si.pci_1.enable_bus = 1;
261	si.pci_1.pci_io.cpu_base = EV64260_PCI1_IO_CPU_BASE;
262	si.pci_1.pci_io.pci_base_hi = 0;
263	si.pci_1.pci_io.pci_base_lo = EV64260_PCI1_IO_PCI_BASE;
264	si.pci_1.pci_io.size = EV64260_PCI1_IO_SIZE;
265	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
266	si.pci_1.pci_mem[0].cpu_base = EV64260_PCI1_MEM_CPU_BASE;
267	si.pci_1.pci_mem[0].pci_base_hi = 0;
268	si.pci_1.pci_mem[0].pci_base_lo = EV64260_PCI1_MEM_PCI_BASE;
269	si.pci_1.pci_mem[0].size = EV64260_PCI1_MEM_SIZE;
270	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
271	si.pci_1.pci_cmd_bits = 0;
272	si.pci_1.latency_timer = 0x8;
273
274	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
275		si.cpu_prot_options[i] = 0;
276		si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
277		si.pci_0.acc_cntl_options[i] =
278			GT64260_PCI_ACC_CNTL_DREADEN |
279			GT64260_PCI_ACC_CNTL_RDPREFETCH |
280			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
281			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
282			GT64260_PCI_ACC_CNTL_SWAP_NONE |
283			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
284		si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
285		si.pci_1.acc_cntl_options[i] =
286			GT64260_PCI_ACC_CNTL_DREADEN |
287			GT64260_PCI_ACC_CNTL_RDPREFETCH |
288			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
289			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
290			GT64260_PCI_ACC_CNTL_SWAP_NONE |
291			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
292		si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
293	}
294
295        /* Lookup PCI host bridges */
296        if (mv64x60_init(&bh, &si))
297                printk(KERN_ERR "Bridge initialization failed.\n");
298
299	pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
300	ppc_md.pci_swizzle = common_swizzle;
301	ppc_md.pci_map_irq = ev64260_map_irq;
302	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
303
304	mv64x60_set_bus(&bh, 0, 0);
305	bh.hose_a->first_busno = 0;
306	bh.hose_a->last_busno = 0xff;
307	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
308
309	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
310	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
311	bh.hose_b->last_busno = 0xff;
312	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
313		bh.hose_b->first_busno);
314
315	return;
316}
317
318#if defined(CONFIG_SERIAL_8250) && !defined(CONFIG_SERIAL_MPSC_CONSOLE)
319static void __init
320ev64260_early_serial_map(void)
321{
322	struct uart_port	port;
323	static char		first_time = 1;
324
325	if (first_time) {
326		memset(&port, 0, sizeof(port));
327
328		port.membase = ioremap(EV64260_SERIAL_0, EV64260_UART_SIZE);
329		port.irq = EV64260_UART_0_IRQ;
330		port.uartclk = BASE_BAUD * 16;
331		port.regshift = 2;
332		port.iotype = SERIAL_IO_MEM;
333		port.flags = STD_COM_FLAGS;
334
335#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
336		gen550_init(0, &port);
337#endif
338
339		if (early_serial_setup(&port) != 0)
340			printk(KERN_WARNING "Early serial init of port 0"
341				"failed\n");
342
343		first_time = 0;
344	}
345
346	return;
347}
348#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
349static void __init
350ev64260_early_serial_map(void)
351{
352}
353#endif
354
355static void __init
356ev64260_setup_arch(void)
357{
358	if (ppc_md.progress)
359		ppc_md.progress("ev64260_setup_arch: enter", 0);
360
361#ifdef CONFIG_BLK_DEV_INITRD
362	if (initrd_start)
363		ROOT_DEV = Root_RAM0;
364	else
365#endif
366#ifdef	CONFIG_ROOT_NFS
367		ROOT_DEV = Root_NFS;
368#else
369		ROOT_DEV = Root_SDA2;
370#endif
371
372	if (ppc_md.progress)
373		ppc_md.progress("ev64260_setup_arch: Enabling L2 cache", 0);
374
375	/* Enable L2 and L3 caches (if 745x) */
376	_set_L2CR(_get_L2CR() | L2CR_L2E);
377	_set_L3CR(_get_L3CR() | L3CR_L3E);
378
379	if (ppc_md.progress)
380		ppc_md.progress("ev64260_setup_arch: Initializing bridge", 0);
381
382	ev64260_setup_bridge();		/* set up PCI bridge(s) */
383	ev64260_setup_peripherals();	/* set up chip selects/GPP/MPP etc */
384
385	if (ppc_md.progress)
386		ppc_md.progress("ev64260_setup_arch: bridge init complete", 0);
387
388#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_MPSC_CONSOLE)
389	ev64260_early_serial_map();
390#endif
391
392	printk(KERN_INFO "%s %s port (C) 2001 MontaVista Software, Inc."
393		"(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
394
395	if (ppc_md.progress)
396		ppc_md.progress("ev64260_setup_arch: exit", 0);
397
398	return;
399}
400
401/* Platform device data fixup routines. */
402#if defined(CONFIG_SERIAL_MPSC)
403static void __init
404ev64260_fixup_mpsc_pdata(struct platform_device *pdev)
405{
406	struct mpsc_pdata *pdata;
407
408	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
409
410	pdata->max_idle = 40;
411	pdata->default_baud = EV64260_DEFAULT_BAUD;
412	pdata->brg_clk_src = EV64260_MPSC_CLK_SRC;
413	pdata->brg_clk_freq = EV64260_MPSC_CLK_FREQ;
414
415	return;
416}
417
418static int __init
419ev64260_platform_notify(struct device *dev)
420{
421	static struct {
422		char	*bus_id;
423		void	((*rtn)(struct platform_device *pdev));
424	} dev_map[] = {
425		{ MPSC_CTLR_NAME ".0", ev64260_fixup_mpsc_pdata },
426		{ MPSC_CTLR_NAME ".1", ev64260_fixup_mpsc_pdata },
427	};
428	struct platform_device	*pdev;
429	int	i;
430
431	if (dev && dev->bus_id)
432		for (i=0; i<ARRAY_SIZE(dev_map); i++)
433			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
434				BUS_ID_SIZE)) {
435
436				pdev = container_of(dev,
437					struct platform_device, dev);
438				dev_map[i].rtn(pdev);
439			}
440
441	return 0;
442}
443#endif
444
445static void
446ev64260_reset_board(void *addr)
447{
448	local_irq_disable();
449
450	/* disable and invalidate the L2 cache */
451	_set_L2CR(0);
452	_set_L2CR(0x200000);
453
454	/* flush and disable L1 I/D cache */
455	__asm__ __volatile__
456	("mfspr   3,1008\n\t"
457	 "ori	5,5,0xcc00\n\t"
458	 "ori	4,3,0xc00\n\t"
459	 "andc	5,3,5\n\t"
460	 "sync\n\t"
461	 "mtspr	1008,4\n\t"
462	 "isync\n\t"
463	 "sync\n\t"
464	 "mtspr	1008,5\n\t"
465	 "isync\n\t"
466	 "sync\n\t");
467
468	/* unmap any other random cs's that might overlap with bootcs */
469	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, 0, 0, 0);
470	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
471	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, 0, 0, 0);
472	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
473	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, 0, 0, 0);
474	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
475	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN, 0, 0, 0);
476	bh.ci->disable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
477
478	/* map bootrom back in to gt @ reset defaults */
479	mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
480						0xff800000, 8*1024*1024, 0);
481	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
482
483	/* move reg base back to default, setup default pci0 */
484	mv64x60_write(&bh, MV64x60_INTERNAL_SPACE_DECODE,
485		(1<<24) | CONFIG_MV64X60_BASE >> 20);
486
487	/* NOTE: FROM NOW ON no more GT_REGS accesses.. 0x1 is not mapped
488	 * via BAT or MMU, and MSR IR/DR is ON */
489	/* SRR0 has system reset vector, SRR1 has default MSR value */
490	/* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
491	/* NOTE: assumes reset vector is at 0xfff00100 */
492	__asm__ __volatile__
493	("mtspr   26, %0\n\t"
494	 "li      4,(1<<6)\n\t"
495	 "mtspr   27,4\n\t"
496	 "rfi\n\t"
497	 :: "r" (addr):"r4");
498
499	return;
500}
501
502static void
503ev64260_restart(char *cmd)
504{
505	volatile ulong	i = 10000000;
506
507	ev64260_reset_board((void *)0xfff00100);
508
509	while (i-- > 0);
510	panic("restart failed\n");
511}
512
513static void
514ev64260_halt(void)
515{
516	local_irq_disable();
517	while (1);
518	/* NOTREACHED */
519}
520
521static void
522ev64260_power_off(void)
523{
524	ev64260_halt();
525	/* NOTREACHED */
526}
527
528static int
529ev64260_show_cpuinfo(struct seq_file *m)
530{
531	uint pvid;
532
533	pvid = mfspr(SPRN_PVR);
534	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
535	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
536	seq_printf(m, "cpu MHz\t\t: %d\n", ev64260_get_cpu_speed()/1000/1000);
537	seq_printf(m, "bus MHz\t\t: %d\n", ev64260_get_bus_speed()/1000/1000);
538
539	return 0;
540}
541
542/* DS1501 RTC has too much variation to use RTC for calibration */
543static void __init
544ev64260_calibrate_decr(void)
545{
546	ulong freq;
547
548	freq = ev64260_get_bus_speed()/4;
549
550	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
551	       freq/1000000, freq%1000000);
552
553	tb_ticks_per_jiffy = freq / HZ;
554	tb_to_us = mulhwu_scale_factor(freq, 1000000);
555
556	return;
557}
558
559/*
560 * Set BAT 3 to map 0xfb000000 to 0xfc000000 of physical memory space.
561 */
562static __inline__ void
563ev64260_set_bat(void)
564{
565	mb();
566	mtspr(SPRN_DBAT1U, 0xfb0001fe);
567	mtspr(SPRN_DBAT1L, 0xfb00002a);
568	mb();
569
570	return;
571}
572
573#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
574static void __init
575ev64260_map_io(void)
576{
577	io_block_mapping(0xfb000000, 0xfb000000, 0x01000000, _PAGE_IO);
578}
579#endif
580
581void __init
582platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
583	      unsigned long r6, unsigned long r7)
584{
585#ifdef CONFIG_BLK_DEV_INITRD
586	extern int	initrd_below_start_ok;
587
588	initrd_start=initrd_end=0;
589	initrd_below_start_ok=0;
590#endif /* CONFIG_BLK_DEV_INITRD */
591
592	parse_bootinfo(find_bootinfo());
593
594	isa_mem_base = 0;
595	isa_io_base = EV64260_PCI0_IO_CPU_BASE;
596	pci_dram_offset = EV64260_PCI0_MEM_CPU_BASE;
597
598	loops_per_jiffy = ev64260_get_cpu_speed() / HZ;
599
600	ppc_md.setup_arch = ev64260_setup_arch;
601	ppc_md.show_cpuinfo = ev64260_show_cpuinfo;
602	ppc_md.init_IRQ = gt64260_init_irq;
603	ppc_md.get_irq = gt64260_get_irq;
604
605	ppc_md.restart = ev64260_restart;
606	ppc_md.power_off = ev64260_power_off;
607	ppc_md.halt = ev64260_halt;
608
609	ppc_md.find_end_of_memory = ev64260_find_end_of_memory;
610
611	ppc_md.init = NULL;
612
613	ppc_md.time_init = todc_time_init;
614	ppc_md.set_rtc_time = todc_set_rtc_time;
615	ppc_md.get_rtc_time = todc_get_rtc_time;
616	ppc_md.nvram_read_val = todc_direct_read_val;
617	ppc_md.nvram_write_val = todc_direct_write_val;
618	ppc_md.calibrate_decr = ev64260_calibrate_decr;
619
620	bh.p_base = CONFIG_MV64X60_NEW_BASE;
621
622	ev64260_set_bat();
623
624#ifdef	CONFIG_SERIAL_8250
625#if defined(CONFIG_SERIAL_TEXT_DEBUG)
626	ppc_md.setup_io_mappings = ev64260_map_io;
627	ppc_md.progress = gen550_progress;
628#endif
629#if defined(CONFIG_KGDB)
630	ppc_md.setup_io_mappings = ev64260_map_io;
631	ppc_md.early_serial_map = ev64260_early_serial_map;
632#endif
633#elif defined(CONFIG_SERIAL_MPSC_CONSOLE)
634#ifdef	CONFIG_SERIAL_TEXT_DEBUG
635	ppc_md.setup_io_mappings = ev64260_map_io;
636	ppc_md.progress = mv64x60_mpsc_progress;
637	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
638#endif	/* CONFIG_SERIAL_TEXT_DEBUG */
639#ifdef	CONFIG_KGDB
640	ppc_md.setup_io_mappings = ev64260_map_io;
641	ppc_md.early_serial_map = ev64260_early_serial_map;
642#endif	/* CONFIG_KGDB */
643
644#endif
645
646#if defined(CONFIG_SERIAL_MPSC)
647	platform_notify = ev64260_platform_notify;
648#endif
649
650	return;
651}