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/arch/ppc/platforms/cpci690.c

https://bitbucket.org/evzijst/gittest
C | 491 lines | 369 code | 76 blank | 46 comment | 23 complexity | 458ce831b331b8f027f456f1ac9c6a5f MD5 | raw file
  1/*
  2 * arch/ppc/platforms/cpci690.c
  3 *
  4 * Board setup routines for the Force CPCI690 board.
  5 *
  6 * Author: Mark A. Greer <mgreer@mvista.com>
  7 *
  8 * 2003 (c) MontaVista Software, Inc.  This file is licensed under
  9 * the terms of the GNU General Public License version 2.  This programr
 10 * is licensed "as is" without any warranty of any kind, whether express
 11 * or implied.
 12 */
 13#include <linux/config.h>
 14#include <linux/delay.h>
 15#include <linux/pci.h>
 16#include <linux/ide.h>
 17#include <linux/irq.h>
 18#include <linux/fs.h>
 19#include <linux/seq_file.h>
 20#include <linux/console.h>
 21#include <linux/initrd.h>
 22#include <linux/root_dev.h>
 23#include <linux/mv643xx.h>
 24#include <asm/bootinfo.h>
 25#include <asm/machdep.h>
 26#include <asm/todc.h>
 27#include <asm/time.h>
 28#include <asm/mv64x60.h>
 29#include <platforms/cpci690.h>
 30
 31#define BOARD_VENDOR	"Force"
 32#define BOARD_MACHINE	"CPCI690"
 33
 34/* Set IDE controllers into Native mode? */
 35#define SET_PCI_IDE_NATIVE
 36
 37static struct mv64x60_handle	bh;
 38static u32 cpci690_br_base;
 39
 40static const unsigned int cpu_7xx[16] = { /* 7xx & 74xx (but not 745x) */
 41	18, 15, 14, 2, 4, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
 42};
 43
 44TODC_ALLOC();
 45
 46static int __init
 47cpci690_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 48{
 49	struct pci_controller	*hose = pci_bus_to_hose(dev->bus->number);
 50
 51	if (hose->index == 0) {
 52		static char pci_irq_table[][4] =
 53		/*
 54		 *	PCI IDSEL/INTPIN->INTLINE
 55		 * 	   A   B   C   D
 56		 */
 57		{
 58			{ 90, 91, 88, 89}, /* IDSEL 30/20 - Sentinel */
 59		};
 60
 61		const long min_idsel = 20, max_idsel = 20, irqs_per_slot = 4;
 62		return PCI_IRQ_TABLE_LOOKUP;
 63	} else {
 64		static char pci_irq_table[][4] =
 65		/*
 66		 *	PCI IDSEL/INTPIN->INTLINE
 67		 * 	   A   B   C   D
 68		 */
 69		{
 70			{ 93, 94, 95, 92}, /* IDSEL 28/18 - PMC slot 2 */
 71			{  0,  0,  0,  0}, /* IDSEL 29/19 - Not used */
 72			{ 94, 95, 92, 93}, /* IDSEL 30/20 - PMC slot 1 */
 73		};
 74
 75		const long min_idsel = 18, max_idsel = 20, irqs_per_slot = 4;
 76		return PCI_IRQ_TABLE_LOOKUP;
 77	}
 78}
 79
 80static int
 81cpci690_get_cpu_speed(void)
 82{
 83	unsigned long	hid1;
 84
 85	hid1 = mfspr(SPRN_HID1) >> 28;
 86	return CPCI690_BUS_FREQ * cpu_7xx[hid1]/2;
 87}
 88
 89#define	KB	(1024UL)
 90#define	MB	(1024UL * KB)
 91#define	GB	(1024UL * MB)
 92
 93unsigned long __init
 94cpci690_find_end_of_memory(void)
 95{
 96	u32		mem_ctlr_size;
 97	static u32	board_size;
 98	static u8	first_time = 1;
 99
100	if (first_time) {
101		/* Using cpci690_set_bat() mapping ==> virt addr == phys addr */
102		switch (in_8((u8 *) (cpci690_br_base +
103			CPCI690_BR_MEM_CTLR)) & 0x07) {
104		case 0x01:
105			board_size = 256*MB;
106			break;
107		case 0x02:
108			board_size = 512*MB;
109			break;
110		case 0x03:
111			board_size = 768*MB;
112			break;
113		case 0x04:
114			board_size = 1*GB;
115			break;
116		case 0x05:
117			board_size = 1*GB + 512*MB;
118			break;
119		case 0x06:
120			board_size = 2*GB;
121			break;
122		default:
123			board_size = 0xffffffff; /* use mem ctlr size */
124		} /* switch */
125
126		mem_ctlr_size =  mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
127			MV64x60_TYPE_GT64260A);
128
129		/* Check that mem ctlr & board reg agree.  If not, pick MIN. */
130		if (board_size != mem_ctlr_size) {
131			printk(KERN_WARNING "Board register & memory controller"
132				"mem size disagree (board reg: 0x%lx, "
133				"mem ctlr: 0x%lx)\n",
134				(ulong)board_size, (ulong)mem_ctlr_size);
135			board_size = min(board_size, mem_ctlr_size);
136		}
137
138		first_time = 0;
139	} /* if */
140
141	return board_size;
142}
143
144static void __init
145cpci690_setup_bridge(void)
146{
147	struct mv64x60_setup_info	si;
148	int				i;
149
150	memset(&si, 0, sizeof(si));
151
152	si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
153
154	si.pci_0.enable_bus = 1;
155	si.pci_0.pci_io.cpu_base = CPCI690_PCI0_IO_START_PROC_ADDR;
156	si.pci_0.pci_io.pci_base_hi = 0;
157	si.pci_0.pci_io.pci_base_lo = CPCI690_PCI0_IO_START_PCI_ADDR;
158	si.pci_0.pci_io.size = CPCI690_PCI0_IO_SIZE;
159	si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
160	si.pci_0.pci_mem[0].cpu_base = CPCI690_PCI0_MEM_START_PROC_ADDR;
161	si.pci_0.pci_mem[0].pci_base_hi = CPCI690_PCI0_MEM_START_PCI_HI_ADDR;
162	si.pci_0.pci_mem[0].pci_base_lo = CPCI690_PCI0_MEM_START_PCI_LO_ADDR;
163	si.pci_0.pci_mem[0].size = CPCI690_PCI0_MEM_SIZE;
164	si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
165	si.pci_0.pci_cmd_bits = 0;
166	si.pci_0.latency_timer = 0x80;
167
168	si.pci_1.enable_bus = 1;
169	si.pci_1.pci_io.cpu_base = CPCI690_PCI1_IO_START_PROC_ADDR;
170	si.pci_1.pci_io.pci_base_hi = 0;
171	si.pci_1.pci_io.pci_base_lo = CPCI690_PCI1_IO_START_PCI_ADDR;
172	si.pci_1.pci_io.size = CPCI690_PCI1_IO_SIZE;
173	si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
174	si.pci_1.pci_mem[0].cpu_base = CPCI690_PCI1_MEM_START_PROC_ADDR;
175	si.pci_1.pci_mem[0].pci_base_hi = CPCI690_PCI1_MEM_START_PCI_HI_ADDR;
176	si.pci_1.pci_mem[0].pci_base_lo = CPCI690_PCI1_MEM_START_PCI_LO_ADDR;
177	si.pci_1.pci_mem[0].size = CPCI690_PCI1_MEM_SIZE;
178	si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
179	si.pci_1.pci_cmd_bits = 0;
180	si.pci_1.latency_timer = 0x80;
181
182	for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
183		si.cpu_prot_options[i] = 0;
184		si.cpu_snoop_options[i] = GT64260_CPU_SNOOP_WB;
185		si.pci_0.acc_cntl_options[i] =
186			GT64260_PCI_ACC_CNTL_DREADEN |
187			GT64260_PCI_ACC_CNTL_RDPREFETCH |
188			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
189			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
190			GT64260_PCI_ACC_CNTL_SWAP_NONE |
191			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
192		si.pci_0.snoop_options[i] = GT64260_PCI_SNOOP_WB;
193		si.pci_1.acc_cntl_options[i] =
194			GT64260_PCI_ACC_CNTL_DREADEN |
195			GT64260_PCI_ACC_CNTL_RDPREFETCH |
196			GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |
197			GT64260_PCI_ACC_CNTL_RDMULPREFETCH |
198			GT64260_PCI_ACC_CNTL_SWAP_NONE |
199			GT64260_PCI_ACC_CNTL_MBURST_32_BTYES;
200		si.pci_1.snoop_options[i] = GT64260_PCI_SNOOP_WB;
201	}
202
203        /* Lookup PCI host bridges */
204        if (mv64x60_init(&bh, &si))
205                printk(KERN_ERR "Bridge initialization failed.\n");
206
207	pci_dram_offset = 0; /* System mem at same addr on PCI & cpu bus */
208	ppc_md.pci_swizzle = common_swizzle;
209	ppc_md.pci_map_irq = cpci690_map_irq;
210	ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
211
212	mv64x60_set_bus(&bh, 0, 0);
213	bh.hose_a->first_busno = 0;
214	bh.hose_a->last_busno = 0xff;
215	bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
216
217	bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
218	mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
219	bh.hose_b->last_busno = 0xff;
220	bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
221		bh.hose_b->first_busno);
222}
223
224static void __init
225cpci690_setup_peripherals(void)
226{
227	/* Set up windows to CPLD, RTC/TODC, IPMI. */
228	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN, CPCI690_BR_BASE,
229		CPCI690_BR_SIZE, 0);
230	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
231	cpci690_br_base = (u32)ioremap(CPCI690_BR_BASE, CPCI690_BR_SIZE);
232
233	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN, CPCI690_TODC_BASE,
234		CPCI690_TODC_SIZE, 0);
235	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
236	TODC_INIT(TODC_TYPE_MK48T35, 0, 0,
237			ioremap(CPCI690_TODC_BASE, CPCI690_TODC_SIZE), 8);
238
239	mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN, CPCI690_IPMI_BASE,
240		CPCI690_IPMI_SIZE, 0);
241	bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
242
243	mv64x60_set_bits(&bh, MV64x60_PCI0_ARBITER_CNTL, (1<<31));
244	mv64x60_set_bits(&bh, MV64x60_PCI1_ARBITER_CNTL, (1<<31));
245
246        mv64x60_set_bits(&bh, MV64x60_CPU_MASTER_CNTL, (1<<9)); /* Only 1 cpu */
247
248	/*
249	 * Turn off timer/counters.  Not turning off watchdog timer because
250	 * can't read its reg on the 64260A so don't know if we'll be enabling
251	 * or disabling.
252	 */
253	mv64x60_clr_bits(&bh, MV64x60_TIMR_CNTR_0_3_CNTL,
254			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
255	mv64x60_clr_bits(&bh, GT64260_TIMR_CNTR_4_7_CNTL,
256			((1<<0) | (1<<8) | (1<<16) | (1<<24)));
257
258	/*
259	 * Set MPSC Multiplex RMII
260	 * NOTE: ethernet driver modifies bit 0 and 1
261	 */
262	mv64x60_write(&bh, GT64260_MPP_SERIAL_PORTS_MULTIPLEX, 0x00001102);
263
264#define GPP_EXTERNAL_INTERRUPTS \
265		((1<<24) | (1<<25) | (1<<26) | (1<<27) | \
266		 (1<<28) | (1<<29) | (1<<30) | (1<<31))
267	/* PCI interrupts are inputs */
268	mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL, GPP_EXTERNAL_INTERRUPTS);
269	/* PCI interrupts are active low */
270	mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL, GPP_EXTERNAL_INTERRUPTS);
271
272	/* Clear any pending interrupts for these inputs and enable them. */
273	mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~GPP_EXTERNAL_INTERRUPTS);
274	mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK, GPP_EXTERNAL_INTERRUPTS);
275
276	/* Route MPP interrupt inputs to GPP */
277	mv64x60_write(&bh, MV64x60_MPP_CNTL_2, 0x00000000);
278	mv64x60_write(&bh, MV64x60_MPP_CNTL_3, 0x00000000);
279}
280
281static void __init
282cpci690_setup_arch(void)
283{
284	if (ppc_md.progress)
285		ppc_md.progress("cpci690_setup_arch: enter", 0);
286#ifdef CONFIG_BLK_DEV_INITRD
287	if (initrd_start)
288		ROOT_DEV = Root_RAM0;
289	else
290#endif
291#ifdef   CONFIG_ROOT_NFS
292		ROOT_DEV = Root_NFS;
293#else
294		ROOT_DEV = Root_SDA2;
295#endif
296
297	if (ppc_md.progress)
298		ppc_md.progress("cpci690_setup_arch: Enabling L2 cache", 0);
299
300	/* Enable L2 and L3 caches (if 745x) */
301	_set_L2CR(_get_L2CR() | L2CR_L2E);
302	_set_L3CR(_get_L3CR() | L3CR_L3E);
303
304	if (ppc_md.progress)
305		ppc_md.progress("cpci690_setup_arch: Initializing bridge", 0);
306
307	cpci690_setup_bridge();		/* set up PCI bridge(s) */
308	cpci690_setup_peripherals();	/* set up chip selects/GPP/MPP etc */
309
310	if (ppc_md.progress)
311		ppc_md.progress("cpci690_setup_arch: bridge init complete", 0);
312
313	printk(KERN_INFO "%s %s port (C) 2003 MontaVista Software, Inc. "
314		"(source@mvista.com)\n", BOARD_VENDOR, BOARD_MACHINE);
315
316	if (ppc_md.progress)
317		ppc_md.progress("cpci690_setup_arch: exit", 0);
318}
319
320/* Platform device data fixup routines. */
321#if defined(CONFIG_SERIAL_MPSC)
322static void __init
323cpci690_fixup_mpsc_pdata(struct platform_device *pdev)
324{
325	struct mpsc_pdata *pdata;
326
327	pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
328
329	pdata->max_idle = 40;
330	pdata->default_baud = CPCI690_MPSC_BAUD;
331	pdata->brg_clk_src = CPCI690_MPSC_CLK_SRC;
332	pdata->brg_clk_freq = CPCI690_BUS_FREQ;
333}
334
335static int __init
336cpci690_platform_notify(struct device *dev)
337{
338	static struct {
339		char	*bus_id;
340		void	((*rtn)(struct platform_device *pdev));
341	} dev_map[] = {
342		{ MPSC_CTLR_NAME ".0", cpci690_fixup_mpsc_pdata },
343		{ MPSC_CTLR_NAME ".1", cpci690_fixup_mpsc_pdata },
344	};
345	struct platform_device	*pdev;
346	int	i;
347
348	if (dev && dev->bus_id)
349		for (i=0; i<ARRAY_SIZE(dev_map); i++)
350			if (!strncmp(dev->bus_id, dev_map[i].bus_id,
351				BUS_ID_SIZE)) {
352
353				pdev = container_of(dev,
354					struct platform_device, dev);
355				dev_map[i].rtn(pdev);
356			}
357
358	return 0;
359}
360#endif
361
362static void
363cpci690_reset_board(void)
364{
365	u32	i = 10000;
366
367	local_irq_disable();
368	out_8((u8 *)(cpci690_br_base + CPCI690_BR_SW_RESET), 0x11);
369
370	while (i != 0) i++;
371	panic("restart failed\n");
372}
373
374static void
375cpci690_restart(char *cmd)
376{
377	cpci690_reset_board();
378}
379
380static void
381cpci690_halt(void)
382{
383	while (1);
384	/* NOTREACHED */
385}
386
387static void
388cpci690_power_off(void)
389{
390	cpci690_halt();
391	/* NOTREACHED */
392}
393
394static int
395cpci690_show_cpuinfo(struct seq_file *m)
396{
397	seq_printf(m, "vendor\t\t: " BOARD_VENDOR "\n");
398	seq_printf(m, "machine\t\t: " BOARD_MACHINE "\n");
399	seq_printf(m, "cpu MHz\t\t: %d\n", cpci690_get_cpu_speed()/1000/1000);
400	seq_printf(m, "bus MHz\t\t: %d\n", CPCI690_BUS_FREQ/1000/1000);
401
402	return 0;
403}
404
405static void __init
406cpci690_calibrate_decr(void)
407{
408	ulong freq;
409
410	freq = CPCI690_BUS_FREQ / 4;
411
412	printk(KERN_INFO "time_init: decrementer frequency = %lu.%.6lu MHz\n",
413	       freq/1000000, freq%1000000);
414
415	tb_ticks_per_jiffy = freq / HZ;
416	tb_to_us = mulhwu_scale_factor(freq, 1000000);
417}
418
419static __inline__ void
420cpci690_set_bat(u32 addr, u32 size)
421{
422	addr &= 0xfffe0000;
423	size &= 0x1ffe0000;
424	size = ((size >> 17) - 1) << 2;
425
426	mb();
427	mtspr(SPRN_DBAT1U, addr | size | 0x2); /* Vs == 1; Vp == 0 */
428	mtspr(SPRN_DBAT1L, addr | 0x2a); /* WIMG bits == 0101; PP == r/w access */
429	mb();
430}
431
432#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
433static void __init
434cpci690_map_io(void)
435{
436	io_block_mapping(CONFIG_MV64X60_NEW_BASE, CONFIG_MV64X60_NEW_BASE,
437		128 * KB, _PAGE_IO);
438}
439#endif
440
441void __init
442platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
443	      unsigned long r6, unsigned long r7)
444{
445#ifdef CONFIG_BLK_DEV_INITRD
446	initrd_start=initrd_end=0;
447	initrd_below_start_ok=0;
448#endif /* CONFIG_BLK_DEV_INITRD */
449
450	parse_bootinfo(find_bootinfo());
451
452	loops_per_jiffy = cpci690_get_cpu_speed() / HZ;
453
454	isa_mem_base = 0;
455
456	ppc_md.setup_arch = cpci690_setup_arch;
457	ppc_md.show_cpuinfo = cpci690_show_cpuinfo;
458	ppc_md.init_IRQ = gt64260_init_irq;
459	ppc_md.get_irq = gt64260_get_irq;
460	ppc_md.restart = cpci690_restart;
461	ppc_md.power_off = cpci690_power_off;
462	ppc_md.halt = cpci690_halt;
463	ppc_md.find_end_of_memory = cpci690_find_end_of_memory;
464	ppc_md.time_init = todc_time_init;
465	ppc_md.set_rtc_time = todc_set_rtc_time;
466	ppc_md.get_rtc_time = todc_get_rtc_time;
467	ppc_md.nvram_read_val = todc_direct_read_val;
468	ppc_md.nvram_write_val = todc_direct_write_val;
469	ppc_md.calibrate_decr = cpci690_calibrate_decr;
470
471	/*
472	 * Need to map in board regs (used by cpci690_find_end_of_memory())
473	 * and the bridge's regs (used by progress);
474	 */
475	cpci690_set_bat(CPCI690_BR_BASE, 32 * MB);
476	cpci690_br_base = CPCI690_BR_BASE;
477
478#ifdef	CONFIG_SERIAL_TEXT_DEBUG
479	ppc_md.setup_io_mappings = cpci690_map_io;
480	ppc_md.progress = mv64x60_mpsc_progress;
481	mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
482#endif	/* CONFIG_SERIAL_TEXT_DEBUG */
483#ifdef	CONFIG_KGDB
484	ppc_md.setup_io_mappings = cpci690_map_io;
485	ppc_md.early_serial_map = cpci690_early_serial_map;
486#endif	/* CONFIG_KGDB */
487
488#if defined(CONFIG_SERIAL_MPSC)
489	platform_notify = cpci690_platform_notify;
490#endif
491}