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/arch/ppc/platforms/chestnut.h

https://bitbucket.org/evzijst/gittest
C Header | 129 lines | 67 code | 18 blank | 44 comment | 0 complexity | 891a1fa3c1b0d7f6712e50067e4ed930 MD5 | raw file
  1/*
  2 * arch/ppc/platforms/chestnut.h
  3 *
  4 * Definitions for IBM 750FXGX Eval (Chestnut)
  5 *
  6 * Author: <source@mvista.com>
  7 *
  8 * Based on Artesyn Katana code done by Tim Montgomery <timm@artesyncp.com>
  9 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
 10 * Based on code done by Mark A. Greer <mgreer@mvista.com>
 11 *
 12 * <2004> (c) MontaVista Software, Inc. This file is licensed under
 13 * the terms of the GNU General Public License version 2. This program
 14 * is licensed "as is" without any warranty of any kind, whether express
 15 * or implied.
 16 */
 17
 18/*
 19 * This is the CPU physical memory map (windows must be at least 1MB and start
 20 * on a boundary that is a multiple of the window size):
 21 *
 22 * Seems on the IBM 750FXGX Eval board, the MV64460 Registers can be in
 23 * only 2 places per switch U17 0x14000000 or 0xf1000000 easily - chose to
 24 * implement at 0xf1000000 only at this time
 25 *
 26 *    0xfff00000-0xffffffff      - 8 Flash
 27 *    0xffe00000-0xffefffff      - BOOT SRAM
 28 *    0xffd00000-0xffd00004      - CPLD
 29 *    0xffc00000-0xffc0000f      - UART
 30 *    0xffb00000-0xffb07fff      - FRAM
 31 *    0xff840000-0xffafffff      - *** HOLE ***
 32 *    0xff800000-0xff83ffff      - MV64460 Integrated SRAM
 33 *    0xfe000000-0xff8fffff      - *** HOLE ***
 34 *    0xfc000000-0xfdffffff      - 32bit Flash
 35 *    0xf1010000-0xfbffffff      - *** HOLE ***
 36 *    0xf1000000-0xf100ffff      - MV64460 Registers
 37 */
 38
 39#ifndef __PPC_PLATFORMS_CHESTNUT_H__
 40#define __PPC_PLATFORMS_CHESTNUT_H__
 41
 42#define CHESTNUT_BOOT_8BIT_BASE			0xfff00000
 43#define CHESTNUT_BOOT_8BIT_SIZE_ACTUAL		(1024*1024)
 44#define CHESTNUT_BOOT_SRAM_BASE			0xffe00000
 45#define CHESTNUT_BOOT_SRAM_SIZE_ACTUAL		(1024*1024)
 46#define CHESTNUT_CPLD_BASE			0xffd00000
 47#define CHESTNUT_CPLD_SIZE_ACTUAL		5
 48#define CHESTNUT_CPLD_REG3			(CHESTNUT_CPLD_BASE+3)
 49#define CHESTNUT_UART_BASE			0xffc00000
 50#define CHESTNUT_UART_SIZE_ACTUAL		16
 51#define CHESTNUT_FRAM_BASE			0xffb00000
 52#define CHESTNUT_FRAM_SIZE_ACTUAL		(32*1024)
 53#define CHESTNUT_INTERNAL_SRAM_BASE		0xff800000
 54#define CHESTNUT_32BIT_BASE			0xfc000000
 55#define CHESTNUT_32BIT_SIZE			(32*1024*1024)
 56
 57#define CHESTNUT_BOOT_8BIT_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
 58					CHESTNUT_BOOT_8BIT_SIZE_ACTUAL)
 59#define CHESTNUT_BOOT_SRAM_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
 60					CHESTNUT_BOOT_SRAM_SIZE_ACTUAL)
 61#define CHESTNUT_CPLD_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
 62					CHESTNUT_CPLD_SIZE_ACTUAL)
 63#define CHESTNUT_UART_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
 64					CHESTNUT_UART_SIZE_ACTUAL)
 65#define CHESTNUT_FRAM_SIZE		max(MV64360_WINDOW_SIZE_MIN, \
 66					CHESTNUT_FRAM_SIZE_ACTUAL)
 67
 68#define CHESTNUT_BUS_SPEED		200000000
 69#define CHESTNUT_PIBS_DATABASE		0xf0000 /* from PIBS src code */
 70
 71#define	KATANA_ETH0_PHY_ADDR			12
 72#define	KATANA_ETH1_PHY_ADDR			11
 73#define	KATANA_ETH2_PHY_ADDR			4
 74
 75#define CHESTNUT_ETH_TX_QUEUE_SIZE		800
 76#define CHESTNUT_ETH_RX_QUEUE_SIZE		400
 77
 78/*
 79 * PCI windows
 80 */
 81
 82#define CHESTNUT_PCI0_MEM_PROC_ADDR	0x80000000
 83#define CHESTNUT_PCI0_MEM_PCI_HI_ADDR	0x00000000
 84#define CHESTNUT_PCI0_MEM_PCI_LO_ADDR	0x80000000
 85#define CHESTNUT_PCI0_MEM_SIZE		0x10000000
 86#define CHESTNUT_PCI0_IO_PROC_ADDR	0xa0000000
 87#define CHESTNUT_PCI0_IO_PCI_ADDR	0x00000000
 88#define CHESTNUT_PCI0_IO_SIZE		0x01000000
 89
 90/*
 91 * Board-specific IRQ info
 92 */
 93#define CHESTNUT_PCI_SLOT0_IRQ	(64 + 31)
 94#define CHESTNUT_PCI_SLOT1_IRQ	(64 + 30)
 95#define CHESTNUT_PCI_SLOT2_IRQ	(64 + 29)
 96#define CHESTNUT_PCI_SLOT3_IRQ	(64 + 28)
 97
 98/* serial port definitions */
 99#define CHESTNUT_UART0_IO_BASE  (CHESTNUT_UART_BASE + 8)
100#define CHESTNUT_UART1_IO_BASE  CHESTNUT_UART_BASE
101
102#define UART0_INT           	(64 + 25)
103#define UART1_INT        	(64 + 26)
104
105#ifdef CONFIG_SERIAL_MANY_PORTS
106#define RS_TABLE_SIZE  64
107#else
108#define RS_TABLE_SIZE  2
109#endif
110
111/* Rate for the 3.6864 Mhz clock for the onboard serial chip */
112#define BASE_BAUD 		(3686400 / 16)
113
114#ifdef CONFIG_SERIAL_DETECT_IRQ
115#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ)
116#else
117#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST)
118#endif
119
120#define STD_UART_OP(num)						\
121        { 0, BASE_BAUD, 0, UART##num##_INT, STD_COM_FLAGS,		\
122                iomem_base: (u8 *)CHESTNUT_UART##num##_IO_BASE,	\
123		io_type: SERIAL_IO_MEM},
124
125#define SERIAL_PORT_DFNS        \
126        STD_UART_OP(0)          \
127        STD_UART_OP(1)
128
129#endif /* __PPC_PLATFORMS_CHESTNUT_H__ */