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/arch/ppc/platforms/85xx/stx_gp3.h

https://bitbucket.org/evzijst/gittest
C Header | 74 lines | 42 code | 14 blank | 18 comment | 0 complexity | c332e61746c08243f9603751252d1346 MD5 | raw file
 1/*
 2 * arch/ppc/platforms/stx8560_gp3.h
 3 *
 4 * STx GP3 board definitions
 5 *
 6 * Dan Malek (dan@embeddededge.com)
 7 * Copyright 2004 Embedded Edge, LLC
 8 *
 9 * Ported to 2.6, Matt Porter <mporter@kernel.crashing.org>
10 * Copyright 2004-2005 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute  it and/or modify it
13 * under  the terms of  the GNU General  Public License as published by the
14 * Free Software Foundation;  either version 2 of the  License, or (at your
15 * option) any later version.
16 *
17 */
18
19#ifndef __MACH_STX_GP3_H
20#define __MACH_STX_GP3_H
21
22#include <linux/config.h>
23#include <linux/init.h>
24#include <linux/seq_file.h>
25#include <asm/ppcboot.h>
26
27#define BOARD_CCSRBAR		((uint)0xe0000000)
28#define CCSRBAR_SIZE		((uint)1024*1024)
29
30#define CPM_MAP_ADDR		(CCSRBAR + MPC85xx_CPM_OFFSET)
31
32#define BCSR_ADDR		((uint)0xfc000000)
33#define BCSR_SIZE		((uint)(16 * 1024))
34
35#define BCSR_TSEC1_RESET	0x00000080
36#define BCSR_TSEC2_RESET	0x00000040
37#define BCSR_LED1		0x00000008
38#define BCSR_LED2		0x00000004
39#define BCSR_LED3		0x00000002
40#define BCSR_LED4		0x00000001
41
42extern void mpc85xx_setup_hose(void) __init;
43extern void mpc85xx_restart(char *cmd);
44extern void mpc85xx_power_off(void);
45extern void mpc85xx_halt(void);
46extern int mpc85xx_show_cpuinfo(struct seq_file *m);
47extern void mpc85xx_init_IRQ(void) __init;
48extern unsigned long mpc85xx_find_end_of_memory(void) __init;
49extern void mpc85xx_calibrate_decr(void) __init;
50
51#define PCI_CFG_ADDR_OFFSET	(0x8000)
52#define PCI_CFG_DATA_OFFSET	(0x8004)
53
54/* PCI interrupt controller */
55#define PIRQA		MPC85xx_IRQ_EXT1
56#define PIRQB		MPC85xx_IRQ_EXT2
57#define PIRQC		MPC85xx_IRQ_EXT3
58#define PIRQD		MPC85xx_IRQ_EXT4
59#define PCI_MIN_IDSEL	16
60#define PCI_MAX_IDSEL	19
61#define PCI_IRQ_SLOT	4
62
63#define MPC85XX_PCI1_LOWER_IO	0x00000000
64#define MPC85XX_PCI1_UPPER_IO	0x00ffffff
65
66#define MPC85XX_PCI1_LOWER_MEM	0x80000000
67#define MPC85XX_PCI1_UPPER_MEM	0x9fffffff
68
69#define MPC85XX_PCI1_IO_BASE	0xe2000000
70#define MPC85XX_PCI1_MEM_OFFSET	0x00000000
71
72#define MPC85XX_PCI1_IO_SIZE	0x01000000
73
74#endif /* __MACH_STX_GP3_H */