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/arch/ppc/platforms/85xx/sbc85xx.h

https://bitbucket.org/evzijst/gittest
C Header | 55 lines | 28 code | 12 blank | 15 comment | 0 complexity | 12eea52e3c8f21ea0ca7439b1633cf92 MD5 | raw file
 1/*
 2 * arch/ppc/platforms/85xx/sbc85xx.h
 3 *
 4 * WindRiver PowerQUICC III SBC85xx common board definitions
 5 *
 6 * Copyright 2003 Motorola Inc.
 7 * Copyright 2004 Red Hat, Inc.
 8 *
 9 * This program is free software; you can redistribute  it and/or modify it
10 * under  the terms of  the GNU General  Public License as published by the
11 * Free Software Foundation;  either version 2 of the  License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __PLATFORMS_85XX_SBC85XX_H__
17#define __PLATFORMS_85XX_SBC85XX_H__
18
19#include <linux/config.h>
20#include <linux/init.h>
21#include <linux/seq_file.h>
22#include <asm/ppcboot.h>
23
24#define BOARD_CCSRBAR		((uint)0xff700000)
25#define CCSRBAR_SIZE		((uint)1024*1024)
26
27#define BCSR_ADDR		((uint)0xfc000000)
28#define BCSR_SIZE		((uint)(16 * 1024 * 1024))
29
30#define UARTA_ADDR		(BCSR_ADDR + 0x00700000)
31#define UARTB_ADDR		(BCSR_ADDR + 0x00800000)
32#define RTC_DEVICE_ADDR		(BCSR_ADDR + 0x00900000)
33#define EEPROM_ADDR		(BCSR_ADDR + 0x00b00000)
34
35extern int  sbc8560_show_cpuinfo(struct seq_file *m);
36extern void sbc8560_init_IRQ(void) __init; 
37
38/* PCI interrupt controller */
39#define PIRQA		MPC85xx_IRQ_EXT1
40#define PIRQB		MPC85xx_IRQ_EXT2
41#define PIRQC		MPC85xx_IRQ_EXT3
42#define PIRQD		MPC85xx_IRQ_EXT4
43
44#define MPC85XX_PCI1_LOWER_IO	0x00000000
45#define MPC85XX_PCI1_UPPER_IO	0x00ffffff
46
47#define MPC85XX_PCI1_LOWER_MEM	0x80000000
48#define MPC85XX_PCI1_UPPER_MEM	0x9fffffff
49
50#define MPC85XX_PCI1_IO_BASE	0xe2000000
51#define MPC85XX_PCI1_MEM_OFFSET	0x00000000
52
53#define MPC85XX_PCI1_IO_SIZE	0x01000000
54
55#endif /* __PLATFORMS_85XX_SBC85XX_H__ */