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/arch/ppc/platforms/4xx/sycamore.c

https://bitbucket.org/evzijst/gittest
C | 278 lines | 185 code | 40 blank | 53 comment | 5 complexity | d82bb552b3e58f23c9fea9df468dda19 MD5 | raw file
  1/*
  2 * arch/ppc/platforms/4xx/sycamore.c
  3 *
  4 * Architecture- / platform-specific boot-time initialization code for
  5 * IBM PowerPC 4xx based boards.
  6 *
  7 * Author: Armin Kuster <akuster@mvista.com>
  8 *
  9 * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
 10 * the terms of the GNU General Public License version 2.  This program
 11 * is licensed "as is" without any warranty of any kind, whether express
 12 * or implied.
 13 */
 14#include <linux/config.h>
 15#include <linux/init.h>
 16#include <linux/smp.h>
 17#include <linux/threads.h>
 18#include <linux/param.h>
 19#include <linux/string.h>
 20#include <linux/pci.h>
 21#include <linux/rtc.h>
 22
 23#include <asm/ocp.h>
 24#include <asm/ppc4xx_pic.h>
 25#include <asm/system.h>
 26#include <asm/pci-bridge.h>
 27#include <asm/machdep.h>
 28#include <asm/page.h>
 29#include <asm/time.h>
 30#include <asm/io.h>
 31#include <asm/ibm_ocp_pci.h>
 32#include <asm/todc.h>
 33
 34#undef DEBUG
 35
 36#ifdef DEBUG
 37#define DBG(x...) printk(x)
 38#else
 39#define DBG(x...)
 40#endif
 41
 42void *kb_cs;
 43void *kb_data;
 44void *sycamore_rtc_base;
 45
 46/*
 47 * Define external IRQ senses and polarities.
 48 */
 49unsigned char ppc4xx_uic_ext_irq_cfg[] __initdata = {
 50	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 7 */
 51	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 8 */
 52	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 9 */
 53	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 10 */
 54	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 11 */
 55	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 12 */
 56	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 0 */
 57	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 1 */
 58	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 2 */
 59	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 3 */
 60	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 4 */
 61	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 5 */
 62	(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),	/* Ext Int 6 */
 63};
 64
 65
 66/* Some IRQs unique to Sycamore.
 67 * Used by the generic 405 PCI setup functions in ppc4xx_pci.c
 68 */
 69int __init
 70ppc405_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 71{
 72	static char pci_irq_table[][4] =
 73	    /*
 74	     *      PCI IDSEL/INTPIN->INTLINE
 75	     *      A       B       C       D
 76	     */
 77	{
 78		{28, 28, 28, 28},	/* IDSEL 1 - PCI slot 1 */
 79		{29, 29, 29, 29},	/* IDSEL 2 - PCI slot 2 */
 80		{30, 30, 30, 30},	/* IDSEL 3 - PCI slot 3 */
 81		{31, 31, 31, 31},	/* IDSEL 4 - PCI slot 4 */
 82	};
 83
 84	const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 85	return PCI_IRQ_TABLE_LOOKUP;
 86};
 87
 88void __init
 89sycamore_setup_arch(void)
 90{
 91#define SYCAMORE_PS2_BASE	0xF0100000
 92#define SYCAMORE_FPGA_BASE	0xF0300000
 93
 94	void *fpga_brdc;
 95	unsigned char fpga_brdc_data;
 96	void *fpga_enable;
 97	void *fpga_polarity;
 98	void *fpga_status;
 99	void *fpga_trigger;
100
101	ppc4xx_setup_arch();
102
103	ibm_ocp_set_emac(0, 1);
104
105	kb_data = ioremap(SYCAMORE_PS2_BASE, 8);
106	if (!kb_data) {
107		printk(KERN_CRIT
108		       "sycamore_setup_arch() kb_data ioremap failed\n");
109		return;
110	}
111
112	kb_cs = kb_data + 1;
113
114	fpga_status = ioremap(SYCAMORE_FPGA_BASE, 8);
115	if (!fpga_status) {
116		printk(KERN_CRIT
117		       "sycamore_setup_arch() fpga_status ioremap failed\n");
118		return;
119	}
120
121	fpga_enable = fpga_status + 1;
122	fpga_polarity = fpga_status + 2;
123	fpga_trigger = fpga_status + 3;
124	fpga_brdc = fpga_status + 4;
125
126	/* split the keyboard and mouse interrupts */
127	fpga_brdc_data = readb(fpga_brdc);
128	fpga_brdc_data |= 0x80;
129	writeb(fpga_brdc_data, fpga_brdc);
130
131	writeb(0x3, fpga_enable);
132
133	writeb(0x3, fpga_polarity);
134
135	writeb(0x3, fpga_trigger);
136
137	/* RTC step for the sycamore */
138	sycamore_rtc_base = (void *) SYCAMORE_RTC_VADDR;
139	TODC_INIT(TODC_TYPE_DS1743, sycamore_rtc_base, sycamore_rtc_base,
140		  sycamore_rtc_base, 8);
141
142	/* Identify the system */
143	printk(KERN_INFO "IBM Sycamore (IBM405GPr) Platform\n");
144	printk(KERN_INFO
145	       "Port by MontaVista Software, Inc. (source@mvista.com)\n");
146}
147
148void __init
149bios_fixup(struct pci_controller *hose, struct pcil0_regs *pcip)
150{
151#ifdef CONFIG_PCI
152	unsigned int bar_response, bar;
153	/*
154	 * Expected PCI mapping:
155	 *
156	 *  PLB addr             PCI memory addr
157	 *  ---------------------       ---------------------
158	 *  0000'0000 - 7fff'ffff <---  0000'0000 - 7fff'ffff
159	 *  8000'0000 - Bfff'ffff --->  8000'0000 - Bfff'ffff
160	 *
161	 *  PLB addr             PCI io addr
162	 *  ---------------------       ---------------------
163	 *  e800'0000 - e800'ffff --->  0000'0000 - 0001'0000
164	 *
165	 * The following code is simplified by assuming that the bootrom
166	 * has been well behaved in following this mapping.
167	 */
168
169#ifdef DEBUG
170	int i;
171
172	printk("ioremap PCLIO_BASE = 0x%x\n", pcip);
173	printk("PCI bridge regs before fixup \n");
174	for (i = 0; i <= 3; i++) {
175		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
176		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
177		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
178		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
179	}
180	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
181	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
182	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
183	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
184
185#endif
186
187	/* added for IBM boot rom version 1.15 bios bar changes  -AK */
188
189	/* Disable region first */
190	out_le32((void *) &(pcip->pmm[0].ma), 0x00000000);
191	/* PLB starting addr, PCI: 0x80000000 */
192	out_le32((void *) &(pcip->pmm[0].la), 0x80000000);
193	/* PCI start addr, 0x80000000 */
194	out_le32((void *) &(pcip->pmm[0].pcila), PPC405_PCI_MEM_BASE);
195	/* 512MB range of PLB to PCI */
196	out_le32((void *) &(pcip->pmm[0].pciha), 0x00000000);
197	/* Enable no pre-fetch, enable region */
198	out_le32((void *) &(pcip->pmm[0].ma), ((0xffffffff -
199						(PPC405_PCI_UPPER_MEM -
200						 PPC405_PCI_MEM_BASE)) | 0x01));
201
202	/* Enable inbound region one - 1GB size */
203	out_le32((void *) &(pcip->ptm1ms), 0xc0000001);
204
205	/* Disable outbound region one */
206	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
207	out_le32((void *) &(pcip->pmm[1].la), 0x00000000);
208	out_le32((void *) &(pcip->pmm[1].pcila), 0x00000000);
209	out_le32((void *) &(pcip->pmm[1].pciha), 0x00000000);
210	out_le32((void *) &(pcip->pmm[1].ma), 0x00000000);
211
212	/* Disable inbound region two */
213	out_le32((void *) &(pcip->ptm2ms), 0x00000000);
214
215	/* Disable outbound region two */
216	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
217	out_le32((void *) &(pcip->pmm[2].la), 0x00000000);
218	out_le32((void *) &(pcip->pmm[2].pcila), 0x00000000);
219	out_le32((void *) &(pcip->pmm[2].pciha), 0x00000000);
220	out_le32((void *) &(pcip->pmm[2].ma), 0x00000000);
221
222	/* Zero config bars */
223	for (bar = PCI_BASE_ADDRESS_1; bar <= PCI_BASE_ADDRESS_2; bar += 4) {
224		early_write_config_dword(hose, hose->first_busno,
225					 PCI_FUNC(hose->first_busno), bar,
226					 0x00000000);
227		early_read_config_dword(hose, hose->first_busno,
228					PCI_FUNC(hose->first_busno), bar,
229					&bar_response);
230		DBG("BUS %d, device %d, Function %d bar 0x%8.8x is 0x%8.8x\n",
231		    hose->first_busno, PCI_SLOT(hose->first_busno),
232		    PCI_FUNC(hose->first_busno), bar, bar_response);
233	}
234	/* end work arround */
235
236#ifdef DEBUG
237	printk("PCI bridge regs after fixup \n");
238	for (i = 0; i <= 3; i++) {
239		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].ma)));
240		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].la)));
241		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pcila)));
242		printk(" pmm%dma\t0x%x\n", i, in_le32(&(pcip->pmm[i].pciha)));
243	}
244	printk(" ptm1ms\t0x%x\n", in_le32(&(pcip->ptm1ms)));
245	printk(" ptm1la\t0x%x\n", in_le32(&(pcip->ptm1la)));
246	printk(" ptm2ms\t0x%x\n", in_le32(&(pcip->ptm2ms)));
247	printk(" ptm2la\t0x%x\n", in_le32(&(pcip->ptm2la)));
248
249#endif
250#endif
251
252}
253
254void __init
255sycamore_map_io(void)
256{
257	ppc4xx_map_io();
258	io_block_mapping(SYCAMORE_RTC_VADDR,
259			 SYCAMORE_RTC_PADDR, SYCAMORE_RTC_SIZE, _PAGE_IO);
260}
261
262void __init
263platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
264	      unsigned long r6, unsigned long r7)
265{
266	ppc4xx_init(r3, r4, r5, r6, r7);
267
268	ppc_md.setup_arch = sycamore_setup_arch;
269	ppc_md.setup_io_mappings = sycamore_map_io;
270
271#ifdef CONFIG_GEN_RTC
272	ppc_md.time_init = todc_time_init;
273	ppc_md.set_rtc_time = todc_set_rtc_time;
274	ppc_md.get_rtc_time = todc_get_rtc_time;
275	ppc_md.nvram_read_val = todc_direct_read_val;
276	ppc_md.nvram_write_val = todc_direct_write_val;
277#endif
278}