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/arch/ppc/platforms/4xx/ibmstb4.h

https://bitbucket.org/evzijst/gittest
C Header | 238 lines | 182 code | 27 blank | 29 comment | 0 complexity | f81da1efdaca23f80088e4ea6d69be1c MD5 | raw file
  1/*
  2 * arch/ppc/platforms/4xx/ibmstb4.h
  3 *
  4 * Author: Armin Kuster <akuster@mvista.com>
  5 *
  6 * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
  7 * the terms of the GNU General Public License version 2.  This program
  8 * is licensed "as is" without any warranty of any kind, whether express
  9 * or implied.
 10 */
 11
 12#ifdef __KERNEL__
 13#ifndef __ASM_IBMSTB4_H__
 14#define __ASM_IBMSTB4_H__
 15
 16#include <linux/config.h>
 17
 18/* serial port defines */
 19#define STB04xxx_IO_BASE	((uint)0xe0000000)
 20#define PPC4xx_PCI_IO_ADDR	STB04xxx_IO_BASE
 21#define PPC4xx_ONB_IO_PADDR	STB04xxx_IO_BASE
 22#define PPC4xx_ONB_IO_VADDR	((uint)0xe0000000)
 23#define PPC4xx_ONB_IO_SIZE	((uint)14*64*1024)
 24
 25/*
 26 * map STB04xxx internal i/o address (0x400x00xx) to an address
 27 * which is below the 2GB limit...
 28 *
 29 * 4000 000x	uart1		-> 0xe000 000x
 30 * 4001 00xx	ppu
 31 * 4002 00xx	smart card
 32 * 4003 000x	iic
 33 * 4004 000x	uart0
 34 * 4005 0xxx	timer
 35 * 4006 00xx	gpio
 36 * 4007 00xx	smart card
 37 * 400b 000x	iic
 38 * 400c 000x	scp
 39 * 400d 000x	modem
 40 * 400e 000x	uart2
 41*/
 42#define STB04xxx_MAP_IO_ADDR(a)	(((uint)(a)) + (STB04xxx_IO_BASE - 0x40000000))
 43
 44#define RS_TABLE_SIZE		3
 45#define UART0_INT		20
 46
 47#ifdef __BOOTER__
 48#define UART0_IO_BASE		0x40040000
 49#else
 50#define UART0_IO_BASE		0xe0040000
 51#endif
 52
 53#define UART1_INT		21
 54
 55#ifdef __BOOTER__
 56#define UART1_IO_BASE		0x40000000
 57#else
 58#define UART1_IO_BASE		0xe0000000
 59#endif
 60
 61#define UART2_INT		31
 62#ifdef __BOOTER__
 63#define UART2_IO_BASE		0x400e0000
 64#else
 65#define UART2_IO_BASE		0xe00e0000
 66#endif
 67
 68#define IDE0_BASE	0x400F0000
 69#define IDE0_SIZE	0x200
 70#define IDE0_IRQ	25
 71#define IIC0_BASE	0x40030000
 72#define IIC1_BASE	0x400b0000
 73#define OPB0_BASE	0x40000000
 74#define GPIO0_BASE	0x40060000
 75
 76#define USB0_IRQ	18
 77#define USB0_BASE	STB04xxx_MAP_IO_ADDR(0x40010000)
 78#define USB0_EXTENT 4096
 79
 80#define IIC_NUMS 2
 81#define UART_NUMS	3
 82#define IIC0_IRQ	9
 83#define IIC1_IRQ	10
 84#define IIC_OWN		0x55
 85#define IIC_CLOCK	50
 86
 87#define BD_EMAC_ADDR(e,i) bi_enetaddr[i]
 88
 89#define STD_UART_OP(num)					\
 90	{ 0, BASE_BAUD, 0, UART##num##_INT,			\
 91		(ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST),	\
 92		iomem_base: (u8 *)UART##num##_IO_BASE,		\
 93		io_type: SERIAL_IO_MEM},
 94
 95#if defined(CONFIG_UART0_TTYS0)
 96#define SERIAL_DEBUG_IO_BASE	UART0_IO_BASE
 97#define SERIAL_PORT_DFNS	\
 98	STD_UART_OP(0)		\
 99	STD_UART_OP(1)		\
100	STD_UART_OP(2)
101#endif
102
103#if defined(CONFIG_UART0_TTYS1)
104#define SERIAL_DEBUG_IO_BASE	UART2_IO_BASE
105#define SERIAL_PORT_DFNS	\
106	STD_UART_OP(1)		\
107	STD_UART_OP(0)		\
108	STD_UART_OP(2)
109#endif
110
111#if defined(CONFIG_UART0_TTYS2)
112#define SERIAL_DEBUG_IO_BASE	UART2_IO_BASE
113#define SERIAL_PORT_DFNS	\
114	STD_UART_OP(2)		\
115	STD_UART_OP(0)		\
116	STD_UART_OP(1)
117#endif
118
119#define DCRN_BE_BASE		0x090
120#define DCRN_DMA0_BASE		0x0C0
121#define DCRN_DMA1_BASE		0x0C8
122#define DCRN_DMA2_BASE		0x0D0
123#define DCRN_DMA3_BASE		0x0D8
124#define DCRNCAP_DMA_CC		1	/* have DMA chained count capability */
125#define DCRN_DMASR_BASE		0x0E0
126#define DCRN_PLB0_BASE		0x054
127#define DCRN_PLB1_BASE		0x064
128#define DCRN_POB0_BASE		0x0B0
129#define DCRN_SCCR_BASE		0x120
130#define DCRN_UIC0_BASE		0x040
131#define DCRN_BE_BASE		0x090
132#define DCRN_DMA0_BASE		0x0C0
133#define DCRN_DMA1_BASE		0x0C8
134#define DCRN_DMA2_BASE		0x0D0
135#define DCRN_DMA3_BASE		0x0D8
136#define DCRN_CIC_BASE 		0x030
137#define DCRN_DMASR_BASE		0x0E0
138#define DCRN_EBIMC_BASE		0x070
139#define DCRN_DCRX_BASE		0x020
140#define DCRN_CPMFR_BASE		0x102
141#define DCRN_SCCR_BASE		0x120
142#define UIC0 DCRN_UIC0_BASE
143
144#define IBM_CPM_IIC0	0x80000000	/* IIC 0 interface */
145#define IBM_CPM_USB0	0x40000000	/* IEEE-1284 */
146#define IBM_CPM_IIC1	0x20000000	/* IIC 1 interface */
147#define IBM_CPM_CPU	0x10000000	/* PPC405B3 clock control */
148#define IBM_CPM_AUD	0x08000000	/* Audio Decoder */
149#define IBM_CPM_EBIU	0x04000000	/* External Bus Interface Unit */
150#define IBM_CPM_SDRAM1	0x02000000	/* SDRAM 1 memory controller */
151#define IBM_CPM_DMA	0x01000000	/* DMA controller */
152#define IBM_CPM_DMA1	0x00800000	/* reserved */
153#define IBM_CPM_XPT1	0x00400000	/* reserved */
154#define IBM_CPM_XPT2	0x00200000	/* reserved */
155#define IBM_CPM_UART1	0x00100000	/* Serial 1 / Infrared */
156#define IBM_CPM_UART0	0x00080000	/* Serial 0 / 16550 */
157#define IBM_CPM_EPI	0x00040000	/* DCR Extension */
158#define IBM_CPM_SC0	0x00020000	/* Smart Card 0 */
159#define IBM_CPM_VID	0x00010000	/* reserved */
160#define IBM_CPM_SC1	0x00008000	/* Smart Card 1 */
161#define IBM_CPM_USBSDRA	0x00004000	/* SDRAM 0 memory controller */
162#define IBM_CPM_XPT0	0x00002000	/* Transport - 54 Mhz */
163#define IBM_CPM_CBS	0x00001000	/* Cross Bar Switch */
164#define IBM_CPM_GPT	0x00000800	/* GPTPWM */
165#define IBM_CPM_GPIO0	0x00000400	/* General Purpose IO 0 */
166#define IBM_CPM_DENC	0x00000200	/* Digital video Encoder */
167#define IBM_CPM_TMRCLK	0x00000100	/* CPU timers */
168#define IBM_CPM_XPT27	0x00000080	/* Transport - 27 Mhz */
169#define IBM_CPM_UIC	0x00000040	/* Universal Interrupt Controller */
170#define IBM_CPM_SSP	0x00000010	/* Modem Serial Interface (SSP) */
171#define IBM_CPM_UART2	0x00000008	/* Serial Control Port */
172#define IBM_CPM_DDIO	0x00000004	/* Descrambler */
173#define IBM_CPM_VID2	0x00000002	/* Video Decoder clock domain 2 */
174
175#define DFLT_IBM4xx_PM	~(IBM_CPM_CPU | IBM_CPM_EBIU | IBM_CPM_SDRAM1 \
176			| IBM_CPM_DMA | IBM_CPM_DMA1 | IBM_CPM_CBS \
177			| IBM_CPM_USBSDRA | IBM_CPM_XPT0 | IBM_CPM_TMRCLK \
178			| IBM_CPM_XPT27 | IBM_CPM_UIC )
179
180#define DCRN_BEAR	(DCRN_BE_BASE + 0x0)	/* Bus Error Address Register */
181#define DCRN_BESR	(DCRN_BE_BASE + 0x1)	/* Bus Error Syndrome Register */
182/* DCRN_BESR */
183#define BESR_DSES	0x80000000	/* Data-Side Error Status */
184#define BESR_DMES	0x40000000	/* DMA Error Status */
185#define BESR_RWS	0x20000000	/* Read/Write Status */
186#define BESR_ETMASK	0x1C000000	/* Error Type */
187#define ET_PROT		0
188#define ET_PARITY	1
189#define ET_NCFG		2
190#define ET_BUSERR	4
191#define ET_BUSTO	6
192
193#define CHR1_CETE	0x00800000	/* CPU external timer enable */
194#define CHR1_PCIPW	0x00008000	/* PCI Int enable/Peripheral Write enable */
195
196#define DCRN_CICCR	(DCRN_CIC_BASE + 0x0)	/* CIC Control Register */
197#define DCRN_DMAS1	(DCRN_CIC_BASE + 0x1)	/* DMA Select1 Register */
198#define DCRN_DMAS2	(DCRN_CIC_BASE + 0x2)	/* DMA Select2 Register */
199#define DCRN_CICVCR	(DCRN_CIC_BASE + 0x3)	/* CIC Video COntro Register */
200#define DCRN_CICSEL3	(DCRN_CIC_BASE + 0x5)	/* CIC Select 3 Register */
201#define DCRN_SGPO	(DCRN_CIC_BASE + 0x6)	/* CIC GPIO Output Register */
202#define DCRN_SGPOD	(DCRN_CIC_BASE + 0x7)	/* CIC GPIO OD Register */
203#define DCRN_SGPTC	(DCRN_CIC_BASE + 0x8)	/* CIC GPIO Tristate Ctrl Reg */
204#define DCRN_SGPI	(DCRN_CIC_BASE + 0x9)	/* CIC GPIO Input Reg */
205
206#define DCRN_DCRXICR	(DCRN_DCRX_BASE + 0x0)	/* Internal Control Register */
207#define DCRN_DCRXISR	(DCRN_DCRX_BASE + 0x1)	/* Internal Status Register */
208#define DCRN_DCRXECR	(DCRN_DCRX_BASE + 0x2)	/* External Control Register */
209#define DCRN_DCRXESR	(DCRN_DCRX_BASE + 0x3)	/* External Status Register */
210#define DCRN_DCRXTAR	(DCRN_DCRX_BASE + 0x4)	/* Target Address Register */
211#define DCRN_DCRXTDR	(DCRN_DCRX_BASE + 0x5)	/* Target Data Register */
212#define DCRN_DCRXIGR	(DCRN_DCRX_BASE + 0x6)	/* Interrupt Generation Register */
213#define DCRN_DCRXBCR	(DCRN_DCRX_BASE + 0x7)	/* Line Buffer Control Register */
214
215#define DCRN_BRCRH0	(DCRN_EBIMC_BASE + 0x0)	/* Bus Region Config High 0 */
216#define DCRN_BRCRH1	(DCRN_EBIMC_BASE + 0x1)	/* Bus Region Config High 1 */
217#define DCRN_BRCRH2	(DCRN_EBIMC_BASE + 0x2)	/* Bus Region Config High 2 */
218#define DCRN_BRCRH3	(DCRN_EBIMC_BASE + 0x3)	/* Bus Region Config High 3 */
219#define DCRN_BRCRH4	(DCRN_EBIMC_BASE + 0x4)	/* Bus Region Config High 4 */
220#define DCRN_BRCRH5	(DCRN_EBIMC_BASE + 0x5)	/* Bus Region Config High 5 */
221#define DCRN_BRCRH6	(DCRN_EBIMC_BASE + 0x6)	/* Bus Region Config High 6 */
222#define DCRN_BRCRH7	(DCRN_EBIMC_BASE + 0x7)	/* Bus Region Config High 7 */
223#define DCRN_BRCR0	(DCRN_EBIMC_BASE + 0x10)	/* BRC 0 */
224#define DCRN_BRCR1	(DCRN_EBIMC_BASE + 0x11)	/* BRC 1 */
225#define DCRN_BRCR2	(DCRN_EBIMC_BASE + 0x12)	/* BRC 2 */
226#define DCRN_BRCR3	(DCRN_EBIMC_BASE + 0x13)	/* BRC 3 */
227#define DCRN_BRCR4	(DCRN_EBIMC_BASE + 0x14)	/* BRC 4 */
228#define DCRN_BRCR5	(DCRN_EBIMC_BASE + 0x15)	/* BRC 5 */
229#define DCRN_BRCR6	(DCRN_EBIMC_BASE + 0x16)	/* BRC 6 */
230#define DCRN_BRCR7	(DCRN_EBIMC_BASE + 0x17)	/* BRC 7 */
231#define DCRN_BEAR0	(DCRN_EBIMC_BASE + 0x20)	/* Bus Error Address Register */
232#define DCRN_BESR0	(DCRN_EBIMC_BASE + 0x21)	/* Bus Error Status Register */
233#define DCRN_BIUCR	(DCRN_EBIMC_BASE + 0x2A)	/* Bus Interfac Unit Ctrl Reg */
234
235#include <asm/ibm405.h>
236
237#endif				/* __ASM_IBMSTB4_H__ */
238#endif				/* __KERNEL__ */