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/arch/ppc/platforms/4xx/ibm405gpr.c

https://bitbucket.org/evzijst/gittest
C | 117 lines | 99 code | 7 blank | 11 comment | 0 complexity | ecf89540d342516d29b0f6659ed84b44 MD5 | raw file
  1/*
  2 * arch/ppc/platforms/4xx/ibm405gpr.c
  3 *
  4 * Author: Armin Kuster <akuster@mvista.com>
  5 *
  6 * 2002 (c) MontaVista, Software, Inc.  This file is licensed under
  7 * the terms of the GNU General Public License version 2.  This program
  8 * is licensed "as is" without any warranty of any kind, whether express
  9 * or implied.
 10 */
 11
 12#include <linux/config.h>
 13#include <linux/init.h>
 14#include <linux/smp.h>
 15#include <linux/threads.h>
 16#include <linux/param.h>
 17#include <linux/string.h>
 18#include <platforms/4xx/ibm405gpr.h>
 19#include <asm/ibm4xx.h>
 20#include <asm/ocp.h>
 21#include <asm/ppc4xx_pic.h>
 22
 23static struct ocp_func_emac_data ibm405gpr_emac0_def = {
 24	.rgmii_idx	= -1,		/* No RGMII */
 25	.rgmii_mux	= -1,		/* No RGMII */
 26	.zmii_idx	= -1,		/* ZMII device index */
 27	.zmii_mux	= 0,		/* ZMII input of this EMAC */
 28	.mal_idx	= 0,		/* MAL device index */
 29	.mal_rx_chan	= 0,		/* MAL rx channel number */
 30	.mal_tx_chan	= 0,		/* MAL tx channel number */
 31	.wol_irq	= 9,		/* WOL interrupt number */
 32	.mdio_idx	= -1,		/* No shared MDIO */
 33	.tah_idx	= -1,		/* No TAH */
 34};
 35OCP_SYSFS_EMAC_DATA()
 36
 37static struct ocp_func_mal_data ibm405gpr_mal0_def = {
 38	.num_tx_chans	= 1,		/* Number of TX channels */
 39	.num_rx_chans	= 1,		/* Number of RX channels */
 40	.txeob_irq	= 11,		/* TX End Of Buffer IRQ  */
 41	.rxeob_irq	= 12,		/* RX End Of Buffer IRQ  */
 42	.txde_irq	= 13,		/* TX Descriptor Error IRQ */
 43	.rxde_irq	= 14,		/* RX Descriptor Error IRQ */
 44	.serr_irq	= 10,		/* MAL System Error IRQ    */
 45};
 46OCP_SYSFS_MAL_DATA()
 47
 48static struct ocp_func_iic_data ibm405gpr_iic0_def = {
 49	.fast_mode	= 0,		/* Use standad mode (100Khz) */
 50};
 51
 52OCP_SYSFS_IIC_DATA()
 53
 54struct ocp_def core_ocp[] = {
 55	{ .vendor	= OCP_VENDOR_IBM,
 56	  .function	= OCP_FUNC_OPB,
 57	  .index	= 0,
 58	  .paddr	= 0xEF600000,
 59	  .irq		= OCP_IRQ_NA,
 60	  .pm		= OCP_CPM_NA,
 61	},
 62	{ .vendor	= OCP_VENDOR_IBM,
 63	  .function	= OCP_FUNC_16550,
 64	  .index	= 0,
 65	  .paddr	= UART0_IO_BASE,
 66	  .irq		= UART0_INT,
 67	  .pm		= IBM_CPM_UART0
 68	},
 69	{ .vendor	= OCP_VENDOR_IBM,
 70	  .function	= OCP_FUNC_16550,
 71	  .index	= 1,
 72	  .paddr	= UART1_IO_BASE,
 73	  .irq		= UART1_INT,
 74	  .pm		= IBM_CPM_UART1
 75	},
 76	{ .vendor	= OCP_VENDOR_IBM,
 77	  .function	= OCP_FUNC_IIC,
 78	  .paddr	= 0xEF600500,
 79	  .irq		= 2,
 80	  .pm		= IBM_CPM_IIC0,
 81	  .additions	= &ibm405gpr_iic0_def,
 82	  .show		= &ocp_show_iic_data,
 83	},
 84	{ .vendor	= OCP_VENDOR_IBM,
 85	  .function	= OCP_FUNC_GPIO,
 86	  .paddr	= 0xEF600700,
 87	  .irq		= OCP_IRQ_NA,
 88	  .pm		= IBM_CPM_GPIO0
 89	},
 90	{ .vendor	= OCP_VENDOR_IBM,
 91	  .function	= OCP_FUNC_MAL,
 92	  .paddr	= OCP_PADDR_NA,
 93	  .irq		= OCP_IRQ_NA,
 94	  .pm		= OCP_CPM_NA,
 95	  .additions	= &ibm405gpr_mal0_def,
 96	  .show		= &ocp_show_mal_data,
 97	},
 98	{ .vendor	= OCP_VENDOR_IBM,
 99	  .function	= OCP_FUNC_EMAC,
100	  .index	= 0,
101	  .paddr	= EMAC0_BASE,
102	  .irq		= 15,
103	  .pm		= IBM_CPM_EMAC0,
104	  .additions	= &ibm405gpr_emac0_def,
105	  .show		= &ocp_show_emac_data,
106	},
107	{ .vendor	= OCP_VENDOR_INVALID
108	}
109};
110
111/* Polarity and triggering settings for internal interrupt sources */
112struct ppc4xx_uic_settings ppc4xx_core_uic_cfg[] __initdata = {
113	{ .polarity 	= 0xffffe000,
114	  .triggering	= 0x10000000,
115	  .ext_irq_mask	= 0x00001fff,	/* IRQ7 - IRQ12, IRQ0 - IRQ6 */
116	}
117};