/arch/ppc/kernel/align.c

https://bitbucket.org/evzijst/gittest · C · 398 lines · 333 code · 29 blank · 36 comment · 68 complexity · b28181ccb6b79196a80f3e40c93dee10 MD5 · raw file

  1. /*
  2. * align.c - handle alignment exceptions for the Power PC.
  3. *
  4. * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
  5. * Copyright (c) 1998-1999 TiVo, Inc.
  6. * PowerPC 403GCX modifications.
  7. * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  8. * PowerPC 403GCX/405GP modifications.
  9. */
  10. #include <linux/config.h>
  11. #include <linux/kernel.h>
  12. #include <linux/mm.h>
  13. #include <asm/ptrace.h>
  14. #include <asm/processor.h>
  15. #include <asm/uaccess.h>
  16. #include <asm/system.h>
  17. #include <asm/cache.h>
  18. struct aligninfo {
  19. unsigned char len;
  20. unsigned char flags;
  21. };
  22. #if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
  23. #define OPCD(inst) (((inst) & 0xFC000000) >> 26)
  24. #define RS(inst) (((inst) & 0x03E00000) >> 21)
  25. #define RA(inst) (((inst) & 0x001F0000) >> 16)
  26. #define IS_XFORM(code) ((code) == 31)
  27. #endif
  28. #define INVALID { 0, 0 }
  29. #define LD 1 /* load */
  30. #define ST 2 /* store */
  31. #define SE 4 /* sign-extend value */
  32. #define F 8 /* to/from fp regs */
  33. #define U 0x10 /* update index register */
  34. #define M 0x20 /* multiple load/store */
  35. #define S 0x40 /* single-precision fp, or byte-swap value */
  36. #define SX 0x40 /* byte count in XER */
  37. #define HARD 0x80 /* string, stwcx. */
  38. #define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
  39. /*
  40. * The PowerPC stores certain bits of the instruction that caused the
  41. * alignment exception in the DSISR register. This array maps those
  42. * bits to information about the operand length and what the
  43. * instruction would do.
  44. */
  45. static struct aligninfo aligninfo[128] = {
  46. { 4, LD }, /* 00 0 0000: lwz / lwarx */
  47. INVALID, /* 00 0 0001 */
  48. { 4, ST }, /* 00 0 0010: stw */
  49. INVALID, /* 00 0 0011 */
  50. { 2, LD }, /* 00 0 0100: lhz */
  51. { 2, LD+SE }, /* 00 0 0101: lha */
  52. { 2, ST }, /* 00 0 0110: sth */
  53. { 4, LD+M }, /* 00 0 0111: lmw */
  54. { 4, LD+F+S }, /* 00 0 1000: lfs */
  55. { 8, LD+F }, /* 00 0 1001: lfd */
  56. { 4, ST+F+S }, /* 00 0 1010: stfs */
  57. { 8, ST+F }, /* 00 0 1011: stfd */
  58. INVALID, /* 00 0 1100 */
  59. INVALID, /* 00 0 1101: ld/ldu/lwa */
  60. INVALID, /* 00 0 1110 */
  61. INVALID, /* 00 0 1111: std/stdu */
  62. { 4, LD+U }, /* 00 1 0000: lwzu */
  63. INVALID, /* 00 1 0001 */
  64. { 4, ST+U }, /* 00 1 0010: stwu */
  65. INVALID, /* 00 1 0011 */
  66. { 2, LD+U }, /* 00 1 0100: lhzu */
  67. { 2, LD+SE+U }, /* 00 1 0101: lhau */
  68. { 2, ST+U }, /* 00 1 0110: sthu */
  69. { 4, ST+M }, /* 00 1 0111: stmw */
  70. { 4, LD+F+S+U }, /* 00 1 1000: lfsu */
  71. { 8, LD+F+U }, /* 00 1 1001: lfdu */
  72. { 4, ST+F+S+U }, /* 00 1 1010: stfsu */
  73. { 8, ST+F+U }, /* 00 1 1011: stfdu */
  74. INVALID, /* 00 1 1100 */
  75. INVALID, /* 00 1 1101 */
  76. INVALID, /* 00 1 1110 */
  77. INVALID, /* 00 1 1111 */
  78. INVALID, /* 01 0 0000: ldx */
  79. INVALID, /* 01 0 0001 */
  80. INVALID, /* 01 0 0010: stdx */
  81. INVALID, /* 01 0 0011 */
  82. INVALID, /* 01 0 0100 */
  83. INVALID, /* 01 0 0101: lwax */
  84. INVALID, /* 01 0 0110 */
  85. INVALID, /* 01 0 0111 */
  86. { 4, LD+M+HARD+SX }, /* 01 0 1000: lswx */
  87. { 4, LD+M+HARD }, /* 01 0 1001: lswi */
  88. { 4, ST+M+HARD+SX }, /* 01 0 1010: stswx */
  89. { 4, ST+M+HARD }, /* 01 0 1011: stswi */
  90. INVALID, /* 01 0 1100 */
  91. INVALID, /* 01 0 1101 */
  92. INVALID, /* 01 0 1110 */
  93. INVALID, /* 01 0 1111 */
  94. INVALID, /* 01 1 0000: ldux */
  95. INVALID, /* 01 1 0001 */
  96. INVALID, /* 01 1 0010: stdux */
  97. INVALID, /* 01 1 0011 */
  98. INVALID, /* 01 1 0100 */
  99. INVALID, /* 01 1 0101: lwaux */
  100. INVALID, /* 01 1 0110 */
  101. INVALID, /* 01 1 0111 */
  102. INVALID, /* 01 1 1000 */
  103. INVALID, /* 01 1 1001 */
  104. INVALID, /* 01 1 1010 */
  105. INVALID, /* 01 1 1011 */
  106. INVALID, /* 01 1 1100 */
  107. INVALID, /* 01 1 1101 */
  108. INVALID, /* 01 1 1110 */
  109. INVALID, /* 01 1 1111 */
  110. INVALID, /* 10 0 0000 */
  111. INVALID, /* 10 0 0001 */
  112. { 0, ST+HARD }, /* 10 0 0010: stwcx. */
  113. INVALID, /* 10 0 0011 */
  114. INVALID, /* 10 0 0100 */
  115. INVALID, /* 10 0 0101 */
  116. INVALID, /* 10 0 0110 */
  117. INVALID, /* 10 0 0111 */
  118. { 4, LD+S }, /* 10 0 1000: lwbrx */
  119. INVALID, /* 10 0 1001 */
  120. { 4, ST+S }, /* 10 0 1010: stwbrx */
  121. INVALID, /* 10 0 1011 */
  122. { 2, LD+S }, /* 10 0 1100: lhbrx */
  123. INVALID, /* 10 0 1101 */
  124. { 2, ST+S }, /* 10 0 1110: sthbrx */
  125. INVALID, /* 10 0 1111 */
  126. INVALID, /* 10 1 0000 */
  127. INVALID, /* 10 1 0001 */
  128. INVALID, /* 10 1 0010 */
  129. INVALID, /* 10 1 0011 */
  130. INVALID, /* 10 1 0100 */
  131. INVALID, /* 10 1 0101 */
  132. INVALID, /* 10 1 0110 */
  133. INVALID, /* 10 1 0111 */
  134. INVALID, /* 10 1 1000 */
  135. INVALID, /* 10 1 1001 */
  136. INVALID, /* 10 1 1010 */
  137. INVALID, /* 10 1 1011 */
  138. INVALID, /* 10 1 1100 */
  139. INVALID, /* 10 1 1101 */
  140. INVALID, /* 10 1 1110 */
  141. { 0, ST+HARD }, /* 10 1 1111: dcbz */
  142. { 4, LD }, /* 11 0 0000: lwzx */
  143. INVALID, /* 11 0 0001 */
  144. { 4, ST }, /* 11 0 0010: stwx */
  145. INVALID, /* 11 0 0011 */
  146. { 2, LD }, /* 11 0 0100: lhzx */
  147. { 2, LD+SE }, /* 11 0 0101: lhax */
  148. { 2, ST }, /* 11 0 0110: sthx */
  149. INVALID, /* 11 0 0111 */
  150. { 4, LD+F+S }, /* 11 0 1000: lfsx */
  151. { 8, LD+F }, /* 11 0 1001: lfdx */
  152. { 4, ST+F+S }, /* 11 0 1010: stfsx */
  153. { 8, ST+F }, /* 11 0 1011: stfdx */
  154. INVALID, /* 11 0 1100 */
  155. INVALID, /* 11 0 1101: lmd */
  156. INVALID, /* 11 0 1110 */
  157. INVALID, /* 11 0 1111: stmd */
  158. { 4, LD+U }, /* 11 1 0000: lwzux */
  159. INVALID, /* 11 1 0001 */
  160. { 4, ST+U }, /* 11 1 0010: stwux */
  161. INVALID, /* 11 1 0011 */
  162. { 2, LD+U }, /* 11 1 0100: lhzux */
  163. { 2, LD+SE+U }, /* 11 1 0101: lhaux */
  164. { 2, ST+U }, /* 11 1 0110: sthux */
  165. INVALID, /* 11 1 0111 */
  166. { 4, LD+F+S+U }, /* 11 1 1000: lfsux */
  167. { 8, LD+F+U }, /* 11 1 1001: lfdux */
  168. { 4, ST+F+S+U }, /* 11 1 1010: stfsux */
  169. { 8, ST+F+U }, /* 11 1 1011: stfdux */
  170. INVALID, /* 11 1 1100 */
  171. INVALID, /* 11 1 1101 */
  172. INVALID, /* 11 1 1110 */
  173. INVALID, /* 11 1 1111 */
  174. };
  175. #define SWAP(a, b) (t = (a), (a) = (b), (b) = t)
  176. int
  177. fix_alignment(struct pt_regs *regs)
  178. {
  179. int instr, nb, flags;
  180. #if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
  181. int opcode, f1, f2, f3;
  182. #endif
  183. int i, t;
  184. int reg, areg;
  185. int offset, nb0;
  186. unsigned char __user *addr;
  187. unsigned char *rptr;
  188. union {
  189. long l;
  190. float f;
  191. double d;
  192. unsigned char v[8];
  193. } data;
  194. CHECK_FULL_REGS(regs);
  195. #if defined(CONFIG_4xx) || defined(CONFIG_POWER4) || defined(CONFIG_BOOKE)
  196. /* The 4xx-family & Book-E processors have no DSISR register,
  197. * so we emulate it.
  198. * The POWER4 has a DSISR register but doesn't set it on
  199. * an alignment fault. -- paulus
  200. */
  201. if (__get_user(instr, (unsigned int __user *) regs->nip))
  202. return 0;
  203. opcode = OPCD(instr);
  204. reg = RS(instr);
  205. areg = RA(instr);
  206. if (!IS_XFORM(opcode)) {
  207. f1 = 0;
  208. f2 = (instr & 0x04000000) >> 26;
  209. f3 = (instr & 0x78000000) >> 27;
  210. } else {
  211. f1 = (instr & 0x00000006) >> 1;
  212. f2 = (instr & 0x00000040) >> 6;
  213. f3 = (instr & 0x00000780) >> 7;
  214. }
  215. instr = ((f1 << 5) | (f2 << 4) | f3);
  216. #else
  217. reg = (regs->dsisr >> 5) & 0x1f; /* source/dest register */
  218. areg = regs->dsisr & 0x1f; /* register to update */
  219. instr = (regs->dsisr >> 10) & 0x7f;
  220. #endif
  221. nb = aligninfo[instr].len;
  222. if (nb == 0) {
  223. long __user *p;
  224. int i;
  225. if (instr != DCBZ)
  226. return 0; /* too hard or invalid instruction */
  227. /*
  228. * The dcbz (data cache block zero) instruction
  229. * gives an alignment fault if used on non-cacheable
  230. * memory. We handle the fault mainly for the
  231. * case when we are running with the cache disabled
  232. * for debugging.
  233. */
  234. p = (long __user *) (regs->dar & -L1_CACHE_BYTES);
  235. if (user_mode(regs)
  236. && !access_ok(VERIFY_WRITE, p, L1_CACHE_BYTES))
  237. return -EFAULT;
  238. for (i = 0; i < L1_CACHE_BYTES / sizeof(long); ++i)
  239. if (__put_user(0, p+i))
  240. return -EFAULT;
  241. return 1;
  242. }
  243. flags = aligninfo[instr].flags;
  244. if ((flags & (LD|ST)) == 0)
  245. return 0;
  246. /* For the 4xx-family & Book-E processors, the 'dar' field of the
  247. * pt_regs structure is overloaded and is really from the DEAR.
  248. */
  249. addr = (unsigned char __user *)regs->dar;
  250. if (flags & M) {
  251. /* lmw, stmw, lswi/x, stswi/x */
  252. nb0 = 0;
  253. if (flags & HARD) {
  254. if (flags & SX) {
  255. nb = regs->xer & 127;
  256. if (nb == 0)
  257. return 1;
  258. } else {
  259. if (__get_user(instr,
  260. (unsigned int __user *)regs->nip))
  261. return 0;
  262. nb = (instr >> 11) & 0x1f;
  263. if (nb == 0)
  264. nb = 32;
  265. }
  266. if (nb + reg * 4 > 128) {
  267. nb0 = nb + reg * 4 - 128;
  268. nb = 128 - reg * 4;
  269. }
  270. } else {
  271. /* lwm, stmw */
  272. nb = (32 - reg) * 4;
  273. }
  274. rptr = (unsigned char *) &regs->gpr[reg];
  275. if (flags & LD) {
  276. for (i = 0; i < nb; ++i)
  277. if (__get_user(rptr[i], addr+i))
  278. return -EFAULT;
  279. if (nb0 > 0) {
  280. rptr = (unsigned char *) &regs->gpr[0];
  281. addr += nb;
  282. for (i = 0; i < nb0; ++i)
  283. if (__get_user(rptr[i], addr+i))
  284. return -EFAULT;
  285. }
  286. for (; (i & 3) != 0; ++i)
  287. rptr[i] = 0;
  288. } else {
  289. for (i = 0; i < nb; ++i)
  290. if (__put_user(rptr[i], addr+i))
  291. return -EFAULT;
  292. if (nb0 > 0) {
  293. rptr = (unsigned char *) &regs->gpr[0];
  294. addr += nb;
  295. for (i = 0; i < nb0; ++i)
  296. if (__put_user(rptr[i], addr+i))
  297. return -EFAULT;
  298. }
  299. }
  300. return 1;
  301. }
  302. offset = 0;
  303. if (nb < 4) {
  304. /* read/write the least significant bits */
  305. data.l = 0;
  306. offset = 4 - nb;
  307. }
  308. /* Verify the address of the operand */
  309. if (user_mode(regs)) {
  310. if (!access_ok((flags & ST? VERIFY_WRITE: VERIFY_READ), addr, nb))
  311. return -EFAULT; /* bad address */
  312. }
  313. if (flags & F) {
  314. preempt_disable();
  315. if (regs->msr & MSR_FP)
  316. giveup_fpu(current);
  317. preempt_enable();
  318. }
  319. /* If we read the operand, copy it in, else get register values */
  320. if (flags & LD) {
  321. for (i = 0; i < nb; ++i)
  322. if (__get_user(data.v[offset+i], addr+i))
  323. return -EFAULT;
  324. } else if (flags & F) {
  325. data.d = current->thread.fpr[reg];
  326. } else {
  327. data.l = regs->gpr[reg];
  328. }
  329. switch (flags & ~U) {
  330. case LD+SE: /* sign extend */
  331. if (data.v[2] >= 0x80)
  332. data.v[0] = data.v[1] = -1;
  333. break;
  334. case LD+S: /* byte-swap */
  335. case ST+S:
  336. if (nb == 2) {
  337. SWAP(data.v[2], data.v[3]);
  338. } else {
  339. SWAP(data.v[0], data.v[3]);
  340. SWAP(data.v[1], data.v[2]);
  341. }
  342. break;
  343. /* Single-precision FP load and store require conversions... */
  344. case LD+F+S:
  345. preempt_disable();
  346. enable_kernel_fp();
  347. cvt_fd(&data.f, &data.d, &current->thread.fpscr);
  348. preempt_enable();
  349. break;
  350. case ST+F+S:
  351. preempt_disable();
  352. enable_kernel_fp();
  353. cvt_df(&data.d, &data.f, &current->thread.fpscr);
  354. preempt_enable();
  355. break;
  356. }
  357. if (flags & ST) {
  358. for (i = 0; i < nb; ++i)
  359. if (__put_user(data.v[offset+i], addr+i))
  360. return -EFAULT;
  361. } else if (flags & F) {
  362. current->thread.fpr[reg] = data.d;
  363. } else {
  364. regs->gpr[reg] = data.l;
  365. }
  366. if (flags & U)
  367. regs->gpr[areg] = regs->dar;
  368. return 1;
  369. }