/arch/ppc/boot/simple/rw4/rw4_init.S

https://bitbucket.org/evzijst/gittest · Assembly · 78 lines · 66 code · 12 blank · 0 comment · 3 complexity · aa63bd8edab6e89a493d4b89202be20e MD5 · raw file 

    

  1. #define VESTA
    2. 

  2. #include "ppc_40x.h"
    3. 

  3. #
    4. 

  4.         .align 2
    5. 

  5.         .text
    6. 

  6. #
    7. 

  7. # added by linguohui
    8. 

  8.         .extern   initb_ebiu0, initb_config, hdw_init_finish
    9. 

  9.         .extern   initb_hsmc0, initb_hsmc1, initb_cache
    10. 

  10. # end added
    11. 

  11.        .globl    HdwInit
    12. 

  12. #
    13. 

  13. HdwInit:
    14. 

  14. #
    15. 

  15. #-----------------------------------------------------------------------*
    16. 

  16. # If we are not executing from the FLASH get out                        *
    17. 

  17. #-----------------------------------------------------------------------*
    18. 

  18. # SAW keep this or comment out a la Hawthorne?
    19. 

  19. # r3 contains NIP when used with Linux
    20. 

  20. #        rlwinm r28, r3, 8, 24, 31    # if MSB == 0xFF -> FLASH address
    21. 

  21. #        cmpwi  r28, 0xff
    22. 

  22. #        bne    locn01
    23. 

  23. #
    24. 

  24. #
    25. 

  25. #------------------------------------------------------------------------
    26. 

  26. # Init_cpu. Bank registers are setup for the IBM STB.
    27. 

  27. #------------------------------------------------------------------------
    28. 

  28. #
    29. 

  29. # Setup processor core clock to be driven off chip.  This is GPI4 bit
    30. 

  30. # twenty.  Setup Open Drain, Output Select, Three-State Control,  and
    31. 

  31. # Three-State Select registers.
    32. 

  32. #
    33. 

  33. 

  34. 

  35.         pb0pesr  =        0x054
    36. 

  36.         pb0pear  =        0x056
    37. 

  37. 

  38. 	mflr	r30
    39. 

  39. 

  40. #-----------------------------------------------------------------------------
    41. 

  41. # Vectors will be at 0x1F000000
    42. 

  42. # Dummy Machine check handler just does RFI before true handler gets installed
    43. 

  43. #-----------------------------------------------------------------------------
    44. 

  44. #if 1  /* xuwentao added*/
    45. 

  45. #ifdef SDRAM16MB
    46. 

  46.          lis     r10,0x0000
    47. 

  47. 	addi 	r10,r10,0x0000
    48. 

  48. #else
    49. 

  49.         lis      r10,0x1F00
    50. 

  50. 	addi	r10,r10,0x0000
    51. 

  51. #endif
    52. 

  52. 

  53.         mtspr   evpr,r10              #EVPR: 0x0 or 0x1f000000 depending
    54. 

  54.         isync                         # on SDRAM memory model used.
    55. 

  55. 

  56.         lis     r10,0xFFFF                # clear PB0_PESR because some
    57. 

  57.         ori    r10,r10,0xFFFF            #  transitions from flash,changed by linguohui
    58. 

  58.         mtdcr   pb0pesr,r10               #  to load RAM image via RiscWatch
    59. 

  59.         lis     r10,0x0000                #  cause PB0_PESR machine checks
    60. 

  60.         mtdcr   pb0pear,r10
    61. 

  61.         addis   r10,r10,0x0000            # clear the
    62. 

  62.         mtxer   r10                       #           XER just in case...
    63. 

  63. #endif /* xuwentao*/
    64. 

  64. 

  65.         bl      initb_ebiu0                      # init EBIU
    66. 

  66. 

  67.         bl      initb_config                     # config PPC and board
    68. 

  68. 

  69. 

  70. 

  71. 

  72. #------------------------------------------------------------------------
    73. 

  73. # EVPR  setup moved to top of this function.
    74. 

  74. #------------------------------------------------------------------------
    75. 

  75. #
    76. 

  76. 	mtlr	r30
    77. 

  77. 	blr
    78. 

  78.         .end
    79.