/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c

https://bitbucket.org/evzijst/gittest · C · 786 lines · 514 code · 140 blank · 132 comment · 48 complexity · 77e5f4462af4192c5dc192b56eb1645f MD5 · raw file 

    

  1. /*
    2. 

  2.  * linux/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
    3. 

  3.  *
    4. 

  4.  * Toshiba RBTX4927 specific interrupt handlers
    5. 

  5.  *
    6. 

  6.  * Author: MontaVista Software, Inc.
    7. 

  7.  *         source@mvista.com
    8. 

  8.  *
    9. 

  9.  * Copyright 2001-2002 MontaVista Software Inc.
    10. 

  10.  *
    11. 

  11.  *  This program is free software; you can redistribute it and/or modify it
    12. 

  12.  *  under the terms of the GNU General Public License as published by the
    13. 

  13.  *  Free Software Foundation; either version 2 of the License, or (at your
    14. 

  14.  *  option) any later version.
    15. 

  15.  *
    16. 

  16.  *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
    17. 

  17.  *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    18. 

  18.  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
    19. 

  19.  *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
    20. 

  20.  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
    21. 

  21.  *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
    22. 

  22.  *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    23. 

  23.  *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
    24. 

  24.  *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
    25. 

  25.  *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    26. 

  26.  *
    27. 

  27.  *  You should have received a copy of the GNU General Public License along
    28. 

  28.  *  with this program; if not, write to the Free Software Foundation, Inc.,
    29. 

  29.  *  675 Mass Ave, Cambridge, MA 02139, USA.
    30. 

  30.  */
    31. 

  31. 

  32. 

  33. /*
    34. 

  34. IRQ  Device  
    35. 

  35. 00   RBTX4927-ISA/00
    36. 

  36. 01   RBTX4927-ISA/01 PS2/Keyboard
    37. 

  37. 02   RBTX4927-ISA/02 Cascade RBTX4927-ISA (irqs 8-15)
    38. 

  38. 03   RBTX4927-ISA/03
    39. 

  39. 04   RBTX4927-ISA/04
    40. 

  40. 05   RBTX4927-ISA/05
    41. 

  41. 06   RBTX4927-ISA/06
    42. 

  42. 07   RBTX4927-ISA/07
    43. 

  43. 08   RBTX4927-ISA/08
    44. 

  44. 09   RBTX4927-ISA/09
    45. 

  45. 10   RBTX4927-ISA/10
    46. 

  46. 11   RBTX4927-ISA/11
    47. 

  47. 12   RBTX4927-ISA/12 PS2/Mouse (not supported at this time)
    48. 

  48. 13   RBTX4927-ISA/13
    49. 

  49. 14   RBTX4927-ISA/14 IDE
    50. 

  50. 15   RBTX4927-ISA/15
    51. 

    52. 

  52. 16   TX4927-CP0/00 Software 0
    53. 

  53. 17   TX4927-CP0/01 Software 1
    54. 

  54. 18   TX4927-CP0/02 Cascade TX4927-CP0
    55. 

  55. 19   TX4927-CP0/03 Multiplexed -- do not use 
    56. 

  56. 20   TX4927-CP0/04 Multiplexed -- do not use 
    57. 

  57. 21   TX4927-CP0/05 Multiplexed -- do not use 
    58. 

  58. 22   TX4927-CP0/06 Multiplexed -- do not use 
    59. 

  59. 23   TX4927-CP0/07 CPU TIMER
    60. 

    61. 

  61. 24   TX4927-PIC/00
    62. 

  62. 25   TX4927-PIC/01
    63. 

  63. 26   TX4927-PIC/02  
    64. 

  64. 27   TX4927-PIC/03 Cascade RBTX4927-IOC
    65. 

  65. 28   TX4927-PIC/04
    66. 

  66. 29   TX4927-PIC/05 RBTX4927 RTL-8019AS ethernet
    67. 

  67. 30   TX4927-PIC/06
    68. 

  68. 31   TX4927-PIC/07
    69. 

  69. 32   TX4927-PIC/08 TX4927 SerialIO Channel 0
    70. 

  70. 33   TX4927-PIC/09 TX4927 SerialIO Channel 1
    71. 

  71. 34   TX4927-PIC/10
    72. 

  72. 35   TX4927-PIC/11
    73. 

  73. 36   TX4927-PIC/12
    74. 

  74. 37   TX4927-PIC/13
    75. 

  75. 38   TX4927-PIC/14
    76. 

  76. 39   TX4927-PIC/15
    77. 

  77. 40   TX4927-PIC/16 TX4927 PCI PCI-C
    78. 

  78. 41   TX4927-PIC/17
    79. 

  79. 42   TX4927-PIC/18
    80. 

  80. 43   TX4927-PIC/19
    81. 

  81. 44   TX4927-PIC/20
    82. 

  82. 45   TX4927-PIC/21
    83. 

  83. 46   TX4927-PIC/22 TX4927 PCI PCI-ERR 
    84. 

  84. 47   TX4927-PIC/23 TX4927 PCI PCI-PMA (not used)
    85. 

  85. 48   TX4927-PIC/24
    86. 

  86. 49   TX4927-PIC/25
    87. 

  87. 50   TX4927-PIC/26
    88. 

  88. 51   TX4927-PIC/27
    89. 

  89. 52   TX4927-PIC/28
    90. 

  90. 53   TX4927-PIC/29
    91. 

  91. 54   TX4927-PIC/30
    92. 

  92. 55   TX4927-PIC/31
    93. 

    94. 

  94. 56 RBTX4927-IOC/00 FPCIB0 PCI-D PJ4/A PJ5/B SB/C PJ6/D PJ7/A (SouthBridge/NotUsed)        [RTL-8139=PJ4]
    95. 

  95. 57 RBTX4927-IOC/01 FPCIB0 PCI-C PJ4/D PJ5/A SB/B PJ6/C PJ7/D (SouthBridge/NotUsed)        [RTL-8139=PJ5]
    96. 

  96. 58 RBTX4927-IOC/02 FPCIB0 PCI-B PJ4/C PJ5/D SB/A PJ6/B PJ7/C (SouthBridge/IDE/pin=1,INTR) [RTL-8139=NotSupported]
    97. 

  97. 59 RBTX4927-IOC/03 FPCIB0 PCI-A PJ4/B PJ5/C SB/D PJ6/A PJ7/B (SouthBridge/USB/pin=4)      [RTL-8139=PJ6]
    98. 

  98. 60 RBTX4927-IOC/04
    99. 

  99. 61 RBTX4927-IOC/05
    100. 

  100. 62 RBTX4927-IOC/06
    101. 

  101. 63 RBTX4927-IOC/07
    102. 

    103. 

  103. NOTES: 
    104. 

  104. SouthBridge/INTR is mapped to SouthBridge/A=PCI-B/#58
    105. 

  105. SouthBridge/ISA/pin=0 no pci irq used by this device
    106. 

  106. SouthBridge/IDE/pin=1 no pci irq used by this device, using INTR via ISA IRQ14
    107. 

  107. SouthBridge/USB/pin=4 using pci irq SouthBridge/D=PCI-A=#59
    108. 

  108. SouthBridge/PMC/pin=0 no pci irq used by this device
    109. 

  109. SuperIO/PS2/Keyboard, using INTR via ISA IRQ1
    110. 

  110. SuperIO/PS2/Mouse, using INTR via ISA IRQ12 (mouse not currently supported)
    111. 

  111. JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthBridge, JP4, JP5, JP6
    112. 

  112. */
    113. 

  113. 

  114. #include <linux/config.h>
    115. 

  115. #include <linux/init.h>
    116. 

  116. #include <linux/kernel.h>
    117. 

  117. #include <linux/types.h>
    118. 

  118. #include <linux/mm.h>
    119. 

  119. #include <linux/swap.h>
    120. 

  120. #include <linux/ioport.h>
    121. 

  121. #include <linux/sched.h>
    122. 

  122. #include <linux/interrupt.h>
    123. 

  123. #include <linux/pci.h>
    124. 

  124. #include <linux/timex.h>
    125. 

  125. #include <asm/bootinfo.h>
    126. 

  126. #include <asm/page.h>
    127. 

  127. #include <asm/io.h>
    128. 

  128. #include <asm/irq.h>
    129. 

  129. #include <asm/pci.h>
    130. 

  130. #include <asm/processor.h>
    131. 

  131. #include <asm/ptrace.h>
    132. 

  132. #include <asm/reboot.h>
    133. 

  133. #include <asm/time.h>
    134. 

  134. #include <linux/bootmem.h>
    135. 

  135. #include <linux/blkdev.h>
    136. 

  136. #ifdef CONFIG_RTC_DS1742
    137. 

  137. #include <linux/ds1742rtc.h>
    138. 

  138. #endif
    139. 

  139. #ifdef CONFIG_TOSHIBA_FPCIB0
    140. 

  140. #include <asm/tx4927/smsc_fdc37m81x.h>
    141. 

  141. #endif
    142. 

  142. #include <asm/tx4927/toshiba_rbtx4927.h>
    143. 

  143. 

  144. 

  145. #undef TOSHIBA_RBTX4927_IRQ_DEBUG
    146. 

  146. 

  147. #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
    148. 

  148. #define TOSHIBA_RBTX4927_IRQ_NONE        0x00000000
    149. 

  149. 

  150. #define TOSHIBA_RBTX4927_IRQ_INFO          ( 1 <<  0 )
    151. 

  151. #define TOSHIBA_RBTX4927_IRQ_WARN          ( 1 <<  1 )
    152. 

  152. #define TOSHIBA_RBTX4927_IRQ_EROR          ( 1 <<  2 )
    153. 

  153. 

  154. #define TOSHIBA_RBTX4927_IRQ_IOC_INIT      ( 1 << 10 )
    155. 

  155. #define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP   ( 1 << 11 )
    156. 

  156. #define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN  ( 1 << 12 )
    157. 

  157. #define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE    ( 1 << 13 )
    158. 

  158. #define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE   ( 1 << 14 )
    159. 

  159. #define TOSHIBA_RBTX4927_IRQ_IOC_MASK      ( 1 << 15 )
    160. 

  160. #define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ    ( 1 << 16 )
    161. 

  161. 

  162. #define TOSHIBA_RBTX4927_IRQ_ISA_INIT      ( 1 << 20 )
    163. 

  163. #define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP   ( 1 << 21 )
    164. 

  164. #define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN  ( 1 << 22 )
    165. 

  165. #define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE    ( 1 << 23 )
    166. 

  166. #define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE   ( 1 << 24 )
    167. 

  167. #define TOSHIBA_RBTX4927_IRQ_ISA_MASK      ( 1 << 25 )
    168. 

  168. #define TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ    ( 1 << 26 )
    169. 

  169. 

  170. #define TOSHIBA_RBTX4927_SETUP_ALL         0xffffffff
    171. 

  171. #endif
    172. 

  172. 

  173. 

  174. #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
    175. 

  175. static const u32 toshiba_rbtx4927_irq_debug_flag =
    176. 

  176.     (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
    177. 

  177.      TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
    178. 

  178. //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_INIT  
    179. 

  179. //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP  
    180. 

  180. //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN  
    181. 

  181. //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE  
    182. 

  182. //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE  
    183. 

  183. //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_MASK  
    184. 

  184. //                                                 | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ  
    185. 

  185. //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_INIT  
    186. 

  186. //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP  
    187. 

  187. //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN  
    188. 

  188. //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE  
    189. 

  189. //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE  
    190. 

  190. //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_MASK  
    191. 

  191. //                                                 | TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ
    192. 

  192.     );
    193. 

  193. #endif
    194. 

  194. 

  195. 

  196. #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
    197. 

  197. #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...) \
    198. 

  198.         if ( (toshiba_rbtx4927_irq_debug_flag) & (flag) ) \
    199. 

  199.         { \
    200. 

  200.            char tmp[100]; \
    201. 

  201.            sprintf( tmp, str ); \
    202. 

  202.            printk( "%s(%s:%u)::%s", __FUNCTION__, __FILE__, __LINE__, tmp ); \
    203. 

  203.         }
    204. 

  204. #else
    205. 

  205. #define TOSHIBA_RBTX4927_IRQ_DPRINTK(flag,str...)
    206. 

  206. #endif
    207. 

  207. 

  208. 

  209. 

  210. 

  211. #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG   0
    212. 

  212. #define TOSHIBA_RBTX4927_IRQ_IOC_RAW_END   7
    213. 

  213. 

  214. #define TOSHIBA_RBTX4927_IRQ_IOC_BEG  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_BEG)	/* 56 */
    215. 

  215. #define TOSHIBA_RBTX4927_IRQ_IOC_END  ((TX4927_IRQ_PIC_END+1)+TOSHIBA_RBTX4927_IRQ_IOC_RAW_END)	/* 63 */
    216. 

  216. 

  217. 

  218. #define TOSHIBA_RBTX4927_IRQ_ISA_BEG MI8259_IRQ_ISA_BEG
    219. 

  219. #define TOSHIBA_RBTX4927_IRQ_ISA_END MI8259_IRQ_ISA_END
    220. 

  220. #define TOSHIBA_RBTX4927_IRQ_ISA_MID ((TOSHIBA_RBTX4927_IRQ_ISA_BEG+TOSHIBA_RBTX4927_IRQ_ISA_END+1)/2)
    221. 

  221. 

  222. 

  223. #define TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC TX4927_IRQ_NEST_EXT_ON_PIC
    224. 

  224. #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC (TOSHIBA_RBTX4927_IRQ_IOC_BEG+2)
    225. 

  225. #define TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA (TOSHIBA_RBTX4927_IRQ_ISA_BEG+2)
    226. 

  226. 

  227. extern int tx4927_using_backplane;
    228. 

  228. 

  229. #ifdef CONFIG_TOSHIBA_FPCIB0
    230. 

  230. extern void enable_8259A_irq(unsigned int irq);
    231. 

  231. extern void disable_8259A_irq(unsigned int irq);
    232. 

  232. extern void mask_and_ack_8259A(unsigned int irq);
    233. 

  233. #endif
    234. 

  234. 

  235. static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq);
    236. 

  236. static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq);
    237. 

  237. static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
    238. 

  238. static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
    239. 

  239. static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq);
    240. 

  240. static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
    241. 

  241. 

  242. #ifdef CONFIG_TOSHIBA_FPCIB0
    243. 

  243. static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq);
    244. 

  244. static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq);
    245. 

  245. static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
    246. 

  246. static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
    247. 

  247. static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
    248. 

  248. static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
    249. 

  249. #endif
    250. 

  250. 

  251. static DEFINE_SPINLOCK(toshiba_rbtx4927_ioc_lock);
    252. 

  252. 

  253. 

  254. #define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
    255. 

  255. static struct hw_interrupt_type toshiba_rbtx4927_irq_ioc_type = {
    256. 

  256. 	.typename = TOSHIBA_RBTX4927_IOC_NAME,
    257. 

  257. 	.startup = toshiba_rbtx4927_irq_ioc_startup,
    258. 

  258. 	.shutdown = toshiba_rbtx4927_irq_ioc_shutdown,
    259. 

  259. 	.enable = toshiba_rbtx4927_irq_ioc_enable,
    260. 

  260. 	.disable = toshiba_rbtx4927_irq_ioc_disable,
    261. 

  261. 	.ack = toshiba_rbtx4927_irq_ioc_mask_and_ack,
    262. 

  262. 	.end = toshiba_rbtx4927_irq_ioc_end,
    263. 

  263. 	.set_affinity = NULL
    264. 

  264. };
    265. 

  265. #define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
    266. 

  266. #define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
    267. 

  267. 

  268. 

  269. #ifdef CONFIG_TOSHIBA_FPCIB0
    270. 

  270. #define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
    271. 

  271. static struct hw_interrupt_type toshiba_rbtx4927_irq_isa_type = {
    272. 

  272. 	.typename = TOSHIBA_RBTX4927_ISA_NAME,
    273. 

  273. 	.startup = toshiba_rbtx4927_irq_isa_startup,
    274. 

  274. 	.shutdown = toshiba_rbtx4927_irq_isa_shutdown,
    275. 

  275. 	.enable = toshiba_rbtx4927_irq_isa_enable,
    276. 

  276. 	.disable = toshiba_rbtx4927_irq_isa_disable,
    277. 

  277. 	.ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
    278. 

  278. 	.end = toshiba_rbtx4927_irq_isa_end,
    279. 

  279. 	.set_affinity = NULL
    280. 

  280. };
    281. 

  281. #endif
    282. 

  282. 

  283. 

  284. u32 bit2num(u32 num)
    285. 

  285. {
    286. 

  286. 	u32 i;
    287. 

  287. 

  288. 	for (i = 0; i < (sizeof(num) * 8); i++) {
    289. 

  289. 		if (num & (1 << i)) {
    290. 

  290. 			return (i);
    291. 

  291. 		}
    292. 

  292. 	}
    293. 

  293. 	return (0);
    294. 

  294. }
    295. 

  295. 

  296. int toshiba_rbtx4927_irq_nested(int sw_irq)
    297. 

  297. {
    298. 

  298. 	u32 level3;
    299. 

  299. 	u32 level4;
    300. 

  300. 	u32 level5;
    301. 

  301. 

  302. 	level3 = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
    303. 

  303. 	if (level3) {
    304. 

  304. 		sw_irq = TOSHIBA_RBTX4927_IRQ_IOC_BEG + bit2num(level3);
    305. 

  305. 		if (sw_irq != TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC) {
    306. 

  306. 			goto RETURN;
    307. 

  307. 		}
    308. 

  308. 	}
    309. 

  309. #ifdef CONFIG_TOSHIBA_FPCIB0
    310. 

  310. 	{
    311. 

  311. 		if (tx4927_using_backplane) {
    312. 

  312. 			outb(0x0A, 0x20);
    313. 

  313. 			level4 = inb(0x20) & 0xff;
    314. 

  314. 			if (level4) {
    315. 

  315. 				sw_irq =
    316. 

  316. 				    TOSHIBA_RBTX4927_IRQ_ISA_BEG +
    317. 

  317. 				    bit2num(level4);
    318. 

  318. 				if (sw_irq !=
    319. 

  319. 				    TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA) {
    320. 

  320. 					goto RETURN;
    321. 

  321. 				}
    322. 

  322. 			}
    323. 

  323. 

  324. 			outb(0x0A, 0xA0);
    325. 

  325. 			level5 = inb(0xA0) & 0xff;
    326. 

  326. 			if (level5) {
    327. 

  327. 				sw_irq =
    328. 

  328. 				    TOSHIBA_RBTX4927_IRQ_ISA_MID +
    329. 

  329. 				    bit2num(level5);
    330. 

  330. 				goto RETURN;
    331. 

  331. 			}
    332. 

  332. 		}
    333. 

  333. 	}
    334. 

  334. #endif
    335. 

  335. 

  336.       RETURN:
    337. 

  337. 	return (sw_irq);
    338. 

  338. }
    339. 

  339. 

  340. //#define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
    341. 

  341. #define TOSHIBA_RBTX4927_PIC_ACTION(s) { no_action, SA_SHIRQ, CPU_MASK_NONE, s, NULL, NULL }
    342. 

  342. static struct irqaction toshiba_rbtx4927_irq_ioc_action =
    343. 

  343. TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_IOC_NAME);
    344. 

  344. #ifdef CONFIG_TOSHIBA_FPCIB0
    345. 

  345. static struct irqaction toshiba_rbtx4927_irq_isa_master =
    346. 

  346. TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/M");
    347. 

  347. static struct irqaction toshiba_rbtx4927_irq_isa_slave =
    348. 

  348. TOSHIBA_RBTX4927_PIC_ACTION(TOSHIBA_RBTX4927_ISA_NAME "/S");
    349. 

  349. #endif
    350. 

  350. 

  351. 

  352. /**********************************************************************************/
    353. 

  353. /* Functions for ioc                                                              */
    354. 

  354. /**********************************************************************************/
    355. 

  355. 

  356. 

  357. static void __init toshiba_rbtx4927_irq_ioc_init(void)
    358. 

  358. {
    359. 

  359. 	int i;
    360. 

  360. 

  361. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_INIT,
    362. 

  362. 				     "beg=%d end=%d\n",
    363. 

  363. 				     TOSHIBA_RBTX4927_IRQ_IOC_BEG,
    364. 

  364. 				     TOSHIBA_RBTX4927_IRQ_IOC_END);
    365. 

  365. 

  366. 	for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
    367. 

  367. 	     i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) {
    368. 

  368. 		irq_desc[i].status = IRQ_DISABLED;
    369. 

  369. 		irq_desc[i].action = 0;
    370. 

  370. 		irq_desc[i].depth = 3;
    371. 

  371. 		irq_desc[i].handler = &toshiba_rbtx4927_irq_ioc_type;
    372. 

  372. 	}
    373. 

  373. 

  374. 	setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
    375. 

  375. 		  &toshiba_rbtx4927_irq_ioc_action);
    376. 

  376. 

  377. 	return;
    378. 

  378. }
    379. 

  379. 

  380. static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq)
    381. 

  381. {
    382. 

  382. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP,
    383. 

  383. 				     "irq=%d\n", irq);
    384. 

  384. 

  385. 	if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
    386. 

  386. 	    || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
    387. 

  387. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    388. 

  388. 					     "bad irq=%d\n", irq);
    389. 

  389. 		panic("\n");
    390. 

  390. 	}
    391. 

  391. 

  392. 	toshiba_rbtx4927_irq_ioc_enable(irq);
    393. 

  393. 

  394. 	return (0);
    395. 

  395. }
    396. 

  396. 

  397. 

  398. static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq)
    399. 

  399. {
    400. 

  400. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN,
    401. 

  401. 				     "irq=%d\n", irq);
    402. 

  402. 

  403. 	if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
    404. 

  404. 	    || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
    405. 

  405. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    406. 

  406. 					     "bad irq=%d\n", irq);
    407. 

  407. 		panic("\n");
    408. 

  408. 	}
    409. 

  409. 

  410. 	toshiba_rbtx4927_irq_ioc_disable(irq);
    411. 

  411. 

  412. 	return;
    413. 

  413. }
    414. 

  414. 

  415. 

  416. static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
    417. 

  417. {
    418. 

  418. 	unsigned long flags;
    419. 

  419. 	volatile unsigned char v;
    420. 

  420. 

  421. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
    422. 

  422. 				     "irq=%d\n", irq);
    423. 

  423. 

  424. 	if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
    425. 

  425. 	    || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
    426. 

  426. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    427. 

  427. 					     "bad irq=%d\n", irq);
    428. 

  428. 		panic("\n");
    429. 

  429. 	}
    430. 

  430. 

  431. 	spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
    432. 

  432. 

  433. 	v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
    434. 

  434. 	v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
    435. 

  435. 	TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
    436. 

  436. 

  437. 	spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
    438. 

  438. 

  439. 	return;
    440. 

  440. }
    441. 

  441. 

  442. 

  443. static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
    444. 

  444. {
    445. 

  445. 	unsigned long flags;
    446. 

  446. 	volatile unsigned char v;
    447. 

  447. 

  448. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
    449. 

  449. 				     "irq=%d\n", irq);
    450. 

  450. 

  451. 	if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
    452. 

  452. 	    || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
    453. 

  453. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    454. 

  454. 					     "bad irq=%d\n", irq);
    455. 

  455. 		panic("\n");
    456. 

  456. 	}
    457. 

  457. 

  458. 	spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
    459. 

  459. 

  460. 	v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
    461. 

  461. 	v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
    462. 

  462. 	TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
    463. 

  463. 

  464. 	spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
    465. 

  465. 

  466. 	return;
    467. 

  467. }
    468. 

  468. 

  469. 

  470. static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq)
    471. 

  471. {
    472. 

  472. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK,
    473. 

  473. 				     "irq=%d\n", irq);
    474. 

  474. 

  475. 	if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
    476. 

  476. 	    || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
    477. 

  477. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    478. 

  478. 					     "bad irq=%d\n", irq);
    479. 

  479. 		panic("\n");
    480. 

  480. 	}
    481. 

  481. 

  482. 	toshiba_rbtx4927_irq_ioc_disable(irq);
    483. 

  483. 

  484. 	return;
    485. 

  485. }
    486. 

  486. 

  487. 

  488. static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
    489. 

  489. {
    490. 

  490. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
    491. 

  491. 				     "irq=%d\n", irq);
    492. 

  492. 

  493. 	if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
    494. 

  494. 	    || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
    495. 

  495. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    496. 

  496. 					     "bad irq=%d\n", irq);
    497. 

  497. 		panic("\n");
    498. 

  498. 	}
    499. 

  499. 

  500. 	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
    501. 

  501. 		toshiba_rbtx4927_irq_ioc_enable(irq);
    502. 

  502. 	}
    503. 

  503. 

  504. 	return;
    505. 

  505. }
    506. 

  506. 

  507. 

  508. /**********************************************************************************/
    509. 

  509. /* Functions for isa                                                              */
    510. 

  510. /**********************************************************************************/
    511. 

  511. 

  512. 

  513. #ifdef CONFIG_TOSHIBA_FPCIB0
    514. 

  514. static void __init toshiba_rbtx4927_irq_isa_init(void)
    515. 

  515. {
    516. 

  516. 	int i;
    517. 

  517. 

  518. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_INIT,
    519. 

  519. 				     "beg=%d end=%d\n",
    520. 

  520. 				     TOSHIBA_RBTX4927_IRQ_ISA_BEG,
    521. 

  521. 				     TOSHIBA_RBTX4927_IRQ_ISA_END);
    522. 

  522. 

  523. 	for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
    524. 

  524. 	     i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) {
    525. 

  525. 		irq_desc[i].status = IRQ_DISABLED;
    526. 

  526. 		irq_desc[i].action = 0;
    527. 

  527. 		irq_desc[i].depth =
    528. 

  528. 		    ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
    529. 

  529. 		irq_desc[i].handler = &toshiba_rbtx4927_irq_isa_type;
    530. 

  530. 	}
    531. 

  531. 

  532. 	setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
    533. 

  533. 		  &toshiba_rbtx4927_irq_isa_master);
    534. 

  534. 	setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_ISA,
    535. 

  535. 		  &toshiba_rbtx4927_irq_isa_slave);
    536. 

  536. 

  537. 	/* make sure we are looking at IRR (not ISR) */
    538. 

  538. 	outb(0x0A, 0x20);
    539. 

  539. 	outb(0x0A, 0xA0);
    540. 

  540. 

  541. 	return;
    542. 

  542. }
    543. 

  543. #endif
    544. 

  544. 

  545. 

  546. #ifdef CONFIG_TOSHIBA_FPCIB0
    547. 

  547. static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq)
    548. 

  548. {
    549. 

  549. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP,
    550. 

  550. 				     "irq=%d\n", irq);
    551. 

  551. 

  552. 	if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
    553. 

  553. 	    || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
    554. 

  554. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    555. 

  555. 					     "bad irq=%d\n", irq);
    556. 

  556. 		panic("\n");
    557. 

  557. 	}
    558. 

  558. 

  559. 	toshiba_rbtx4927_irq_isa_enable(irq);
    560. 

  560. 

  561. 	return (0);
    562. 

  562. }
    563. 

  563. #endif
    564. 

  564. 

  565. 

  566. #ifdef CONFIG_TOSHIBA_FPCIB0
    567. 

  567. static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq)
    568. 

  568. {
    569. 

  569. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN,
    570. 

  570. 				     "irq=%d\n", irq);
    571. 

  571. 

  572. 	if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
    573. 

  573. 	    || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
    574. 

  574. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    575. 

  575. 					     "bad irq=%d\n", irq);
    576. 

  576. 		panic("\n");
    577. 

  577. 	}
    578. 

  578. 

  579. 	toshiba_rbtx4927_irq_isa_disable(irq);
    580. 

  580. 

  581. 	return;
    582. 

  582. }
    583. 

  583. #endif
    584. 

  584. 

  585. 

  586. #ifdef CONFIG_TOSHIBA_FPCIB0
    587. 

  587. static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
    588. 

  588. {
    589. 

  589. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENABLE,
    590. 

  590. 				     "irq=%d\n", irq);
    591. 

  591. 

  592. 	if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
    593. 

  593. 	    || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
    594. 

  594. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    595. 

  595. 					     "bad irq=%d\n", irq);
    596. 

  596. 		panic("\n");
    597. 

  597. 	}
    598. 

  598. 

  599. 	enable_8259A_irq(irq);
    600. 

  600. 

  601. 	return;
    602. 

  602. }
    603. 

  603. #endif
    604. 

  604. 

  605. 

  606. #ifdef CONFIG_TOSHIBA_FPCIB0
    607. 

  607. static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
    608. 

  608. {
    609. 

  609. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_DISABLE,
    610. 

  610. 				     "irq=%d\n", irq);
    611. 

  611. 

  612. 	if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
    613. 

  613. 	    || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
    614. 

  614. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    615. 

  615. 					     "bad irq=%d\n", irq);
    616. 

  616. 		panic("\n");
    617. 

  617. 	}
    618. 

  618. 

  619. 	disable_8259A_irq(irq);
    620. 

  620. 

  621. 	return;
    622. 

  622. }
    623. 

  623. #endif
    624. 

  624. 

  625. 

  626. #ifdef CONFIG_TOSHIBA_FPCIB0
    627. 

  627. static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
    628. 

  628. {
    629. 

  629. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_MASK,
    630. 

  630. 				     "irq=%d\n", irq);
    631. 

  631. 

  632. 	if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
    633. 

  633. 	    || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
    634. 

  634. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    635. 

  635. 					     "bad irq=%d\n", irq);
    636. 

  636. 		panic("\n");
    637. 

  637. 	}
    638. 

  638. 

  639. 	mask_and_ack_8259A(irq);
    640. 

  640. 

  641. 	return;
    642. 

  642. }
    643. 

  643. #endif
    644. 

  644. 

  645. 

  646. #ifdef CONFIG_TOSHIBA_FPCIB0
    647. 

  647. static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
    648. 

  648. {
    649. 

  649. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_ENDIRQ,
    650. 

  650. 				     "irq=%d\n", irq);
    651. 

  651. 

  652. 	if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
    653. 

  653. 	    || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
    654. 

  654. 		TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
    655. 

  655. 					     "bad irq=%d\n", irq);
    656. 

  656. 		panic("\n");
    657. 

  657. 	}
    658. 

  658. 

  659. 	if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
    660. 

  660. 		toshiba_rbtx4927_irq_isa_enable(irq);
    661. 

  661. 	}
    662. 

  662. 

  663. 	return;
    664. 

  664. }
    665. 

  665. #endif
    666. 

  666. 

  667. 

  668. void __init arch_init_irq(void)
    669. 

  669. {
    670. 

  670. 	extern void tx4927_irq_init(void);
    671. 

  671. 

  672. 	local_irq_disable();
    673. 

  673. 

  674. 	tx4927_irq_init();
    675. 

  675. 	toshiba_rbtx4927_irq_ioc_init();
    676. 

  676. #ifdef CONFIG_TOSHIBA_FPCIB0
    677. 

  677. 	{
    678. 

  678. 		if (tx4927_using_backplane) {
    679. 

  679. 			toshiba_rbtx4927_irq_isa_init();
    680. 

  680. 		}
    681. 

  681. 	}
    682. 

  682. #endif
    683. 

  683. 

  684. 	wbflush();
    685. 

  685. 

  686. 	return;
    687. 

  687. }
    688. 

  688. 

  689. void toshiba_rbtx4927_irq_dump(char *key)
    690. 

  690. {
    691. 

  691. #ifdef TOSHIBA_RBTX4927_IRQ_DEBUG
    692. 

  692. 	{
    693. 

  693. 		u32 i, j = 0;
    694. 

  694. 		for (i = 0; i < NR_IRQS; i++) {
    695. 

  695. 			if (strcmp(irq_desc[i].handler->typename, "none")
    696. 

  696. 			    == 0)
    697. 

  697. 				continue;
    698. 

  698. 

  699. 			if ((i >= 1)
    700. 

  700. 			    && (irq_desc[i - 1].handler->typename ==
    701. 

  701. 				irq_desc[i].handler->typename)) {
    702. 

  702. 				j++;
    703. 

  703. 			} else {
    704. 

  704. 				j = 0;
    705. 

  705. 			}
    706. 

  706. 			TOSHIBA_RBTX4927_IRQ_DPRINTK
    707. 

  707. 			    (TOSHIBA_RBTX4927_IRQ_INFO,
    708. 

  708. 			     "%s irq=0x%02x/%3d s=0x%08x h=0x%08x a=0x%08x ah=0x%08x d=%1d n=%s/%02d\n",
    709. 

  709. 			     key, i, i, irq_desc[i].status,
    710. 

  710. 			     (u32) irq_desc[i].handler,
    711. 

  711. 			     (u32) irq_desc[i].action,
    712. 

  712. 			     (u32) (irq_desc[i].action ? irq_desc[i].
    713. 

  713. 				    action->handler : 0),
    714. 

  714. 			     irq_desc[i].depth,
    715. 

  715. 			     irq_desc[i].handler->typename, j);
    716. 

  716. 		}
    717. 

  717. 	}
    718. 

  718. #endif
    719. 

  719. 	return;
    720. 

  720. }
    721. 

  721. 

  722. void toshiba_rbtx4927_irq_dump_pics(char *s)
    723. 

  723. {
    724. 

  724. 	u32 level0_m;
    725. 

  725. 	u32 level0_s;
    726. 

  726. 	u32 level1_m;
    727. 

  727. 	u32 level1_s;
    728. 

  728. 	u32 level2;
    729. 

  729. 	u32 level2_p;
    730. 

  730. 	u32 level2_s;
    731. 

  731. 	u32 level3_m;
    732. 

  732. 	u32 level3_s;
    733. 

  733. 	u32 level4_m;
    734. 

  734. 	u32 level4_s;
    735. 

  735. 	u32 level5_m;
    736. 

  736. 	u32 level5_s;
    737. 

  737. 

  738. 	if (s == NULL)
    739. 

  739. 		s = "null";
    740. 

  740. 

  741. 	level0_m = (read_c0_status() & 0x0000ff00) >> 8;
    742. 

  742. 	level0_s = (read_c0_cause() & 0x0000ff00) >> 8;
    743. 

  743. 

  744. 	level1_m = level0_m;
    745. 

  745. 	level1_s = level0_s & 0x87;
    746. 

  746. 

  747. 	level2 = TX4927_RD(0xff1ff6a0);
    748. 

  748. 	level2_p = (((level2 & 0x10000)) ? 0 : 1);
    749. 

  749. 	level2_s = (((level2 & 0x1f) == 0x1f) ? 0 : (level2 & 0x1f));
    750. 

  750. 

  751. 	level3_m = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_ENAB) & 0x1f;
    752. 

  752. 	level3_s = reg_rd08(TOSHIBA_RBTX4927_IOC_INTR_STAT) & 0x1f;
    753. 

  753. 

  754. 	level4_m = inb(0x21);
    755. 

  755. 	outb(0x0A, 0x20);
    756. 

  756. 	level4_s = inb(0x20);
    757. 

  757. 

  758. 	level5_m = inb(0xa1);
    759. 

  759. 	outb(0x0A, 0xa0);
    760. 

  760. 	level5_s = inb(0xa0);
    761. 

  761. 

  762. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
    763. 

  763. 				     "dump_raw_pic() ");
    764. 

  764. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
    765. 

  765. 				     "cp0:m=0x%02x/s=0x%02x ", level0_m,
    766. 

  766. 				     level0_s);
    767. 

  767. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
    768. 

  768. 				     "cp0:m=0x%02x/s=0x%02x ", level1_m,
    769. 

  769. 				     level1_s);
    770. 

  770. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
    771. 

  771. 				     "pic:e=0x%02x/s=0x%02x ", level2_p,
    772. 

  772. 				     level2_s);
    773. 

  773. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
    774. 

  774. 				     "ioc:m=0x%02x/s=0x%02x ", level3_m,
    775. 

  775. 				     level3_s);
    776. 

  776. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
    777. 

  777. 				     "sbm:m=0x%02x/s=0x%02x ", level4_m,
    778. 

  778. 				     level4_s);
    779. 

  779. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO,
    780. 

  780. 				     "sbs:m=0x%02x/s=0x%02x ", level5_m,
    781. 

  781. 				     level5_s);
    782. 

  782. 	TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
    783. 

  783. 				     s);
    784. 

  784. 

  785. 	return;
    786. 

  786. }
    787.