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#! | 23 lines | 23 code | 0 blank | 0 comment | 0 complexity | e0509cec7a6fa1d53eab680b68a568e8 MD5 | raw file
 11. Need to figure out why PCI writes to the IOC3 hang, and if it is okay
 2not to write to the IOC3 ever.
 32. Need to figure out RRB allocation in bridge_startup().
 43. Need to figure out why address swaizzling is needed in inw/outw for
 5Qlogic scsi controllers.
 64. Need to integrate ip27-klconfig.c:find_lboard and
 7ip27-init.c:find_lbaord_real. DONE
 85. Is it okay to set calias space on all nodes as 0, instead of 8k as
 9in irix?
106. Investigate why things do not work without the setup_test() call
11being invoked on all nodes in ip27-memory.c.
127. Too many CLIs in the locore handlers :
13For the low level handlers set up by set_except_vector(),
14__tlb_refill_debug_tramp, __xtlb_refill_debug_tramp and cacheerror,
15investigate whether the code should do CLI, STI or KMODE.
168. Too many do_page_faults invoked - investigate.
179. start_thread must turn off UX64 ... and define tlb_refill_debug.
1810. Need a bad pmd table, bad pte table. __bad_pmd_table/__bad_pagetable
19does not agree with pgd_bad/pmd_bad.
2011. All intrs (ip27_do_irq handlers) are targetted at cpu A on the node.
21This might need to change later. Only the timer intr is set up to be
22received on both Cpu A and B. (ip27_do_irq()/bridge_startup())
2313. Cache flushing (specially the SMP version) has to be investigated.