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/arch/mips/momentum/ocelot_g/setup.c

https://bitbucket.org/evzijst/gittest
C | 266 lines | 141 code | 40 blank | 85 comment | 4 complexity | d50f985d4a278ec2a8294573dcc11d88 MD5 | raw file
  1/*
  2 * BRIEF MODULE DESCRIPTION
  3 * Momentum Computer Ocelot-G (CP7000G) - board dependent boot routines
  4 *
  5 * Copyright (C) 1996, 1997, 2001  Ralf Baechle
  6 * Copyright (C) 2000 RidgeRun, Inc.
  7 * Copyright (C) 2001 Red Hat, Inc.
  8 * Copyright (C) 2002 Momentum Computer
  9 *
 10 * Author: Matthew Dharm, Momentum Computer
 11 *   mdharm@momenco.com
 12 *
 13 * Author: RidgeRun, Inc.
 14 *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
 15 *
 16 * Copyright 2001 MontaVista Software Inc.
 17 * Author: jsun@mvista.com or jsun@junsun.net
 18 *
 19 *  This program is free software; you can redistribute  it and/or modify it
 20 *  under  the terms of  the GNU General  Public License as published by the
 21 *  Free Software Foundation;  either version 2 of the  License, or (at your
 22 *  option) any later version.
 23 *
 24 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 25 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 26 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 27 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 28 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 29 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 30 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 31 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 32 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 33 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 34 *
 35 *  You should have received a copy of the  GNU General Public License along
 36 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 37 *  675 Mass Ave, Cambridge, MA 02139, USA.
 38 *
 39 */
 40#include <linux/config.h>
 41#include <linux/init.h>
 42#include <linux/kernel.h>
 43#include <linux/types.h>
 44#include <linux/mm.h>
 45#include <linux/swap.h>
 46#include <linux/ioport.h>
 47#include <linux/sched.h>
 48#include <linux/interrupt.h>
 49#include <linux/pci.h>
 50#include <linux/timex.h>
 51#include <linux/vmalloc.h>
 52#include <asm/time.h>
 53#include <asm/bootinfo.h>
 54#include <asm/page.h>
 55#include <asm/io.h>
 56#include <asm/gt64240.h>
 57#include <asm/irq.h>
 58#include <asm/pci.h>
 59#include <asm/processor.h>
 60#include <asm/ptrace.h>
 61#include <asm/reboot.h>
 62#include <linux/bootmem.h>
 63
 64#include "ocelot_pld.h"
 65
 66#ifdef CONFIG_GALILLEO_GT64240_ETH
 67extern unsigned char prom_mac_addr_base[6];
 68#endif
 69
 70unsigned long marvell_base;
 71
 72/* These functions are used for rebooting or halting the machine*/
 73extern void momenco_ocelot_restart(char *command);
 74extern void momenco_ocelot_halt(void);
 75extern void momenco_ocelot_power_off(void);
 76
 77extern void gt64240_time_init(void);
 78extern void momenco_ocelot_irq_setup(void);
 79
 80static char reset_reason;
 81
 82static unsigned long ENTRYLO(unsigned long paddr)
 83{
 84	return ((paddr & PAGE_MASK) |
 85	       (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
 86		_CACHE_UNCACHED)) >> 6;
 87}
 88
 89/* setup code for a handoff from a version 2 PMON 2000 PROM */
 90void PMON_v2_setup(void)
 91{
 92	/* A wired TLB entry for the GT64240 and the serial port. The
 93	   GT64240 is going to be hit on every IRQ anyway - there's
 94	   absolutely no point in letting it be a random TLB entry, as
 95	   it'll just cause needless churning of the TLB. And we use
 96	   the other half for the serial port, which is just a PITA
 97	   otherwise :)
 98
 99		Device			Physical	Virtual
100		GT64240 Internal Regs	0xf4000000	0xe0000000
101		UARTs (CS2)		0xfd000000	0xe0001000
102	*/
103	add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
104	                0xf4000000, PM_64K);
105	add_wired_entry(ENTRYLO(0xfd000000), ENTRYLO(0xfd001000),
106	                0xfd000000, PM_4K);
107
108	/* Also a temporary entry to let us talk to the Ocelot PLD and NVRAM
109	   in the CS[012] region. We can't use ioremap() yet. The NVRAM
110	   is a ST M48T37Y, which includes NVRAM, RTC, and Watchdog functions.
111
112		Ocelot PLD (CS0)	0xfc000000	0xe0020000
113		NVRAM (CS1)		0xfc800000	0xe0030000
114	*/
115	add_temporary_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfc010000),
116	                    0xfc000000, PM_64K);
117	add_temporary_entry(ENTRYLO(0xfc800000), ENTRYLO(0xfc810000),
118	                    0xfc800000, PM_64K);
119
120	marvell_base = 0xf4000000;
121}
122
123extern int rm7k_tcache_enabled;
124
125/*
126 * This runs in KSEG1. See the verbiage in rm7k.c::probe_scache()
127 */
128#define Page_Invalidate_T 0x16
129static void __init setup_l3cache(unsigned long size)
130{
131	int register i;
132
133	printk("Enabling L3 cache...");
134
135	/* Enable the L3 cache in the GT64120A's CPU Configuration register */
136	MV_WRITE(0, MV_READ(0) | (1<<14));
137
138	/* Enable the L3 cache in the CPU */
139	set_c0_config(1<<12 /* CONF_TE */);
140
141	/* Clear the cache */
142	write_c0_taglo(0);
143	write_c0_taghi(0);
144
145	for (i=0; i < size; i+= 4096) {
146		__asm__ __volatile__ (
147			".set noreorder\n\t"
148			".set mips3\n\t"
149			"cache %1, (%0)\n\t"
150			".set mips0\n\t"
151			".set reorder"
152			:
153			: "r" (KSEG0ADDR(i)),
154			  "i" (Page_Invalidate_T));
155	}
156
157	/* Let the RM7000 MM code know that the tertiary cache is enabled */
158	rm7k_tcache_enabled = 1;
159
160	printk("Done\n");
161}
162
163static int  __init momenco_ocelot_g_setup(void)
164{
165	void (*l3func)(unsigned long) = (void *) KSEG1ADDR(setup_l3cache);
166	unsigned int tmpword;
167
168	board_time_init = gt64240_time_init;
169
170	_machine_restart = momenco_ocelot_restart;
171	_machine_halt = momenco_ocelot_halt;
172	_machine_power_off = momenco_ocelot_power_off;
173
174	/*
175	 * initrd_start = (ulong)ocelot_initrd_start;
176	 * initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
177	 * initrd_below_start_ok = 1;
178	 */
179
180	/* do handoff reconfiguration */
181	PMON_v2_setup();
182
183#ifdef CONFIG_GALILLEO_GT64240_ETH
184	/* get the mac addr */
185	memcpy(prom_mac_addr_base, (void*)0xfc807cf2, 6);
186#endif
187
188	/* Turn off the Bit-Error LED */
189	OCELOT_PLD_WRITE(0x80, INTCLR);
190
191	tmpword = OCELOT_PLD_READ(BOARDREV);
192	if (tmpword < 26)
193		printk("Momenco Ocelot-G: Board Assembly Rev. %c\n", 'A'+tmpword);
194	else
195		printk("Momenco Ocelot-G: Board Assembly Revision #0x%x\n", tmpword);
196
197	tmpword = OCELOT_PLD_READ(PLD1_ID);
198	printk("PLD 1 ID: %d.%d\n", tmpword>>4, tmpword&15);
199	tmpword = OCELOT_PLD_READ(PLD2_ID);
200	printk("PLD 2 ID: %d.%d\n", tmpword>>4, tmpword&15);
201	tmpword = OCELOT_PLD_READ(RESET_STATUS);
202	printk("Reset reason: 0x%x\n", tmpword);
203	reset_reason = tmpword;
204	OCELOT_PLD_WRITE(0xff, RESET_STATUS);
205
206	tmpword = OCELOT_PLD_READ(BOARD_STATUS);
207	printk("Board Status register: 0x%02x\n", tmpword);
208	printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
209	printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
210	printk("  - Tulip PHY %s connected\n", (tmpword&0x10)?"is":"not");
211	printk("  - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
212	printk("  - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
213
214	if (tmpword&12)
215		l3func((1<<(((tmpword&12) >> 2)+20)));
216
217	switch(tmpword &3) {
218	case 3:
219		/* 512MiB -- two banks of 256MiB */
220		add_memory_region(  0x0<<20, 0x100<<20, BOOT_MEM_RAM);
221/*
222		add_memory_region(0x100<<20, 0x100<<20, BOOT_MEM_RAM);
223*/
224		break;
225	case 2:
226		/* 256MiB -- two banks of 128MiB */
227		add_memory_region( 0x0<<20, 0x80<<20, BOOT_MEM_RAM);
228		add_memory_region(0x80<<20, 0x80<<20, BOOT_MEM_RAM);
229		break;
230	case 1:
231		/* 128MiB -- 64MiB per bank */
232		add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
233		add_memory_region(0x40<<20, 0x40<<20, BOOT_MEM_RAM);
234		break;
235	case 0:
236		/* 64MiB */
237		add_memory_region( 0x0<<20, 0x40<<20, BOOT_MEM_RAM);
238		break;
239	}
240
241	/* FIXME: Fix up the DiskOnChip mapping */
242	MV_WRITE(0x468, 0xfef73);
243
244	return 0;
245}
246
247early_initcall(momenco_ocelot_g_setup);
248
249/* This needs to be one of the first initcalls, because no I/O port access
250   can work before this */
251
252static int io_base_ioremap(void)
253{
254	/* we're mapping PCI accesses from 0xc0000000 to 0xf0000000 */
255	unsigned long io_remap_range;
256
257	io_remap_range = (unsigned long) ioremap(0xc0000000, 0x30000000);
258	if (!io_remap_range)
259		panic("Could not ioremap I/O port range");
260
261	set_io_port_base(io_remap_range - 0xc0000000);
262
263	return 0;
264}
265
266module_init(io_base_ioremap);