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/arch/mips/momentum/ocelot_c/irq.c

https://bitbucket.org/evzijst/gittest
C | 83 lines | 40 code | 7 blank | 36 comment | 0 complexity | 9ffd2e8063554c0138791490faa0f899 MD5 | raw file
 1/*
 2 * Copyright (C) 2000 RidgeRun, Inc.
 3 * Author: RidgeRun, Inc.
 4 *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
 5 *
 6 * Copyright 2001 MontaVista Software Inc.
 7 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
 8 * Copyright (C) 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
 9 *
10 *  This program is free software; you can redistribute  it and/or modify it
11 *  under  the terms of  the GNU General  Public License as published by the
12 *  Free Software Foundation;  either version 2 of the  License, or (at your
13 *  option) any later version.
14 *
15 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
16 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
17 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
18 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
19 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
21 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
23 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 *  You should have received a copy of the  GNU General Public License along
27 *  with this program; if not, write  to the Free Software Foundation, Inc.,
28 *  675 Mass Ave, Cambridge, MA 02139, USA.
29 *
30 */
31#include <linux/errno.h>
32#include <linux/init.h>
33#include <linux/kernel_stat.h>
34#include <linux/module.h>
35#include <linux/signal.h>
36#include <linux/sched.h>
37#include <linux/types.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/timex.h>
41#include <linux/slab.h>
42#include <linux/random.h>
43#include <linux/bitops.h>
44#include <asm/bootinfo.h>
45#include <asm/io.h>
46#include <asm/irq_cpu.h>
47#include <asm/mipsregs.h>
48#include <asm/mv64340.h>
49#include <asm/system.h>
50
51extern asmlinkage void ocelot_handle_int(void);
52extern void uart_irq_init(void);
53extern void cpci_irq_init(void);
54
55static struct irqaction cascade_fpga = {
56	no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via FPGA", NULL, NULL
57};
58
59static struct irqaction cascade_mv64340 = {
60	no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
61};
62
63void __init arch_init_irq(void)
64{
65	/*
66	 * Clear all of the interrupts while we change the able around a bit.
67	 * int-handler is not on bootstrap
68	 */
69	clear_c0_status(ST0_IM);
70
71	/* Sets the first-level interrupt dispatcher. */
72	set_except_vector(0, ocelot_handle_int);
73	mips_cpu_irq_init(0);
74
75	/* set up the cascading interrupts */
76	setup_irq(3, &cascade_fpga);
77	setup_irq(5, &cascade_fpga);
78	setup_irq(6, &cascade_mv64340);
79
80	mv64340_irq_init(16);
81	uart_irq_init();
82	cpci_irq_init();
83}