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/arch/mips/momentum/ocelot_3/setup.c

https://bitbucket.org/evzijst/gittest
C | 398 lines | 235 code | 68 blank | 95 comment | 10 complexity | d82b8166b0428e583434f49c67089f27 MD5 | raw file
  1/*
  2 * setup.c
  3 *
  4 * BRIEF MODULE DESCRIPTION
  5 * Momentum Computer Ocelot-3 board dependent boot routines
  6 *
  7 * Copyright (C) 1996, 1997, 01, 05  Ralf Baechle
  8 * Copyright (C) 2000 RidgeRun, Inc.
  9 * Copyright (C) 2001 Red Hat, Inc.
 10 * Copyright (C) 2002 Momentum Computer
 11 *
 12 * Author: Matthew Dharm, Momentum Computer
 13 *   mdharm@momenco.com
 14 *
 15 * Louis Hamilton, Red Hat, Inc.
 16 *   hamilton@redhat.com  [MIPS64 modifications]
 17 *
 18 * Author: RidgeRun, Inc.
 19 *   glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
 20 *
 21 * Copyright 2001 MontaVista Software Inc.
 22 * Author: jsun@mvista.com or jsun@junsun.net
 23 *
 24 * Copyright 2004 PMC-Sierra
 25 * Author: Manish Lachwani (lachwani@pmc-sierra.com)
 26 *
 27 * Copyright (C) 2004 MontaVista Software Inc.
 28 * Author: Manish Lachwani, mlachwani@mvista.com
 29 *
 30 *  This program is free software; you can redistribute  it and/or modify it
 31 *  under  the terms of  the GNU General  Public License as published by the
 32 *  Free Software Foundation;  either version 2 of the  License, or (at your
 33 *  option) any later version.
 34 *
 35 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 36 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 37 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 38 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 39 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 40 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 41 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 42 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 43 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 44 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 45 *
 46 *  You should have received a copy of the  GNU General Public License along
 47 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 48 *  675 Mass Ave, Cambridge, MA 02139, USA.
 49 */
 50#include <linux/init.h>
 51#include <linux/kernel.h>
 52#include <linux/types.h>
 53#include <linux/mc146818rtc.h>
 54#include <linux/ioport.h>
 55#include <linux/interrupt.h>
 56#include <linux/pci.h>
 57#include <linux/timex.h>
 58#include <linux/bootmem.h>
 59#include <linux/mv643xx.h>
 60#include <asm/time.h>
 61#include <asm/page.h>
 62#include <asm/bootinfo.h>
 63#include <asm/io.h>
 64#include <asm/irq.h>
 65#include <asm/pci.h>
 66#include <asm/processor.h>
 67#include <asm/ptrace.h>
 68#include <asm/reboot.h>
 69#include <asm/mc146818rtc.h>
 70#include <asm/tlbflush.h>
 71#include "ocelot_3_fpga.h"
 72
 73/* Marvell Discovery Register Base */
 74unsigned long marvell_base = (signed)0xf4000000;
 75
 76/* CPU clock */
 77unsigned long cpu_clock;
 78
 79/* RTC/NVRAM */
 80unsigned char* rtc_base = (unsigned char*)(signed)0xfc800000;
 81
 82/* FPGA Base */
 83unsigned long ocelot_fpga_base = (signed)0xfc000000;
 84
 85/* Serial base */
 86unsigned long uart_base = (signed)0xfd000000;
 87
 88/*
 89 * Marvell Discovery SRAM. This is one place where Ethernet
 90 * Tx and Rx descriptors can be placed to improve performance
 91 */
 92extern unsigned long mv64340_sram_base;
 93
 94/* These functions are used for rebooting or halting the machine*/
 95extern void momenco_ocelot_restart(char *command);
 96extern void momenco_ocelot_halt(void);
 97extern void momenco_ocelot_power_off(void);
 98
 99void momenco_time_init(void);
100static char reset_reason;
101
102void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
103		     unsigned long entryhi, unsigned long pagemask);
104
105static inline unsigned long ENTRYLO(unsigned long paddr)
106{
107	return ((paddr & PAGE_MASK) |
108		(_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
109		_CACHE_UNCACHED)) >> 6;
110}
111
112void __init bus_error_init(void)
113{
114	/* nothing */
115}
116
117/*
118 * setup code for a handoff from a version 2 PMON 2000 PROM
119 */
120void setup_wired_tlb_entries(void)
121{
122	write_c0_wired(0);
123	local_flush_tlb_all();
124
125	/* marvell and extra space */
126	add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000), (signed)0xf4000000, PM_64K);
127
128	/* fpga, rtc, and uart */
129	add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000), (signed)0xfc000000, PM_16M);
130}
131
132#define CONV_BCD_TO_BIN(val)	(((val) & 0xf) + (((val) >> 4) * 10))
133#define CONV_BIN_TO_BCD(val)	(((val) % 10) + (((val) / 10) << 4))
134
135unsigned long m48t37y_get_time(void)
136{
137	unsigned int year, month, day, hour, min, sec;
138
139	/* stop the update */
140	rtc_base[0x7ff8] = 0x40;
141
142	year = CONV_BCD_TO_BIN(rtc_base[0x7fff]);
143	year += CONV_BCD_TO_BIN(rtc_base[0x7ff1]) * 100;
144
145	month = CONV_BCD_TO_BIN(rtc_base[0x7ffe]);
146
147	day = CONV_BCD_TO_BIN(rtc_base[0x7ffd]);
148
149	hour = CONV_BCD_TO_BIN(rtc_base[0x7ffb]);
150	min = CONV_BCD_TO_BIN(rtc_base[0x7ffa]);
151	sec = CONV_BCD_TO_BIN(rtc_base[0x7ff9]);
152
153	/* start the update */
154	rtc_base[0x7ff8] = 0x00;
155
156	return mktime(year, month, day, hour, min, sec);
157}
158
159int m48t37y_set_time(unsigned long sec)
160{
161	struct rtc_time tm;
162
163	/* convert to a more useful format -- note months count from 0 */
164	to_tm(sec, &tm);
165	tm.tm_mon += 1;
166
167	/* enable writing */
168	rtc_base[0x7ff8] = 0x80;
169
170	/* year */
171	rtc_base[0x7fff] = CONV_BIN_TO_BCD(tm.tm_year % 100);
172	rtc_base[0x7ff1] = CONV_BIN_TO_BCD(tm.tm_year / 100);
173
174	/* month */
175	rtc_base[0x7ffe] = CONV_BIN_TO_BCD(tm.tm_mon);
176
177	/* day */
178	rtc_base[0x7ffd] = CONV_BIN_TO_BCD(tm.tm_mday);
179
180	/* hour/min/sec */
181	rtc_base[0x7ffb] = CONV_BIN_TO_BCD(tm.tm_hour);
182	rtc_base[0x7ffa] = CONV_BIN_TO_BCD(tm.tm_min);
183	rtc_base[0x7ff9] = CONV_BIN_TO_BCD(tm.tm_sec);
184
185	/* day of week -- not really used, but let's keep it up-to-date */
186	rtc_base[0x7ffc] = CONV_BIN_TO_BCD(tm.tm_wday + 1);
187
188	/* disable writing */
189	rtc_base[0x7ff8] = 0x00;
190
191	return 0;
192}
193
194void momenco_timer_setup(struct irqaction *irq)
195{
196	setup_irq(7, irq);	/* Timer interrupt, unmask status IM7 */
197}
198
199void momenco_time_init(void)
200{
201	setup_wired_tlb_entries();
202
203	/*
204	 * Ocelot-3 board has been built with both
205	 * the Rm7900 and the Rm7065C
206	 */
207	mips_hpt_frequency = cpu_clock / 2;
208	board_timer_setup = momenco_timer_setup;
209
210	rtc_get_time = m48t37y_get_time;
211	rtc_set_time = m48t37y_set_time;
212}
213
214/*
215 * PCI Support for Ocelot-3
216 */
217
218/* Bus #0 IO and MEM space */
219#define	OCELOT_3_PCI_IO_0_START		0xe0000000
220#define	OCELOT_3_PCI_IO_0_SIZE		0x08000000
221#define	OCELOT_3_PCI_MEM_0_START	0xc0000000
222#define	OCELOT_3_PCI_MEM_0_SIZE		0x10000000
223
224/* Bus #1 IO and MEM space */
225#define	OCELOT_3_PCI_IO_1_START		0xe8000000
226#define	OCELOT_3_PCI_IO_1_SIZE		0x08000000
227#define	OCELOT_3_PCI_MEM_1_START	0xd0000000
228#define	OCELOT_3_PCI_MEM_1_SIZE		0x10000000
229
230static struct resource mv_pci_io_mem0_resource = {
231	.name	= "MV64340 PCI0 IO MEM",
232	.start	= OCELOT_3_PCI_IO_0_START,
233	.end	= OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE - 1,
234	.flags  = IORESOURCE_IO,
235};
236
237static struct resource mv_pci_io_mem1_resource = {
238	.name	= "MV64340 PCI1 IO MEM",
239	.start	= OCELOT_3_PCI_IO_1_START,
240	.end	= OCELOT_3_PCI_IO_1_START + OCELOT_3_PCI_IO_1_SIZE - 1,
241	.flags	= IORESOURCE_IO,
242};
243
244static struct resource mv_pci_mem0_resource = {
245	.name	= "MV64340 PCI0 MEM",
246	.start	= OCELOT_3_PCI_MEM_0_START,
247	.end	= OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE - 1,
248	.flags	= IORESOURCE_MEM,
249};
250
251static struct resource mv_pci_mem1_resource = {
252	.name	= "MV64340 PCI1 MEM",
253	.start	= OCELOT_3_PCI_MEM_1_START,
254	.end	= OCELOT_3_PCI_MEM_1_START + OCELOT_3_PCI_MEM_1_SIZE - 1,
255	.flags	= IORESOURCE_MEM,
256};
257
258static struct mv_pci_controller mv_bus0_controller = {
259	.pcic = {
260		 .pci_ops	= &mv_pci_ops,
261		 .mem_resource	= &mv_pci_mem0_resource,
262		 .io_resource	= &mv_pci_io_mem0_resource,
263	},
264	.config_addr	= MV64340_PCI_0_CONFIG_ADDR,
265	.config_vreg	= MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
266};
267
268static struct mv_pci_controller mv_bus1_controller = {
269	.pcic = {
270		 .pci_ops	= &mv_pci_ops,
271		 .mem_resource	= &mv_pci_mem1_resource,
272		 .io_resource	= &mv_pci_io_mem1_resource,
273	},
274	.config_addr	= MV64340_PCI_1_CONFIG_ADDR,
275	.config_vreg	= MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
276};
277
278static __init int __init ja_pci_init(void)
279{
280	uint32_t enable;
281	extern int pci_probe_only;
282
283	/* PMON will assign PCI resources */
284	pci_probe_only = 1;
285
286	enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
287	/*
288	 * We require at least one enabled I/O or PCI memory window or we
289	 * will ignore this PCI bus.  We ignore PCI windows 1, 2 and 3.
290	 */
291	if (enable & (0x01 <<  9) || enable & (0x01 << 10))
292		register_pci_controller(&mv_bus0_controller.pcic);
293
294	if (enable & (0x01 << 14) || enable & (0x01 << 15))
295		register_pci_controller(&mv_bus1_controller.pcic);
296
297	ioport_resource.end = OCELOT_3_PCI_IO_0_START + OCELOT_3_PCI_IO_0_SIZE +
298					OCELOT_3_PCI_IO_1_SIZE - 1;
299
300	iomem_resource.end = OCELOT_3_PCI_MEM_0_START + OCELOT_3_PCI_MEM_0_SIZE +
301					OCELOT_3_PCI_MEM_1_SIZE - 1;
302
303	set_io_port_base(OCELOT_3_PCI_IO_0_START); /* mips_io_port_base */
304
305	return 0;
306}
307
308arch_initcall(ja_pci_init);
309
310static int __init momenco_ocelot_3_setup(void)
311{
312	unsigned int tmpword;
313
314	board_time_init = momenco_time_init;
315
316	_machine_restart = momenco_ocelot_restart;
317	_machine_halt = momenco_ocelot_halt;
318	_machine_power_off = momenco_ocelot_power_off;
319
320	/* Wired TLB entries */
321	setup_wired_tlb_entries();
322
323	/* shut down ethernet ports, just to be sure our memory doesn't get
324	 * corrupted by random ethernet traffic.
325	 */
326	MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
327	MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
328	MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
329	MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
330	do {}
331	  while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
332	do {}
333	  while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
334	do {}
335	  while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
336	do {}
337	  while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
338	MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
339		 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
340	MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
341		 MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
342
343	/* Turn off the Bit-Error LED */
344	OCELOT_FPGA_WRITE(0x80, CLR);
345
346	tmpword = OCELOT_FPGA_READ(BOARDREV);
347	if (tmpword < 26)
348		printk("Momenco Ocelot-3: Board Assembly Rev. %c\n",
349			'A'+tmpword);
350	else
351		printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n",
352			tmpword);
353
354	tmpword = OCELOT_FPGA_READ(FPGA_REV);
355	printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
356	tmpword = OCELOT_FPGA_READ(RESET_STATUS);
357	printk("Reset reason: 0x%x\n", tmpword);
358	switch (tmpword) {
359		case 0x1:
360			printk("  - Power-up reset\n");
361			break;
362		case 0x2:
363			printk("  - Push-button reset\n");
364			break;
365		case 0x4:
366			printk("  - cPCI bus reset\n");
367			break;
368		case 0x8:
369			printk("  - Watchdog reset\n");
370			break;
371		case 0x10:
372			printk("  - Software reset\n");
373			break;
374		default:
375			printk("  - Unknown reset cause\n");
376	}
377	reset_reason = tmpword;
378	OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
379
380	tmpword = OCELOT_FPGA_READ(CPCI_ID);
381	printk("cPCI ID register: 0x%02x\n", tmpword);
382	printk("  - Slot number: %d\n", tmpword & 0x1f);
383	printk("  - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
384	printk("  - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
385
386	tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
387	printk("Board Status register: 0x%02x\n", tmpword);
388	printk("  - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
389	printk("  - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
390	printk("  - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1);
391
392	/* Support for 128 MB memory */
393	add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM);
394
395	return 0;
396}
397
398early_initcall(momenco_ocelot_3_setup);