/arch/mips/momentum/jaguar_atx/setup.c

https://bitbucket.org/evzijst/gittest · C · 474 lines · 289 code · 81 blank · 104 comment · 14 complexity · ed8983f6c8400c70d6f154e8782c98b9 MD5 · raw file

  1. /*
  2. * BRIEF MODULE DESCRIPTION
  3. * Momentum Computer Jaguar-ATX board dependent boot routines
  4. *
  5. * Copyright (C) 1996, 1997, 2001, 2004 Ralf Baechle (ralf@linux-mips.org)
  6. * Copyright (C) 2000 RidgeRun, Inc.
  7. * Copyright (C) 2001 Red Hat, Inc.
  8. * Copyright (C) 2002 Momentum Computer
  9. *
  10. * Author: Matthew Dharm, Momentum Computer
  11. * mdharm@momenco.com
  12. *
  13. * Louis Hamilton, Red Hat, Inc.
  14. * hamilton@redhat.com [MIPS64 modifications]
  15. *
  16. * Author: RidgeRun, Inc.
  17. * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  18. *
  19. * Copyright 2001 MontaVista Software Inc.
  20. * Author: jsun@mvista.com or jsun@junsun.net
  21. *
  22. * This program is free software; you can redistribute it and/or modify it
  23. * under the terms of the GNU General Public License as published by the
  24. * Free Software Foundation; either version 2 of the License, or (at your
  25. * option) any later version.
  26. *
  27. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  28. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  29. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  30. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  31. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  32. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  33. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  34. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  35. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  36. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37. *
  38. * You should have received a copy of the GNU General Public License along
  39. * with this program; if not, write to the Free Software Foundation, Inc.,
  40. * 675 Mass Ave, Cambridge, MA 02139, USA.
  41. */
  42. #include <linux/config.h>
  43. #include <linux/bcd.h>
  44. #include <linux/init.h>
  45. #include <linux/kernel.h>
  46. #include <linux/types.h>
  47. #include <linux/mm.h>
  48. #include <linux/bootmem.h>
  49. #include <linux/module.h>
  50. #include <linux/pci.h>
  51. #include <linux/swap.h>
  52. #include <linux/ioport.h>
  53. #include <linux/sched.h>
  54. #include <linux/interrupt.h>
  55. #include <linux/timex.h>
  56. #include <linux/vmalloc.h>
  57. #include <asm/time.h>
  58. #include <asm/bootinfo.h>
  59. #include <asm/page.h>
  60. #include <asm/io.h>
  61. #include <asm/irq.h>
  62. #include <asm/processor.h>
  63. #include <asm/ptrace.h>
  64. #include <asm/reboot.h>
  65. #include <asm/tlbflush.h>
  66. #include <asm/mv64340.h>
  67. #include "jaguar_atx_fpga.h"
  68. extern unsigned long mv64340_sram_base;
  69. unsigned long cpu_clock;
  70. /* These functions are used for rebooting or halting the machine*/
  71. extern void momenco_jaguar_restart(char *command);
  72. extern void momenco_jaguar_halt(void);
  73. extern void momenco_jaguar_power_off(void);
  74. void momenco_time_init(void);
  75. static char reset_reason;
  76. static inline unsigned long ENTRYLO(unsigned long paddr)
  77. {
  78. return ((paddr & PAGE_MASK) |
  79. (_PAGE_PRESENT | __READABLE | __WRITEABLE | _PAGE_GLOBAL |
  80. _CACHE_UNCACHED)) >> 6;
  81. }
  82. void __init bus_error_init(void) { /* nothing */ }
  83. /*
  84. * Load a few TLB entries for the MV64340 and perhiperals. The MV64340 is going
  85. * to be hit on every IRQ anyway - there's absolutely no point in letting it be
  86. * a random TLB entry, as it'll just cause needless churning of the TLB. And we
  87. * use the other half for the serial port, which is just a PITA otherwise :)
  88. *
  89. * Device Physical Virtual
  90. * MV64340 Internal Regs 0xf4000000 0xf4000000
  91. * Ocelot-C[S] PLD (CS0) 0xfc000000 0xfc000000
  92. * NVRAM (CS1) 0xfc800000 0xfc800000
  93. * UARTs (CS2) 0xfd000000 0xfd000000
  94. * Internal SRAM 0xfe000000 0xfe000000
  95. * M-Systems DOC (CS3) 0xff000000 0xff000000
  96. */
  97. static __init void wire_stupidity_into_tlb(void)
  98. {
  99. #ifdef CONFIG_MIPS32
  100. write_c0_wired(0);
  101. local_flush_tlb_all();
  102. /* marvell and extra space */
  103. add_wired_entry(ENTRYLO(0xf4000000), ENTRYLO(0xf4010000),
  104. 0xf4000000UL, PM_64K);
  105. /* fpga, rtc, and uart */
  106. add_wired_entry(ENTRYLO(0xfc000000), ENTRYLO(0xfd000000),
  107. 0xfc000000UL, PM_16M);
  108. // /* m-sys and internal SRAM */
  109. // add_wired_entry(ENTRYLO(0xfe000000), ENTRYLO(0xff000000),
  110. // 0xfe000000UL, PM_16M);
  111. marvell_base = 0xf4000000;
  112. //mv64340_sram_base = 0xfe000000; /* Currently unused */
  113. #endif
  114. }
  115. unsigned long marvell_base = 0xf4000000L;
  116. unsigned long ja_fpga_base = JAGUAR_ATX_CS0_ADDR;
  117. unsigned long uart_base = 0xfd000000L;
  118. static unsigned char *rtc_base = (unsigned char*) 0xfc800000L;
  119. EXPORT_SYMBOL(marvell_base);
  120. static __init int per_cpu_mappings(void)
  121. {
  122. marvell_base = (unsigned long) ioremap(0xf4000000, 0x10000);
  123. ja_fpga_base = (unsigned long) ioremap(JAGUAR_ATX_CS0_ADDR, 0x1000);
  124. uart_base = (unsigned long) ioremap(0xfd000000UL, 0x1000);
  125. rtc_base = ioremap(0xfc000000UL, 0x8000);
  126. // ioremap(0xfe000000, 32 << 20);
  127. write_c0_wired(0);
  128. local_flush_tlb_all();
  129. ja_setup_console();
  130. return 0;
  131. }
  132. arch_initcall(per_cpu_mappings);
  133. unsigned long m48t37y_get_time(void)
  134. {
  135. unsigned int year, month, day, hour, min, sec;
  136. /* stop the update */
  137. rtc_base[0x7ff8] = 0x40;
  138. year = BCD2BIN(rtc_base[0x7fff]);
  139. year += BCD2BIN(rtc_base[0x7ff1]) * 100;
  140. month = BCD2BIN(rtc_base[0x7ffe]);
  141. day = BCD2BIN(rtc_base[0x7ffd]);
  142. hour = BCD2BIN(rtc_base[0x7ffb]);
  143. min = BCD2BIN(rtc_base[0x7ffa]);
  144. sec = BCD2BIN(rtc_base[0x7ff9]);
  145. /* start the update */
  146. rtc_base[0x7ff8] = 0x00;
  147. return mktime(year, month, day, hour, min, sec);
  148. }
  149. int m48t37y_set_time(unsigned long sec)
  150. {
  151. struct rtc_time tm;
  152. /* convert to a more useful format -- note months count from 0 */
  153. to_tm(sec, &tm);
  154. tm.tm_mon += 1;
  155. /* enable writing */
  156. rtc_base[0x7ff8] = 0x80;
  157. /* year */
  158. rtc_base[0x7fff] = BIN2BCD(tm.tm_year % 100);
  159. rtc_base[0x7ff1] = BIN2BCD(tm.tm_year / 100);
  160. /* month */
  161. rtc_base[0x7ffe] = BIN2BCD(tm.tm_mon);
  162. /* day */
  163. rtc_base[0x7ffd] = BIN2BCD(tm.tm_mday);
  164. /* hour/min/sec */
  165. rtc_base[0x7ffb] = BIN2BCD(tm.tm_hour);
  166. rtc_base[0x7ffa] = BIN2BCD(tm.tm_min);
  167. rtc_base[0x7ff9] = BIN2BCD(tm.tm_sec);
  168. /* day of week -- not really used, but let's keep it up-to-date */
  169. rtc_base[0x7ffc] = BIN2BCD(tm.tm_wday + 1);
  170. /* disable writing */
  171. rtc_base[0x7ff8] = 0x00;
  172. return 0;
  173. }
  174. void momenco_timer_setup(struct irqaction *irq)
  175. {
  176. setup_irq(8, irq);
  177. }
  178. /*
  179. * Ugly but the least of all evils. TLB initialization did flush the TLB so
  180. * We need to setup mappings again before we can touch the RTC.
  181. */
  182. void momenco_time_init(void)
  183. {
  184. wire_stupidity_into_tlb();
  185. mips_hpt_frequency = cpu_clock / 2;
  186. board_timer_setup = momenco_timer_setup;
  187. rtc_get_time = m48t37y_get_time;
  188. rtc_set_time = m48t37y_set_time;
  189. }
  190. static struct resource mv_pci_io_mem0_resource = {
  191. .name = "MV64340 PCI0 IO MEM",
  192. .flags = IORESOURCE_IO
  193. };
  194. static struct resource mv_pci_mem0_resource = {
  195. .name = "MV64340 PCI0 MEM",
  196. .flags = IORESOURCE_MEM
  197. };
  198. static struct mv_pci_controller mv_bus0_controller = {
  199. .pcic = {
  200. .pci_ops = &mv_pci_ops,
  201. .mem_resource = &mv_pci_mem0_resource,
  202. .io_resource = &mv_pci_io_mem0_resource,
  203. },
  204. .config_addr = MV64340_PCI_0_CONFIG_ADDR,
  205. .config_vreg = MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG,
  206. };
  207. static uint32_t mv_io_base, mv_io_size;
  208. static void ja_pci0_init(void)
  209. {
  210. uint32_t mem0_base, mem0_size;
  211. uint32_t io_base, io_size;
  212. io_base = MV_READ(MV64340_PCI_0_IO_BASE_ADDR) << 16;
  213. io_size = (MV_READ(MV64340_PCI_0_IO_SIZE) + 1) << 16;
  214. mem0_base = MV_READ(MV64340_PCI_0_MEMORY0_BASE_ADDR) << 16;
  215. mem0_size = (MV_READ(MV64340_PCI_0_MEMORY0_SIZE) + 1) << 16;
  216. mv_pci_io_mem0_resource.start = 0;
  217. mv_pci_io_mem0_resource.end = io_size - 1;
  218. mv_pci_mem0_resource.start = mem0_base;
  219. mv_pci_mem0_resource.end = mem0_base + mem0_size - 1;
  220. mv_bus0_controller.pcic.mem_offset = mem0_base;
  221. mv_bus0_controller.pcic.io_offset = 0;
  222. ioport_resource.end = io_size - 1;
  223. register_pci_controller(&mv_bus0_controller.pcic);
  224. mv_io_base = io_base;
  225. mv_io_size = io_size;
  226. }
  227. static struct resource mv_pci_io_mem1_resource = {
  228. .name = "MV64340 PCI1 IO MEM",
  229. .flags = IORESOURCE_IO
  230. };
  231. static struct resource mv_pci_mem1_resource = {
  232. .name = "MV64340 PCI1 MEM",
  233. .flags = IORESOURCE_MEM
  234. };
  235. static struct mv_pci_controller mv_bus1_controller = {
  236. .pcic = {
  237. .pci_ops = &mv_pci_ops,
  238. .mem_resource = &mv_pci_mem1_resource,
  239. .io_resource = &mv_pci_io_mem1_resource,
  240. },
  241. .config_addr = MV64340_PCI_1_CONFIG_ADDR,
  242. .config_vreg = MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG,
  243. };
  244. static __init void ja_pci1_init(void)
  245. {
  246. uint32_t mem0_base, mem0_size;
  247. uint32_t io_base, io_size;
  248. io_base = MV_READ(MV64340_PCI_1_IO_BASE_ADDR) << 16;
  249. io_size = (MV_READ(MV64340_PCI_1_IO_SIZE) + 1) << 16;
  250. mem0_base = MV_READ(MV64340_PCI_1_MEMORY0_BASE_ADDR) << 16;
  251. mem0_size = (MV_READ(MV64340_PCI_1_MEMORY0_SIZE) + 1) << 16;
  252. /*
  253. * Here we assume the I/O window of second bus to be contiguous with
  254. * the first. A gap is no problem but would waste address space for
  255. * remapping the port space.
  256. */
  257. mv_pci_io_mem1_resource.start = mv_io_size;
  258. mv_pci_io_mem1_resource.end = mv_io_size + io_size - 1;
  259. mv_pci_mem1_resource.start = mem0_base;
  260. mv_pci_mem1_resource.end = mem0_base + mem0_size - 1;
  261. mv_bus1_controller.pcic.mem_offset = mem0_base;
  262. mv_bus1_controller.pcic.io_offset = 0;
  263. ioport_resource.end = io_base + io_size -mv_io_base - 1;
  264. register_pci_controller(&mv_bus1_controller.pcic);
  265. mv_io_size = io_base + io_size - mv_io_base;
  266. }
  267. static __init int __init ja_pci_init(void)
  268. {
  269. unsigned long io_v_base;
  270. uint32_t enable;
  271. enable = ~MV_READ(MV64340_BASE_ADDR_ENABLE);
  272. /*
  273. * We require at least one enabled I/O or PCI memory window or we
  274. * will ignore this PCI bus. We ignore PCI windows 1, 2 and 3.
  275. */
  276. if (enable & (0x01 << 9) || enable & (0x01 << 10))
  277. ja_pci0_init();
  278. if (enable & (0x01 << 14) || enable & (0x01 << 15))
  279. ja_pci1_init();
  280. if (mv_io_size) {
  281. io_v_base = (unsigned long) ioremap(mv_io_base, mv_io_size);
  282. if (!io_v_base)
  283. panic("Could not ioremap I/O port range");
  284. set_io_port_base(io_v_base);
  285. }
  286. return 0;
  287. }
  288. arch_initcall(ja_pci_init);
  289. static int __init momenco_jaguar_atx_setup(void)
  290. {
  291. unsigned int tmpword;
  292. board_time_init = momenco_time_init;
  293. _machine_restart = momenco_jaguar_restart;
  294. _machine_halt = momenco_jaguar_halt;
  295. _machine_power_off = momenco_jaguar_power_off;
  296. /*
  297. * initrd_start = (ulong)jaguar_initrd_start;
  298. * initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size;
  299. * initrd_below_start_ok = 1;
  300. */
  301. wire_stupidity_into_tlb();
  302. /*
  303. * shut down ethernet ports, just to be sure our memory doesn't get
  304. * corrupted by random ethernet traffic.
  305. */
  306. MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
  307. MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
  308. MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
  309. MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
  310. MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
  311. MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
  312. while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
  313. while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
  314. while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
  315. while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
  316. while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
  317. while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
  318. MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
  319. MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
  320. MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
  321. MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
  322. MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2),
  323. MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
  324. /* Turn off the Bit-Error LED */
  325. JAGUAR_FPGA_WRITE(0x80, CLR);
  326. tmpword = JAGUAR_FPGA_READ(BOARDREV);
  327. if (tmpword < 26)
  328. printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
  329. 'A'+tmpword);
  330. else
  331. printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
  332. tmpword);
  333. tmpword = JAGUAR_FPGA_READ(FPGA_REV);
  334. printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
  335. tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
  336. printk("Reset reason: 0x%x\n", tmpword);
  337. switch (tmpword) {
  338. case 0x1:
  339. printk(" - Power-up reset\n");
  340. break;
  341. case 0x2:
  342. printk(" - Push-button reset\n");
  343. break;
  344. case 0x8:
  345. printk(" - Watchdog reset\n");
  346. break;
  347. case 0x10:
  348. printk(" - JTAG reset\n");
  349. break;
  350. default:
  351. printk(" - Unknown reset cause\n");
  352. }
  353. reset_reason = tmpword;
  354. JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
  355. tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
  356. printk("Board Status register: 0x%02x\n", tmpword);
  357. printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
  358. printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
  359. /* 256MiB of RM9000x2 DDR */
  360. // add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
  361. /* 128MiB of MV-64340 DDR */
  362. // add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
  363. /* XXX Memory configuration should be picked up from PMON2k */
  364. #ifdef CONFIG_JAGUAR_DMALOW
  365. printk("Jaguar ATX DMA-low mode set\n");
  366. add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
  367. add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
  368. #else
  369. /* 128MiB of MV-64340 DDR RAM */
  370. printk("Jaguar ATX DMA-low mode is not set\n");
  371. add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
  372. #endif
  373. #ifdef GEMDEBUG_TRACEBUFFER
  374. {
  375. unsigned int tbControl;
  376. tbControl =
  377. 0 << 26 | /* post trigger delay 0 */
  378. 0x2 << 16 | /* sequential trace mode */
  379. // 0x0 << 16 | /* non-sequential trace mode */
  380. // 0xf << 4 | /* watchpoints disabled */
  381. 2 << 2 | /* armed */
  382. 2 ; /* interrupt disabled */
  383. printk ("setting tbControl = %08lx\n", tbControl);
  384. write_32bit_cp0_set1_register($22, tbControl);
  385. __asm__ __volatile__(".set noreorder\n\t" \
  386. "nop; nop; nop; nop; nop; nop;\n\t" \
  387. "nop; nop; nop; nop; nop; nop;\n\t" \
  388. ".set reorder\n\t");
  389. }
  390. #endif
  391. return 0;
  392. }
  393. early_initcall(momenco_jaguar_atx_setup);