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/arch/mips/momentum/jaguar_atx/int-handler.S

https://bitbucket.org/evzijst/gittest
Assembly | 128 lines | 110 code | 18 blank | 0 comment | 2 complexity | c33f5f29b21309ba04bd3ec5f6920b2b MD5 | raw file
  1/*
  2 * Copyright 2002 Momentum Computer Inc.
  3 * Author: Matthew Dharm <mdharm@momenco.com>
  4 *
  5 * Based on work:
  6 *   Copyright 2001 MontaVista Software Inc.
  7 *   Author: jsun@mvista.com or jsun@junsun.net
  8 *
  9 * First-level interrupt dispatcher for Jaguar-ATX board.
 10 *
 11 * This program is free software; you can redistribute  it and/or modify it
 12 * under  the terms of  the GNU General  Public License as published by the
 13 * Free Software Foundation;  either version 2 of the  License, or (at your
 14 * option) any later version.
 15 */
 16#include <asm/asm.h>
 17#include <asm/mipsregs.h>
 18#include <asm/addrspace.h>
 19#include <asm/regdef.h>
 20#include <asm/stackframe.h>
 21
 22/*
 23 * First level interrupt dispatcher for Ocelot-CS board
 24 */
 25		.align	5
 26		NESTED(jaguar_handle_int, PT_SIZE, sp)
 27		SAVE_ALL
 28		CLI
 29		.set	at
 30		mfc0	t0, CP0_CAUSE  
 31		mfc0	t2, CP0_STATUS
 32
 33		and	t0, t2
 34        
 35		andi	t1, t0, STATUSF_IP0	/* sw0 software interrupt */
 36		bnez	t1, ll_sw0_irq
 37		andi	t1, t0, STATUSF_IP1	/* sw1 software interrupt */
 38		bnez	t1, ll_sw1_irq
 39		andi	t1, t0, STATUSF_IP2	/* int0 hardware line */
 40		bnez	t1, ll_pcixa_irq
 41		andi	t1, t0, STATUSF_IP3	/* int1 hardware line */
 42		bnez	t1, ll_pcixb_irq
 43		andi	t1, t0, STATUSF_IP4	/* int2 hardware line */
 44		bnez	t1, ll_pcia_irq
 45		andi	t1, t0, STATUSF_IP5	/* int3 hardware line */
 46		bnez	t1, ll_pcib_irq
 47		andi	t1, t0, STATUSF_IP6	/* int4 hardware line */
 48		bnez	t1, ll_uart_irq
 49		andi	t1, t0, STATUSF_IP7	/* cpu timer */
 50		bnez	t1, ll_cputimer_irq
 51
 52		nop
 53		nop
 54
 55		/* now look at extended interrupts */
 56		mfc0	t0, CP0_CAUSE
 57		cfc0	t1, CP0_S1_INTCONTROL
 58
 59		/* shift the mask 8 bits left to line up the bits */
 60		sll	t2, t1, 8
 61
 62		and	t0, t2
 63		srl	t0, t0, 16
 64
 65		andi	t1, t0, STATUSF_IP8	/* int6 hardware line */
 66		bnez	t1, ll_mv64340_decode_irq
 67
 68		nop
 69		nop
 70
 71		.set	reorder
 72
 73		/* wrong alarm or masked ... */
 74		j	spurious_interrupt
 75		nop
 76		END(jaguar_handle_int)
 77
 78		.align	5
 79ll_sw0_irq:
 80		li	a0, 0
 81		move	a1, sp
 82		jal	do_IRQ
 83		j	ret_from_irq
 84ll_sw1_irq:
 85		li	a0, 1
 86		move	a1, sp
 87		jal	do_IRQ
 88		j	ret_from_irq
 89ll_pcixa_irq:
 90		li	a0, 2
 91		move	a1, sp
 92		jal	do_IRQ
 93		j	ret_from_irq
 94
 95ll_pcixb_irq:
 96		li	a0, 3
 97		move	a1, sp
 98		jal	do_IRQ
 99		j	ret_from_irq
100
101ll_pcia_irq:
102		li	a0, 4
103		move	a1, sp
104		jal	do_IRQ
105		j	ret_from_irq
106	
107ll_pcib_irq:
108		li	a0, 5
109		move	a1, sp
110		jal	do_IRQ
111		j	ret_from_irq
112	
113ll_uart_irq:
114		li	a0, 6
115		move	a1, sp
116		jal	do_IRQ
117		j	ret_from_irq
118	
119ll_cputimer_irq:
120		li	a0, 7
121		move	a1, sp
122		jal	ll_timer_interrupt
123		j	ret_from_irq
124	
125ll_mv64340_decode_irq:
126		move	a0, sp
127		jal	ll_mv64340_irq
128		j	ret_from_irq