/arch/mips/galileo-boards/ev96100/setup.c

https://bitbucket.org/evzijst/gittest · C · 162 lines · 93 code · 28 blank · 41 comment · 6 complexity · 8eab1f3273cdd1dd4a767870a2c38c23 MD5 · raw file

  1. /*
  2. * BRIEF MODULE DESCRIPTION
  3. * Galileo EV96100 setup.
  4. *
  5. * Copyright 2000 MontaVista Software Inc.
  6. * Author: MontaVista Software, Inc.
  7. * ppopov@mvista.com or source@mvista.com
  8. *
  9. * This file was derived from Carsten Langgaard's
  10. * arch/mips/mips-boards/atlas/atlas_setup.c.
  11. *
  12. * Carsten Langgaard, carstenl@mips.com
  13. * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
  14. *
  15. * This program is free software; you can redistribute it and/or modify it
  16. * under the terms of the GNU General Public License as published by the
  17. * Free Software Foundation; either version 2 of the License, or (at your
  18. * option) any later version.
  19. *
  20. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30. *
  31. * You should have received a copy of the GNU General Public License along
  32. * with this program; if not, write to the Free Software Foundation, Inc.,
  33. * 675 Mass Ave, Cambridge, MA 02139, USA.
  34. */
  35. #include <linux/config.h>
  36. #include <linux/init.h>
  37. #include <linux/sched.h>
  38. #include <linux/ioport.h>
  39. #include <linux/string.h>
  40. #include <linux/ctype.h>
  41. #include <linux/pci.h>
  42. #include <asm/cpu.h>
  43. #include <asm/bootinfo.h>
  44. #include <asm/mipsregs.h>
  45. #include <asm/irq.h>
  46. #include <asm/delay.h>
  47. #include <asm/gt64120.h>
  48. #include <asm/galileo-boards/ev96100int.h>
  49. extern char *__init prom_getcmdline(void);
  50. extern void mips_reboot_setup(void);
  51. unsigned char mac_0_1[12];
  52. static void __init ev96100_setup(void)
  53. {
  54. unsigned int config = read_c0_config();
  55. unsigned int status = read_c0_status();
  56. unsigned int info = read_c0_info();
  57. u32 tmp;
  58. char *argptr;
  59. clear_c0_status(ST0_FR);
  60. if (config & 0x8)
  61. printk("Secondary cache is enabled\n");
  62. else
  63. printk("Secondary cache is disabled\n");
  64. if (status & (1 << 27))
  65. printk("User-mode cache ops enabled\n");
  66. else
  67. printk("User-mode cache ops disabled\n");
  68. printk("CP0 info reg: %x\n", (unsigned) info);
  69. if (info & (1 << 28))
  70. printk("burst mode Scache RAMS\n");
  71. else
  72. printk("pipelined Scache RAMS\n");
  73. if (info & 0x1)
  74. printk("Atomic Enable is set\n");
  75. argptr = prom_getcmdline();
  76. #ifdef CONFIG_SERIAL_CONSOLE
  77. if (strstr(argptr, "console=") == NULL) {
  78. argptr = prom_getcmdline();
  79. strcat(argptr, " console=ttyS0,115200");
  80. }
  81. #endif
  82. mips_reboot_setup();
  83. set_io_port_base(KSEG1);
  84. ioport_resource.start = GT_PCI_IO_BASE;
  85. ioport_resource.end = GT_PCI_IO_BASE + 0x01ffffff;
  86. #ifdef CONFIG_BLK_DEV_INITRD
  87. ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
  88. #endif
  89. /*
  90. * Setup GT controller master bit so we can do config cycles
  91. */
  92. /* Clear cause register bits */
  93. GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
  94. GT_INTRCAUSE_TARABORT0_BIT));
  95. /* Setup address */
  96. GT_WRITE(GT_PCI0_CFGADDR_OFS,
  97. (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
  98. (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
  99. ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
  100. GT_PCI0_CFGADDR_CONFIGEN_BIT);
  101. udelay(2);
  102. tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
  103. tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  104. PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
  105. GT_WRITE(GT_PCI0_CFGADDR_OFS,
  106. (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
  107. (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
  108. ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
  109. GT_PCI0_CFGADDR_CONFIGEN_BIT);
  110. udelay(2);
  111. GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
  112. /* Setup address */
  113. GT_WRITE(GT_PCI0_CFGADDR_OFS,
  114. (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
  115. (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
  116. ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
  117. GT_PCI0_CFGADDR_CONFIGEN_BIT);
  118. udelay(2);
  119. tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
  120. }
  121. early_initcall(ev96100_setup);
  122. unsigned short get_gt_devid(void)
  123. {
  124. u32 gt_devid;
  125. /* Figure out if this is a gt96100 or gt96100A */
  126. GT_WRITE(GT_PCI0_CFGADDR_OFS,
  127. (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
  128. (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
  129. ((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
  130. GT_PCI0_CFGADDR_CONFIGEN_BIT);
  131. udelay(4);
  132. gt_devid = GT_READ(GT_PCI0_CFGDATA_OFS);
  133. return gt_devid >> 16;
  134. }