/arch/mips/galileo-boards/ev96100/setup.c

  1/*
  2 * BRIEF MODULE DESCRIPTION
  3 *	Galileo EV96100 setup.
  4 *
  5 * Copyright 2000 MontaVista Software Inc.
  6 * Author: MontaVista Software, Inc.
  7 *         	ppopov@mvista.com or source@mvista.com
  8 *
  9 * This file was derived from Carsten Langgaard's
 10 * arch/mips/mips-boards/atlas/atlas_setup.c.
 11 *
 12 * Carsten Langgaard, carstenl@mips.com
 13 * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
 14 *
 15 *  This program is free software; you can redistribute  it and/or modify it
 16 *  under  the terms of  the GNU General  Public License as published by the
 17 *  Free Software Foundation;  either version 2 of the  License, or (at your
 18 *  option) any later version.
 19 *
 20 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 21 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 22 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 23 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 24 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 25 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 26 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 27 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 28 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 29 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 30 *
 31 *  You should have received a copy of the  GNU General Public License along
 32 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 33 *  675 Mass Ave, Cambridge, MA 02139, USA.
 34 */
 35#include <linux/config.h>
 36#include <linux/init.h>
 37#include <linux/sched.h>
 38#include <linux/ioport.h>
 39#include <linux/string.h>
 40#include <linux/ctype.h>
 41#include <linux/pci.h>
 42
 43#include <asm/cpu.h>
 44#include <asm/bootinfo.h>
 45#include <asm/mipsregs.h>
 46#include <asm/irq.h>
 47#include <asm/delay.h>
 48#include <asm/gt64120.h>
 49#include <asm/galileo-boards/ev96100int.h>
 50
 51
 52extern char *__init prom_getcmdline(void);
 53
 54extern void mips_reboot_setup(void);
 55
 56unsigned char mac_0_1[12];
 57
 58static void __init ev96100_setup(void)
 59{
 60	unsigned int config = read_c0_config();
 61	unsigned int status = read_c0_status();
 62	unsigned int info = read_c0_info();
 63	u32 tmp;
 64
 65	char *argptr;
 66
 67	clear_c0_status(ST0_FR);
 68
 69	if (config & 0x8)
 70		printk("Secondary cache is enabled\n");
 71	else
 72		printk("Secondary cache is disabled\n");
 73
 74	if (status & (1 << 27))
 75		printk("User-mode cache ops enabled\n");
 76	else
 77		printk("User-mode cache ops disabled\n");
 78
 79	printk("CP0 info reg: %x\n", (unsigned) info);
 80	if (info & (1 << 28))
 81		printk("burst mode Scache RAMS\n");
 82	else
 83		printk("pipelined Scache RAMS\n");
 84
 85	if (info & 0x1)
 86		printk("Atomic Enable is set\n");
 87
 88	argptr = prom_getcmdline();
 89#ifdef CONFIG_SERIAL_CONSOLE
 90	if (strstr(argptr, "console=") == NULL) {
 91		argptr = prom_getcmdline();
 92		strcat(argptr, " console=ttyS0,115200");
 93	}
 94#endif
 95
 96	mips_reboot_setup();
 97
 98	set_io_port_base(KSEG1);
 99	ioport_resource.start = GT_PCI_IO_BASE;
100	ioport_resource.end = GT_PCI_IO_BASE + 0x01ffffff;
101
102#ifdef CONFIG_BLK_DEV_INITRD
103	ROOT_DEV = MKDEV(RAMDISK_MAJOR, 0);
104#endif
105
106
107	/*
108	 * Setup GT controller master bit so we can do config cycles
109	 */
110
111	/* Clear cause register bits */
112	GT_WRITE(GT_INTRCAUSE_OFS, ~(GT_INTRCAUSE_MASABORT0_BIT |
113				     GT_INTRCAUSE_TARABORT0_BIT));
114	/* Setup address */
115	GT_WRITE(GT_PCI0_CFGADDR_OFS,
116		 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
117		 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
118		 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
119		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
120
121	udelay(2);
122	tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
123
124	tmp |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
125		PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
126	GT_WRITE(GT_PCI0_CFGADDR_OFS,
127		 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
128		 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
129		 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
130		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
131	udelay(2);
132	GT_WRITE(GT_PCI0_CFGDATA_OFS, tmp);
133
134	/* Setup address */
135	GT_WRITE(GT_PCI0_CFGADDR_OFS,
136		 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
137		 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
138		 ((PCI_COMMAND / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
139		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
140
141	udelay(2);
142	tmp = GT_READ(GT_PCI0_CFGDATA_OFS);
143}
144
145early_initcall(ev96100_setup);
146
147unsigned short get_gt_devid(void)
148{
149	u32 gt_devid;
150
151	/* Figure out if this is a gt96100 or gt96100A */
152	GT_WRITE(GT_PCI0_CFGADDR_OFS,
153		 (0 << GT_PCI0_CFGADDR_BUSNUM_SHF) |
154		 (0 << GT_PCI0_CFGADDR_FUNCTNUM_SHF) |
155		 ((PCI_VENDOR_ID / 4) << GT_PCI0_CFGADDR_REGNUM_SHF) |
156		 GT_PCI0_CFGADDR_CONFIGEN_BIT);
157
158	udelay(4);
159	gt_devid = GT_READ(GT_PCI0_CFGDATA_OFS);
160
161	return gt_devid >> 16;
162}