/arch/mips/ddb5xxx/ddb5476/nile4_pic.c

https://bitbucket.org/evzijst/gittest · C · 190 lines · 144 code · 28 blank · 18 comment · 5 complexity · 92bf6f6e2e6374799444630c9109be84 MD5 · raw file

  1. /*
  2. * arch/mips/ddb5476/nile4.c --
  3. * low-level PIC code for NEC Vrc-5476 (Nile 4)
  4. *
  5. * Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
  6. * Sony Software Development Center Europe (SDCE), Brussels
  7. *
  8. * Copyright 2001 MontaVista Software Inc.
  9. * Author: jsun@mvista.com or jsun@junsun.net
  10. *
  11. */
  12. #include <linux/config.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <asm/addrspace.h>
  16. #include <asm/ddb5xxx/ddb5xxx.h>
  17. /*
  18. * Interrupt Programming
  19. */
  20. void nile4_map_irq(int nile4_irq, int cpu_irq)
  21. {
  22. u32 offset, t;
  23. offset = DDB_INTCTRL;
  24. if (nile4_irq >= 8) {
  25. offset += 4;
  26. nile4_irq -= 8;
  27. }
  28. t = ddb_in32(offset);
  29. t &= ~(7 << (nile4_irq * 4));
  30. t |= cpu_irq << (nile4_irq * 4);
  31. ddb_out32(offset, t);
  32. }
  33. void nile4_map_irq_all(int cpu_irq)
  34. {
  35. u32 all, t;
  36. all = cpu_irq;
  37. all |= all << 4;
  38. all |= all << 8;
  39. all |= all << 16;
  40. t = ddb_in32(DDB_INTCTRL);
  41. t &= 0x88888888;
  42. t |= all;
  43. ddb_out32(DDB_INTCTRL, t);
  44. t = ddb_in32(DDB_INTCTRL + 4);
  45. t &= 0x88888888;
  46. t |= all;
  47. ddb_out32(DDB_INTCTRL + 4, t);
  48. }
  49. void nile4_enable_irq(int nile4_irq)
  50. {
  51. u32 offset, t;
  52. offset = DDB_INTCTRL;
  53. if (nile4_irq >= 8) {
  54. offset += 4;
  55. nile4_irq -= 8;
  56. }
  57. t = ddb_in32(offset);
  58. t |= 8 << (nile4_irq * 4);
  59. ddb_out32(offset, t);
  60. }
  61. void nile4_disable_irq(int nile4_irq)
  62. {
  63. u32 offset, t;
  64. offset = DDB_INTCTRL;
  65. if (nile4_irq >= 8) {
  66. offset += 4;
  67. nile4_irq -= 8;
  68. }
  69. t = ddb_in32(offset);
  70. t &= ~(8 << (nile4_irq * 4));
  71. ddb_out32(offset, t);
  72. }
  73. void nile4_disable_irq_all(void)
  74. {
  75. ddb_out32(DDB_INTCTRL, 0);
  76. ddb_out32(DDB_INTCTRL + 4, 0);
  77. }
  78. u16 nile4_get_irq_stat(int cpu_irq)
  79. {
  80. return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
  81. }
  82. void nile4_enable_irq_output(int cpu_irq)
  83. {
  84. u32 t;
  85. t = ddb_in32(DDB_INTSTAT1 + 4);
  86. t |= 1 << (16 + cpu_irq);
  87. ddb_out32(DDB_INTSTAT1, t);
  88. }
  89. void nile4_disable_irq_output(int cpu_irq)
  90. {
  91. u32 t;
  92. t = ddb_in32(DDB_INTSTAT1 + 4);
  93. t &= ~(1 << (16 + cpu_irq));
  94. ddb_out32(DDB_INTSTAT1, t);
  95. }
  96. void nile4_set_pci_irq_polarity(int pci_irq, int high)
  97. {
  98. u32 t;
  99. t = ddb_in32(DDB_INTPPES);
  100. if (high)
  101. t &= ~(1 << (pci_irq * 2));
  102. else
  103. t |= 1 << (pci_irq * 2);
  104. ddb_out32(DDB_INTPPES, t);
  105. }
  106. void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
  107. {
  108. u32 t;
  109. t = ddb_in32(DDB_INTPPES);
  110. if (level)
  111. t |= 2 << (pci_irq * 2);
  112. else
  113. t &= ~(2 << (pci_irq * 2));
  114. ddb_out32(DDB_INTPPES, t);
  115. }
  116. void nile4_clear_irq(int nile4_irq)
  117. {
  118. ddb_out32(DDB_INTCLR, 1 << nile4_irq);
  119. }
  120. void nile4_clear_irq_mask(u32 mask)
  121. {
  122. ddb_out32(DDB_INTCLR, mask);
  123. }
  124. u8 nile4_i8259_iack(void)
  125. {
  126. u8 irq;
  127. u32 reg;
  128. /* Set window 0 for interrupt acknowledge */
  129. reg = ddb_in32(DDB_PCIINIT0);
  130. ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
  131. irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
  132. /* restore window 0 for PCI I/O space */
  133. // ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
  134. ddb_out32(DDB_PCIINIT0, reg);
  135. /* i8269.c set the base vector to be 0x0 */
  136. return irq + I8259_IRQ_BASE;
  137. }
  138. #if defined(CONFIG_RUNTIME_DEBUG)
  139. void nile4_dump_irq_status(void)
  140. {
  141. printk(KERN_DEBUG "
  142. CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
  143. (void *) ddb_in32(DDB_CPUSTAT));
  144. printk(KERN_DEBUG "
  145. INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
  146. (void *) ddb_in32(DDB_INTCTRL));
  147. printk(KERN_DEBUG
  148. "INTSTAT0 = %p:%p\n",
  149. (void *) ddb_in32(DDB_INTSTAT0 + 4),
  150. (void *) ddb_in32(DDB_INTSTAT0));
  151. printk(KERN_DEBUG
  152. "INTSTAT1 = %p:%p\n",
  153. (void *) ddb_in32(DDB_INTSTAT1 + 4),
  154. (void *) ddb_in32(DDB_INTSTAT1));
  155. printk(KERN_DEBUG
  156. "INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
  157. (void *) ddb_in32(DDB_INTCLR));
  158. printk(KERN_DEBUG
  159. "INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
  160. (void *) ddb_in32(DDB_INTPPES));
  161. }
  162. #endif