PageRenderTime 23ms CodeModel.GetById 15ms app.highlight 5ms RepoModel.GetById 1ms app.codeStats 0ms

/arch/mips/ddb5xxx/ddb5476/int-handler.S

https://bitbucket.org/evzijst/gittest
Assembly | 112 lines | 96 code | 16 blank | 0 comment | 4 complexity | 61d44d84a190f9d519268b8e63ef2414 MD5 | raw file
  1/*
  2 * Copyright 2001 MontaVista Software Inc.
  3 * Author: jsun@mvista.com or jsun@junsun.net
  4 *
  5 * First-level interrupt dispatcher for ddb5476
  6 *
  7 * This program is free software; you can redistribute  it and/or modify it
  8 * under  the terms of  the GNU General  Public License as published by the
  9 * Free Software Foundation;  either version 2 of the  License, or (at your
 10 * option) any later version.
 11 */
 12#include <asm/asm.h>
 13#include <asm/mipsregs.h>
 14#include <asm/addrspace.h>
 15#include <asm/regdef.h>
 16#include <asm/stackframe.h>
 17
 18#include <asm/ddb5xxx/ddb5476.h>
 19
 20/*
 21 * first level interrupt dispatcher for ocelot board -
 22 * We check for the timer first, then check PCI ints A and D.
 23 * Then check for serial IRQ and fall through.
 24 */
 25	.align	5
 26	NESTED(ddb5476_handle_int, PT_SIZE, sp)
 27	SAVE_ALL
 28	CLI
 29	.set	at
 30	.set	noreorder
 31	mfc0	t0, CP0_CAUSE
 32	mfc0	t2, CP0_STATUS
 33
 34	and	t0, t2
 35
 36        andi    t1, t0, STATUSF_IP7     /* cpu timer */
 37        bnez    t1, ll_cpu_ip7
 38        andi    t1, t0, STATUSF_IP2	/* vrc5476 & i8259 */
 39        bnez    t1, ll_cpu_ip2
 40        andi    t1, t0, STATUSF_IP3
 41        bnez    t1, ll_cpu_ip3
 42        andi    t1, t0, STATUSF_IP4
 43        bnez    t1, ll_cpu_ip4
 44        andi    t1, t0, STATUSF_IP5
 45        bnez    t1, ll_cpu_ip5
 46        andi    t1, t0, STATUSF_IP6
 47        bnez    t1, ll_cpu_ip6
 48        andi    t1, t0, STATUSF_IP0     /* software int 0 */
 49        bnez    t1, ll_cpu_ip0
 50        andi    t1, t0, STATUSF_IP1     /* software int 1 */
 51        bnez    t1, ll_cpu_ip1
 52        nop
 53
 54	.set	reorder
 55
 56	/* wrong alarm or masked ... */
 57	// j	spurious_interrupt
 58	move 	a0, sp
 59	jal	vrc5476_irq_dispatch
 60	j	ret_from_irq
 61	nop
 62
 63	.align	5
 64
 65ll_cpu_ip0:
 66	li	a0, CPU_IRQ_BASE + 0
 67	move	a1, sp
 68	jal	do_IRQ
 69	j	ret_from_irq
 70
 71ll_cpu_ip1:
 72	li	a0, CPU_IRQ_BASE + 1
 73	move	a1, sp
 74	jal	do_IRQ
 75	j	ret_from_irq
 76
 77ll_cpu_ip2:		/* jump to second-level dispatching */
 78	move	a0, sp
 79	jal	vrc5476_irq_dispatch
 80	j	ret_from_irq
 81
 82ll_cpu_ip3:
 83	li	a0, CPU_IRQ_BASE + 3
 84	move	a1, sp
 85	jal	do_IRQ
 86	j	ret_from_irq
 87
 88ll_cpu_ip4:
 89	li	a0, CPU_IRQ_BASE + 4
 90	move	a1, sp
 91	jal	do_IRQ
 92	j	ret_from_irq
 93
 94ll_cpu_ip5:
 95	li	a0, CPU_IRQ_BASE + 5
 96	move	a1, sp
 97	jal	do_IRQ
 98	j	ret_from_irq
 99
100ll_cpu_ip6:
101	li	a0, CPU_IRQ_BASE + 6
102	move	a1, sp
103	jal	do_IRQ
104	j	ret_from_irq
105
106ll_cpu_ip7:
107	li	a0, CPU_IRQ_BASE + 7
108	move	a1, sp
109	jal	do_IRQ
110	j	ret_from_irq
111
112	END(ddb5476_handle_int)