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/arch/ia64/sn/include/pci/pcibr_provider.h

https://bitbucket.org/evzijst/gittest
C Header | 149 lines | 93 code | 25 blank | 31 comment | 6 complexity | 9ed90821adb12f86f8a9106ef360c779 MD5 | raw file
  1/*
  2 * This file is subject to the terms and conditions of the GNU General Public
  3 * License.  See the file "COPYING" in the main directory of this archive
  4 * for more details.
  5 *
  6 * Copyright (C) 1992-1997,2000-2004 Silicon Graphics, Inc. All rights reserved.
  7 */
  8#ifndef _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
  9#define _ASM_IA64_SN_PCI_PCIBR_PROVIDER_H
 10
 11/* Workarounds */
 12#define PV907516 (1 << 1) /* TIOCP: Don't write the write buffer flush reg */
 13
 14#define BUSTYPE_MASK                    0x1
 15
 16/* Macros given a pcibus structure */
 17#define IS_PCIX(ps)     ((ps)->pbi_bridge_mode & BUSTYPE_MASK)
 18#define IS_PCI_BRIDGE_ASIC(asic) (asic == PCIIO_ASIC_TYPE_PIC || \
 19                asic == PCIIO_ASIC_TYPE_TIOCP)
 20#define IS_PIC_SOFT(ps)     (ps->pbi_bridge_type == PCIBR_BRIDGETYPE_PIC)
 21
 22
 23/* 
 24 * The different PCI Bridge types supported on the SGI Altix platforms
 25 */
 26#define PCIBR_BRIDGETYPE_UNKNOWN       -1
 27#define PCIBR_BRIDGETYPE_PIC            2
 28#define PCIBR_BRIDGETYPE_TIOCP          3
 29
 30/*
 31 * Bridge 64bit Direct Map Attributes
 32 */
 33#define PCI64_ATTR_PREF                 (1ull << 59)
 34#define PCI64_ATTR_PREC                 (1ull << 58)
 35#define PCI64_ATTR_VIRTUAL              (1ull << 57)
 36#define PCI64_ATTR_BAR                  (1ull << 56)
 37#define PCI64_ATTR_SWAP                 (1ull << 55)
 38#define PCI64_ATTR_VIRTUAL1             (1ull << 54)
 39
 40#define PCI32_LOCAL_BASE                0
 41#define PCI32_MAPPED_BASE               0x40000000
 42#define PCI32_DIRECT_BASE               0x80000000
 43
 44#define IS_PCI32_MAPPED(x)              ((uint64_t)(x) < PCI32_DIRECT_BASE && \
 45                                         (uint64_t)(x) >= PCI32_MAPPED_BASE)
 46#define IS_PCI32_DIRECT(x)              ((uint64_t)(x) >= PCI32_MAPPED_BASE)
 47
 48
 49/*
 50 * Bridge PMU Address Transaltion Entry Attibutes
 51 */
 52#define PCI32_ATE_V                     (0x1 << 0)
 53#define PCI32_ATE_CO                    (0x1 << 1)
 54#define PCI32_ATE_PREC                  (0x1 << 2)
 55#define PCI32_ATE_PREF                  (0x1 << 3)
 56#define PCI32_ATE_BAR                   (0x1 << 4)
 57#define PCI32_ATE_ADDR_SHFT             12
 58
 59#define MINIMAL_ATES_REQUIRED(addr, size) \
 60	(IOPG(IOPGOFF(addr) + (size) - 1) == IOPG((size) - 1))
 61
 62#define MINIMAL_ATE_FLAG(addr, size) \
 63	(MINIMAL_ATES_REQUIRED((uint64_t)addr, size) ? 1 : 0)
 64
 65/* bit 29 of the pci address is the SWAP bit */
 66#define ATE_SWAPSHIFT                   29
 67#define ATE_SWAP_ON(x)                  ((x) |= (1 << ATE_SWAPSHIFT))
 68#define ATE_SWAP_OFF(x)                 ((x) &= ~(1 << ATE_SWAPSHIFT))
 69
 70/*
 71 * I/O page size
 72 */
 73#if PAGE_SIZE < 16384
 74#define IOPFNSHIFT                      12      /* 4K per mapped page */
 75#else
 76#define IOPFNSHIFT                      14      /* 16K per mapped page */
 77#endif
 78
 79#define IOPGSIZE                        (1 << IOPFNSHIFT)
 80#define IOPG(x)                         ((x) >> IOPFNSHIFT)
 81#define IOPGOFF(x)                      ((x) & (IOPGSIZE-1))
 82
 83#define PCIBR_DEV_SWAP_DIR              (1ull << 19)
 84#define PCIBR_CTRL_PAGE_SIZE            (0x1 << 21)
 85
 86/*
 87 * PMU resources.
 88 */
 89struct ate_resource{
 90	uint64_t *ate;
 91	uint64_t num_ate;
 92	uint64_t lowest_free_index;
 93};
 94
 95struct pcibus_info {
 96	struct pcibus_bussoft	pbi_buscommon;   /* common header */
 97	uint32_t                pbi_moduleid;
 98	short                   pbi_bridge_type;
 99	short                   pbi_bridge_mode;
100
101	struct ate_resource     pbi_int_ate_resource;
102	uint64_t                pbi_int_ate_size;
103	
104	uint64_t                pbi_dir_xbase;
105	char                    pbi_hub_xid;
106
107	uint64_t                pbi_devreg[8];
108	spinlock_t              pbi_lock;
109
110	uint32_t		pbi_valid_devices;
111	uint32_t		pbi_enabled_devices;
112};
113
114/*
115 * pcibus_info structure locking macros
116 */
117inline static unsigned long
118pcibr_lock(struct pcibus_info *pcibus_info)
119{
120	unsigned long flag;
121	spin_lock_irqsave(&pcibus_info->pbi_lock, flag);
122	return(flag);
123}
124#define pcibr_unlock(pcibus_info, flag)  spin_unlock_irqrestore(&pcibus_info->pbi_lock, flag)
125
126extern void *pcibr_bus_fixup(struct pcibus_bussoft *);
127extern uint64_t pcibr_dma_map(struct pcidev_info *, unsigned long, size_t, unsigned int);
128extern void pcibr_dma_unmap(struct pcidev_info *, dma_addr_t, int);
129
130/*
131 * prototypes for the bridge asic register access routines in pcibr_reg.c
132 */
133extern void             pcireg_control_bit_clr(struct pcibus_info *, uint64_t);
134extern void             pcireg_control_bit_set(struct pcibus_info *, uint64_t);
135extern uint64_t         pcireg_tflush_get(struct pcibus_info *);
136extern uint64_t         pcireg_intr_status_get(struct pcibus_info *);
137extern void             pcireg_intr_enable_bit_clr(struct pcibus_info *, uint64_t);
138extern void             pcireg_intr_enable_bit_set(struct pcibus_info *, uint64_t);
139extern void             pcireg_intr_addr_addr_set(struct pcibus_info *, int, uint64_t);
140extern void             pcireg_force_intr_set(struct pcibus_info *, int);
141extern uint64_t         pcireg_wrb_flush_get(struct pcibus_info *, int);
142extern void             pcireg_int_ate_set(struct pcibus_info *, int, uint64_t);
143extern uint64_t *	pcireg_int_ate_addr(struct pcibus_info *, int);
144extern void 		pcibr_force_interrupt(struct sn_irq_info *sn_irq_info);
145extern void 		pcibr_change_devices_irq(struct sn_irq_info *sn_irq_info);
146extern int 		pcibr_ate_alloc(struct pcibus_info *, int);
147extern void 		pcibr_ate_free(struct pcibus_info *, int);
148extern void 		ate_write(struct pcibus_info *, int, int, uint64_t);
149#endif