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/arch/ia64/kernel/perfmon_mckinley.h

https://bitbucket.org/evzijst/gittest
C Header | 187 lines | 114 code | 26 blank | 47 comment | 40 complexity | af226af6a9f53b97d55cca8b9d552a45 MD5 | raw file
  1/*
  2 * This file contains the McKinley PMU register description tables
  3 * and pmc checker used by perfmon.c.
  4 *
  5 * Copyright (C) 2002-2003  Hewlett Packard Co
  6 *               Stephane Eranian <eranian@hpl.hp.com>
  7 */
  8static int pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
  9
 10static pfm_reg_desc_t pfm_mck_pmc_desc[PMU_MAX_PMCS]={
 11/* pmc0  */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 12/* pmc1  */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 13/* pmc2  */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 14/* pmc3  */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 15/* pmc4  */ { PFM_REG_COUNTING, 6, 0x0000000000800000UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 16/* pmc5  */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL,  pfm_mck_pmc_check, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 17/* pmc6  */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL,  pfm_mck_pmc_check, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 18/* pmc7  */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL,  pfm_mck_pmc_check, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 19/* pmc8  */ { PFM_REG_CONFIG  , 0, 0xffffffff3fffffffUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 20/* pmc9  */ { PFM_REG_CONFIG  , 0, 0xffffffff3ffffffcUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 21/* pmc10 */ { PFM_REG_MONITOR , 4, 0x0UL, 0xffffUL, NULL, pfm_mck_pmc_check, {RDEP(0)|RDEP(1),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 22/* pmc11 */ { PFM_REG_MONITOR , 6, 0x0UL, 0x30f01cf, NULL,  pfm_mck_pmc_check, {RDEP(2)|RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 23/* pmc12 */ { PFM_REG_MONITOR , 6, 0x0UL, 0xffffUL, NULL,  pfm_mck_pmc_check, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 24/* pmc13 */ { PFM_REG_CONFIG  , 0, 0x00002078fefefefeUL, 0x1e00018181818UL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 25/* pmc14 */ { PFM_REG_CONFIG  , 0, 0x0db60db60db60db6UL, 0x2492UL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 26/* pmc15 */ { PFM_REG_CONFIG  , 0, 0x00000000fffffff0UL, 0xfUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
 27	    { PFM_REG_END     , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
 28};
 29
 30static pfm_reg_desc_t pfm_mck_pmd_desc[PMU_MAX_PMDS]={
 31/* pmd0  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(1),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
 32/* pmd1  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(0),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
 33/* pmd2  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
 34/* pmd3  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
 35/* pmd4  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(4),0UL, 0UL, 0UL}},
 36/* pmd5  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(5),0UL, 0UL, 0UL}},
 37/* pmd6  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(6),0UL, 0UL, 0UL}},
 38/* pmd7  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(7),0UL, 0UL, 0UL}},
 39/* pmd8  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
 40/* pmd9  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
 41/* pmd10 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
 42/* pmd11 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
 43/* pmd12 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
 44/* pmd13 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
 45/* pmd14 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
 46/* pmd15 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
 47/* pmd16 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
 48/* pmd17 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(3),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
 49	    { PFM_REG_END     , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
 50};
 51
 52/*
 53 * PMC reserved fields must have their power-up values preserved
 54 */
 55static int
 56pfm_mck_reserved(unsigned int cnum, unsigned long *val, struct pt_regs *regs)
 57{
 58	unsigned long tmp1, tmp2, ival = *val;
 59
 60	/* remove reserved areas from user value */
 61	tmp1 = ival & PMC_RSVD_MASK(cnum);
 62
 63	/* get reserved fields values */
 64	tmp2 = PMC_DFL_VAL(cnum) & ~PMC_RSVD_MASK(cnum);
 65
 66	*val = tmp1 | tmp2;
 67
 68	DPRINT(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n",
 69		  cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val));
 70	return 0;
 71}
 72
 73/*
 74 * task can be NULL if the context is unloaded
 75 */
 76static int
 77pfm_mck_pmc_check(struct task_struct *task, pfm_context_t *ctx, unsigned int cnum, unsigned long *val, struct pt_regs *regs)
 78{
 79	int ret = 0, check_case1 = 0;
 80	unsigned long val8 = 0, val14 = 0, val13 = 0;
 81	int is_loaded;
 82
 83	/* first preserve the reserved fields */
 84	pfm_mck_reserved(cnum, val, regs);
 85
 86	/* sanitfy check */
 87	if (ctx == NULL) return -EINVAL;
 88
 89	is_loaded = ctx->ctx_state == PFM_CTX_LOADED || ctx->ctx_state == PFM_CTX_MASKED;
 90
 91	/*
 92	 * we must clear the debug registers if pmc13 has a value which enable
 93	 * memory pipeline event constraints. In this case we need to clear the
 94	 * the debug registers if they have not yet been accessed. This is required
 95	 * to avoid picking stale state.
 96	 * PMC13 is "active" if:
 97	 * 	one of the pmc13.cfg_dbrpXX field is different from 0x3
 98	 * AND
 99	 * 	at the corresponding pmc13.ena_dbrpXX is set.
100	 */
101	DPRINT(("cnum=%u val=0x%lx, using_dbreg=%d loaded=%d\n", cnum, *val, ctx->ctx_fl_using_dbreg, is_loaded));
102
103	if (cnum == 13 && is_loaded
104	    && (*val & 0x1e00000000000UL) && (*val & 0x18181818UL) != 0x18181818UL && ctx->ctx_fl_using_dbreg == 0) {
105
106		DPRINT(("pmc[%d]=0x%lx has active pmc13 settings, clearing dbr\n", cnum, *val));
107
108		/* don't mix debug with perfmon */
109		if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
110
111		/*
112		 * a count of 0 will mark the debug registers as in use and also
113		 * ensure that they are properly cleared.
114		 */
115		ret = pfm_write_ibr_dbr(PFM_DATA_RR, ctx, NULL, 0, regs);
116		if (ret) return ret;
117	}
118	/*
119	 * we must clear the (instruction) debug registers if any pmc14.ibrpX bit is enabled
120	 * before they are (fl_using_dbreg==0) to avoid picking up stale information.
121	 */
122	if (cnum == 14 && is_loaded && ((*val & 0x2222UL) != 0x2222UL) && ctx->ctx_fl_using_dbreg == 0) {
123
124		DPRINT(("pmc[%d]=0x%lx has active pmc14 settings, clearing ibr\n", cnum, *val));
125
126		/* don't mix debug with perfmon */
127		if (task && (task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
128
129		/*
130		 * a count of 0 will mark the debug registers as in use and also
131		 * ensure that they are properly cleared.
132		 */
133		ret = pfm_write_ibr_dbr(PFM_CODE_RR, ctx, NULL, 0, regs);
134		if (ret) return ret;
135
136	}
137
138	switch(cnum) {
139		case  4: *val |= 1UL << 23; /* force power enable bit */
140			 break;
141		case  8: val8 = *val;
142			 val13 = ctx->ctx_pmcs[13];
143			 val14 = ctx->ctx_pmcs[14];
144			 check_case1 = 1;
145			 break;
146		case 13: val8  = ctx->ctx_pmcs[8];
147			 val13 = *val;
148			 val14 = ctx->ctx_pmcs[14];
149			 check_case1 = 1;
150			 break;
151		case 14: val8  = ctx->ctx_pmcs[8];
152			 val13 = ctx->ctx_pmcs[13];
153			 val14 = *val;
154			 check_case1 = 1;
155			 break;
156	}
157	/* check illegal configuration which can produce inconsistencies in tagging
158	 * i-side events in L1D and L2 caches
159	 */
160	if (check_case1) {
161		ret =   ((val13 >> 45) & 0xf) == 0
162		   && ((val8 & 0x1) == 0)
163		   && ((((val14>>1) & 0x3) == 0x2 || ((val14>>1) & 0x3) == 0x0)
164		       ||(((val14>>4) & 0x3) == 0x2 || ((val14>>4) & 0x3) == 0x0));
165
166		if (ret) DPRINT((KERN_DEBUG "perfmon: failure check_case1\n"));
167	}
168
169	return ret ? -EINVAL : 0;
170}
171
172/*
173 * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
174 */
175static pmu_config_t pmu_conf_mck={
176	.pmu_name      = "Itanium 2",
177	.pmu_family    = 0x1f,
178	.flags	       = PFM_PMU_IRQ_RESEND,
179	.ovfl_val      = (1UL << 47) - 1,
180	.pmd_desc      = pfm_mck_pmd_desc,
181	.pmc_desc      = pfm_mck_pmc_desc,
182	.num_ibrs       = 8,
183	.num_dbrs       = 8,
184	.use_rr_dbregs = 1 /* debug register are use for range retrictions */
185};
186
187