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/arch/i386/kernel/cpu/mcheck/k7.c

https://bitbucket.org/evzijst/gittest
C | 97 lines | 73 code | 14 blank | 10 comment | 11 complexity | 9314b11794ae2ea092803c749ad1ffd2 MD5 | raw file
 1/*
 2 * Athlon/Hammer specific Machine Check Exception Reporting
 3 * (C) Copyright 2002 Dave Jones <davej@codemonkey.org.uk>
 4 */
 5
 6#include <linux/init.h>
 7#include <linux/types.h>
 8#include <linux/kernel.h>
 9#include <linux/config.h>
10#include <linux/irq.h>
11#include <linux/interrupt.h>
12#include <linux/smp.h>
13
14#include <asm/processor.h> 
15#include <asm/system.h>
16#include <asm/msr.h>
17
18#include "mce.h"
19
20/* Machine Check Handler For AMD Athlon/Duron */
21static fastcall void k7_machine_check(struct pt_regs * regs, long error_code)
22{
23	int recover=1;
24	u32 alow, ahigh, high, low;
25	u32 mcgstl, mcgsth;
26	int i;
27
28	rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
29	if (mcgstl & (1<<0))	/* Recoverable ? */
30		recover=0;
31
32	printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
33		smp_processor_id(), mcgsth, mcgstl);
34
35	for (i=1; i<nr_mce_banks; i++) {
36		rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
37		if (high&(1<<31)) {
38			if (high & (1<<29))
39				recover |= 1;
40			if (high & (1<<25))
41				recover |= 2;
42			printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
43			high &= ~(1<<31);
44			if (high & (1<<27)) {
45				rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
46				printk ("[%08x%08x]", ahigh, alow);
47			}
48			if (high & (1<<26)) {
49				rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
50				printk (" at %08x%08x", ahigh, alow);
51			}
52			printk ("\n");
53			/* Clear it */
54			wrmsr (MSR_IA32_MC0_STATUS+i*4, 0UL, 0UL);
55			/* Serialize */
56			wmb();
57			add_taint(TAINT_MACHINE_CHECK);
58		}
59	}
60
61	if (recover&2)
62		panic ("CPU context corrupt");
63	if (recover&1)
64		panic ("Unable to continue");
65	printk (KERN_EMERG "Attempting to continue.\n");
66	mcgstl &= ~(1<<2);
67	wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
68}
69
70
71/* AMD K7 machine check is Intel like */
72void __init amd_mcheck_init(struct cpuinfo_x86 *c)
73{
74	u32 l, h;
75	int i;
76
77	machine_check_vector = k7_machine_check;
78	wmb();
79
80	printk (KERN_INFO "Intel machine check architecture supported.\n");
81	rdmsr (MSR_IA32_MCG_CAP, l, h);
82	if (l & (1<<8))	/* Control register present ? */
83		wrmsr (MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
84	nr_mce_banks = l & 0xff;
85
86	/* Clear status for MC index 0 separately, we don't touch CTL,
87	 * as some Athlons cause spurious MCEs when its enabled. */
88	wrmsr (MSR_IA32_MC0_STATUS, 0x0, 0x0);
89	for (i=1; i<nr_mce_banks; i++) {
90		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
91		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
92	}
93
94	set_in_cr4 (X86_CR4_MCE);
95	printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
96		smp_processor_id());
97}