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/arch/h8300/platform/h8s/generic/crt0_rom.S

https://bitbucket.org/evzijst/gittest
Assembly | 129 lines | 97 code | 16 blank | 16 comment | 0 complexity | 377c4b2194f3872bbf3e5388aab6b494 MD5 | raw file
  1/*
  2 *  linux/arch/h8300/platform/h8s/generic/crt0_rom.S
  3 *
  4 *  Yoshinori Sato <ysato@users.sourceforge.jp>
  5 *
  6 *  Platform depend startup 
  7 *  Target Archtecture:	generic
  8 *  Memory Layout     :	ROM
  9 */
 10
 11#define ASSEMBLY
 12
 13#include <linux/config.h>
 14#include <asm/linkage.h>
 15#include <asm/regs267x.h>
 16	
 17	.global SYMBOL_NAME(_start)
 18	.global SYMBOL_NAME(_command_line)
 19	.global SYMBOL_NAME(_platform_gpio_table)
 20	.global SYMBOL_NAME(_target_name)
 21	
 22	.h8300s
 23	.section .text
 24	.file	"crt0_rom.S"
 25
 26	/* CPU Reset entry */
 27SYMBOL_NAME_LABEL(_start)
 28	mov.l	#__ramend,sp
 29	ldc	#0x80,ccr
 30	ldc	#0,exr
 31	bclr	#4,@INTCR:8
 32	bset	#5,@INTCR:8	/* Interrupt mode 2 */
 33	
 34	/* Peripheral Setup */
 35	
 36	/* copy .data */
 37#if !defined(CONFIG_H8S_SIM)
 38	mov.l	#__begin_data,er5
 39	mov.l	#__sdata,er6
 40	mov.l	#__edata,er4
 41	sub.l	er6,er4
 42	shlr.l	#2,er4
 431:	
 44	mov.l	@er5+,er0
 45	mov.l	er0,@er6
 46	adds	#4,er6
 47	dec.l	#1,er4
 48	bne	1b	
 49#endif
 50
 51	/* .bss clear */
 52	mov.l	#__sbss,er5
 53	mov.l	#__ebss,er4
 54	sub.l	er5,er4
 55	shlr.l	#2,er4		
 56	sub.l	er0,er0
 571:
 58	mov.l	er0,@er5
 59	adds	#4,er5
 60	dec.l	#1,er4
 61	bne	1b
 62
 63	/* linux kernel start */
 64	ldc	#0x90,ccr	/* running kernel */
 65	mov.l	#SYMBOL_NAME(init_thread_union),sp
 66	add.l	#0x2000,sp
 67	jsr	@_start_kernel
 68_exit:
 69
 70	jmp	_exit
 71
 72	rts
 73
 74	/* I/O port assign information */
 75__platform_gpio_table:	
 76	mov.l	#gpio_table,er0
 77	rts
 78
 79gpio_table:
 80	;; P1DDR
 81	.byte	0x00,0x00
 82	;; P2DDR
 83	.byte	0x00,0x00
 84	;; P3DDR
 85	.byte	0x00,0x00
 86	;; P4DDR
 87	.byte	0x00,0x00
 88	;; P5DDR
 89	.byte	0x00,0x00
 90	;; P6DDR
 91	.byte	0x00,0x00
 92	;; dummy
 93	.byte	0x00,0x00
 94	;; P8DDR
 95	.byte	0x00,0x00
 96	;; PADDR
 97	.byte	0x00,0x00
 98	;; PBDDR
 99	.byte	0x00,0x00
100	;; PCDDR
101	.byte	0x00,0x00
102	;; PDDDR
103	.byte	0x00,0x00
104	;; PEDDR
105	.byte	0x00,0x00
106	;; PFDDR
107	.byte	0x00,0x00
108	;; PGDDR
109	.byte	0x00,0x00
110	;; PHDDR
111	.byte	0x00,0x00
112
113	.section .rodata
114__target_name:	
115	.asciz	"generic"
116	
117	.section .bss
118__command_line:	
119	.space	512
120
121	/* interrupt vector */
122	.section .vectors,"ax"
123	.long	__start
124	.long	__start
125vector	=	2
126	.rept	126-1
127	.long	_interrupt_redirect_table+vector*4
128vector	=	vector + 1
129	.endr