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/arch/h8300/platform/h8s/edosk2674/crt0_rom.S

https://bitbucket.org/evzijst/gittest
Assembly | 187 lines | 145 code | 22 blank | 20 comment | 0 complexity | f2e5e775a4fde0f61c79ce3ae0f0099d MD5 | raw file
  1/*
  2 *  linux/arch/h8300/platform/h8s/edosk2674/crt0_rom.S
  3 *
  4 *  Yoshinori Sato <ysato@users.sourceforge.jp>
  5 *
  6 *  Platform depend startup
  7 *  Target Archtecture:	EDOSK-2674
  8 *  Memory Layout     :	ROM
  9 */
 10
 11#define ASSEMBLY
 12
 13#include <linux/config.h>
 14#include <asm/linkage.h>
 15#include <asm/regs267x.h>
 16		
 17	.global SYMBOL_NAME(_start)
 18	.global SYMBOL_NAME(_command_line)
 19	.global SYMBOL_NAME(_platform_gpio_table)
 20	.global SYMBOL_NAME(_target_name)
 21	
 22	.h8300s
 23	.section .text
 24	.file	"crt0_rom.S"
 25
 26	/* CPU Reset entry */
 27SYMBOL_NAME_LABEL(_start)
 28	mov.l	#__ramend,sp
 29	ldc	#0x80,ccr
 30	ldc	#0,exr
 31	
 32	/* Peripheral Setup */
 33;BSC/GPIO setup
 34	mov.l	#init_regs,er0
 35	mov.w	#0xffff,e2
 361:
 37	mov.w	@er0+,r2
 38	beq	2f
 39	mov.w	@er0+,r1
 40	mov.b	r1l,@er2
 41	bra	1b
 42
 432:
 44;SDRAM setup
 45#define SDRAM_SMR 0x400040
 46
 47	mov.b	#0,r0l
 48	mov.b	r0l,@DRACCR:16
 49	mov.w	#0x188,r0
 50	mov.w	r0,@REFCR:16
 51	mov.w	#0x85b4,r0
 52	mov.w	r0,@DRAMCR:16
 53	mov.b	#0,r1l
 54	mov.b	r1l,@SDRAM_SMR
 55	mov.w	#0x84b4,r0
 56	mov.w	r0,@DRAMCR:16
 57;special thanks to Arizona Cooperative Power
 58	
 59	/* copy .data */
 60	mov.l	#__begin_data,er5
 61	mov.l	#__sdata,er6
 62	mov.l	#__edata,er4
 63	sub.l	er6,er4
 64	shlr.l	#2,er4
 651:	
 66	mov.l	@er5+,er0
 67	mov.l	er0,@er6
 68	adds	#4,er6
 69	dec.l	#1,er4
 70	bne	1b	
 71
 72	/* .bss clear */
 73	mov.l	#__sbss,er5
 74	mov.l	#__ebss,er4
 75	sub.l	er5,er4
 76	shlr.l	#2,er4		
 77	sub.l	er0,er0
 781:
 79	mov.l	er0,@er5
 80	adds	#4,er5
 81	dec.l	#1,er4
 82	bne	1b
 83
 84	/* copy kernel commandline */
 85	mov.l	#COMMAND_START,er5
 86	mov.l	#SYMBOL_NAME(_command_line),er6
 87	mov.w	#512,r4
 88	eepmov.w
 89
 90	/* linux kernel start */
 91	ldc	#0x90,ccr	/* running kernel */
 92	mov.l	#SYMBOL_NAME(init_thread_union),sp
 93	add.l	#0x2000,sp
 94	jsr	@_start_kernel
 95_exit:
 96
 97	jmp	_exit
 98
 99	rts
100
101	/* I/O port assign information */
102__platform_gpio_table:	
103	mov.l	#gpio_table,er0
104	rts
105
106#define INIT_REGS_DATA(REGS,DATA) \
107	.word	((REGS) & 0xffff),DATA
108
109init_regs:
110INIT_REGS_DATA(ASTCR,0xff)
111INIT_REGS_DATA(RDNCR,0x00)
112INIT_REGS_DATA(ABWCR,0x80)
113INIT_REGS_DATA(WTCRAH,0x27)
114INIT_REGS_DATA(WTCRAL,0x77)
115INIT_REGS_DATA(WTCRBH,0x71)
116INIT_REGS_DATA(WTCRBL,0x22)
117INIT_REGS_DATA(CSACRH,0x80)
118INIT_REGS_DATA(CSACRL,0x80)
119INIT_REGS_DATA(BROMCRH,0xa0)
120INIT_REGS_DATA(BROMCRL,0xa0)
121INIT_REGS_DATA(P3DDR,0x3a)
122INIT_REGS_DATA(P3ODR,0x06)
123INIT_REGS_DATA(PADDR,0xff)
124INIT_REGS_DATA(PFDDR,0xfe)
125INIT_REGS_DATA(PGDDR,0x0f)
126INIT_REGS_DATA(PHDDR,0x0f)
127INIT_REGS_DATA(PFCR0,0xff)
128INIT_REGS_DATA(PFCR2,0x0d)
129INIT_REGS_DATA(ITSR, 0x00)
130INIT_REGS_DATA(ITSR+1,0x3f)
131INIT_REGS_DATA(INTCR,0x20)
132		
133	.word	0
134
135gpio_table:
136	;; P1DDR
137	.byte	0x00,0x00
138	;; P2DDR
139	.byte	0x00,0x00
140	;; P3DDR
141	.byte	0x00,0x00
142	;; dummy
143	.byte	0x00,0x00
144	;; P5DDR
145	.byte	0x00,0x00
146	;; P6DDR
147	.byte	0x00,0x00
148	;; P7DDR
149	.byte	0x00,0x00
150	;; P8DDR
151	.byte	0x00,0x00
152	;; dummy
153	.byte	0x00,0x00
154	;; PADDR
155	.byte	0x00,0x00
156	;; PBDDR
157	.byte	0x00,0x00
158	;; PCDDR
159	.byte	0x00,0x00
160	;; PDDDR
161	.byte	0x00,0x00
162	;; PEDDR
163	.byte	0x00,0x00
164	;; PFDDR
165	.byte	0x00,0x00
166	;; PGDDR
167	.byte	0x00,0x00
168	;; PHDDR
169	.byte	0x00,0x00
170
171	.section .rodata
172__target_name:	
173	.asciz	"EDOSK-2674"
174	
175	.section .bss
176__command_line:	
177	.space	512
178
179	/* interrupt vector */
180	.section .vectors,"ax"
181	.long	__start
182	.long	__start
183vector	=	2
184	.rept	126
185	.long	_interrupt_redirect_table+vector*4
186vector	=	vector + 1
187	.endr