/arch/frv/mb93090-mb00/pci-vdk.c

https://bitbucket.org/evzijst/gittest · C · 467 lines · 318 code · 76 blank · 73 comment · 80 complexity · c3f8ca2e129567d5fd275b67f90c9441 MD5 · raw file

  1. /* pci-vdk.c: MB93090-MB00 (VDK) PCI support
  2. *
  3. * Copyright (C) 2003, 2004 Red Hat, Inc. All Rights Reserved.
  4. * Written by David Howells (dhowells@redhat.com)
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * as published by the Free Software Foundation; either version
  9. * 2 of the License, or (at your option) any later version.
  10. */
  11. #include <linux/config.h>
  12. #include <linux/types.h>
  13. #include <linux/kernel.h>
  14. #include <linux/sched.h>
  15. #include <linux/pci.h>
  16. #include <linux/init.h>
  17. #include <linux/ioport.h>
  18. #include <linux/delay.h>
  19. #include <linux/slab.h>
  20. #include <asm/segment.h>
  21. #include <asm/io.h>
  22. #include <asm/mb-regs.h>
  23. #include <asm/mb86943a.h>
  24. #include "pci-frv.h"
  25. unsigned int __nongpreldata pci_probe = 1;
  26. int __nongpreldata pcibios_last_bus = -1;
  27. struct pci_bus *__nongpreldata pci_root_bus;
  28. struct pci_ops *__nongpreldata pci_root_ops;
  29. /*
  30. * Functions for accessing PCI configuration space
  31. */
  32. #define CONFIG_CMD(bus, dev, where) \
  33. (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
  34. #define __set_PciCfgAddr(A) writel((A), (volatile void __iomem *) __region_CS1 + 0x80)
  35. #define __get_PciCfgDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 3))
  36. #define __get_PciCfgDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x88 + ((A) & 2))
  37. #define __get_PciCfgDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x88)
  38. #define __set_PciCfgDataB(A,V) \
  39. writeb((V), (volatile void __iomem *) __region_CS1 + 0x88 + (3 - ((A) & 3)))
  40. #define __set_PciCfgDataW(A,V) \
  41. writew((V), (volatile void __iomem *) __region_CS1 + 0x88 + (2 - ((A) & 2)))
  42. #define __set_PciCfgDataL(A,V) \
  43. writel((V), (volatile void __iomem *) __region_CS1 + 0x88)
  44. #define __get_PciBridgeDataB(A) readb((volatile void __iomem *) __region_CS1 + 0x800 + (A))
  45. #define __get_PciBridgeDataW(A) readw((volatile void __iomem *) __region_CS1 + 0x800 + (A))
  46. #define __get_PciBridgeDataL(A) readl((volatile void __iomem *) __region_CS1 + 0x800 + (A))
  47. #define __set_PciBridgeDataB(A,V) writeb((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
  48. #define __set_PciBridgeDataW(A,V) writew((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
  49. #define __set_PciBridgeDataL(A,V) writel((V), (volatile void __iomem *) __region_CS1 + 0x800 + (A))
  50. static inline int __query(const struct pci_dev *dev)
  51. {
  52. // return dev->bus->number==0 && (dev->devfn==PCI_DEVFN(0,0));
  53. // return dev->bus->number==1;
  54. // return dev->bus->number==0 &&
  55. // (dev->devfn==PCI_DEVFN(2,0) || dev->devfn==PCI_DEVFN(3,0));
  56. return 0;
  57. }
  58. /*****************************************************************************/
  59. /*
  60. *
  61. */
  62. static int pci_frv_read_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
  63. u32 *val)
  64. {
  65. u32 _value;
  66. if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
  67. _value = __get_PciBridgeDataL(where & ~3);
  68. }
  69. else {
  70. __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
  71. _value = __get_PciCfgDataL(where & ~3);
  72. }
  73. switch (size) {
  74. case 1:
  75. _value = _value >> ((where & 3) * 8);
  76. break;
  77. case 2:
  78. _value = _value >> ((where & 2) * 8);
  79. break;
  80. case 4:
  81. break;
  82. default:
  83. BUG();
  84. }
  85. *val = _value;
  86. return PCIBIOS_SUCCESSFUL;
  87. }
  88. static int pci_frv_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
  89. u32 value)
  90. {
  91. switch (size) {
  92. case 1:
  93. if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
  94. __set_PciBridgeDataB(where, value);
  95. }
  96. else {
  97. __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
  98. __set_PciCfgDataB(where, value);
  99. }
  100. break;
  101. case 2:
  102. if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
  103. __set_PciBridgeDataW(where, value);
  104. }
  105. else {
  106. __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
  107. __set_PciCfgDataW(where, value);
  108. }
  109. break;
  110. case 4:
  111. if (bus->number == 0 && devfn == PCI_DEVFN(0, 0)) {
  112. __set_PciBridgeDataL(where, value);
  113. }
  114. else {
  115. __set_PciCfgAddr(CONFIG_CMD(bus, devfn, where));
  116. __set_PciCfgDataL(where, value);
  117. }
  118. break;
  119. default:
  120. BUG();
  121. }
  122. return PCIBIOS_SUCCESSFUL;
  123. }
  124. static struct pci_ops pci_direct_frv = {
  125. pci_frv_read_config,
  126. pci_frv_write_config,
  127. };
  128. /*
  129. * Before we decide to use direct hardware access mechanisms, we try to do some
  130. * trivial checks to ensure it at least _seems_ to be working -- we just test
  131. * whether bus 00 contains a host bridge (this is similar to checking
  132. * techniques used in XFree86, but ours should be more reliable since we
  133. * attempt to make use of direct access hints provided by the PCI BIOS).
  134. *
  135. * This should be close to trivial, but it isn't, because there are buggy
  136. * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
  137. */
  138. static int __init pci_sanity_check(struct pci_ops *o)
  139. {
  140. struct pci_bus bus; /* Fake bus and device */
  141. u32 id;
  142. bus.number = 0;
  143. if (o->read(&bus, 0, PCI_VENDOR_ID, 4, &id) == PCIBIOS_SUCCESSFUL) {
  144. printk("PCI: VDK Bridge device:vendor: %08x\n", id);
  145. if (id == 0x200e10cf)
  146. return 1;
  147. }
  148. printk("PCI: VDK Bridge: Sanity check failed\n");
  149. return 0;
  150. }
  151. static struct pci_ops * __init pci_check_direct(void)
  152. {
  153. unsigned long flags;
  154. local_irq_save(flags);
  155. /* check if access works */
  156. if (pci_sanity_check(&pci_direct_frv)) {
  157. local_irq_restore(flags);
  158. printk("PCI: Using configuration frv\n");
  159. // request_mem_region(0xBE040000, 256, "FRV bridge");
  160. // request_mem_region(0xBFFFFFF4, 12, "PCI frv");
  161. return &pci_direct_frv;
  162. }
  163. local_irq_restore(flags);
  164. return NULL;
  165. }
  166. /*
  167. * Several buggy motherboards address only 16 devices and mirror
  168. * them to next 16 IDs. We try to detect this `feature' on all
  169. * primary buses (those containing host bridges as they are
  170. * expected to be unique) and remove the ghost devices.
  171. */
  172. static void __init pcibios_fixup_ghosts(struct pci_bus *b)
  173. {
  174. struct list_head *ln, *mn;
  175. struct pci_dev *d, *e;
  176. int mirror = PCI_DEVFN(16,0);
  177. int seen_host_bridge = 0;
  178. int i;
  179. for (ln=b->devices.next; ln != &b->devices; ln=ln->next) {
  180. d = pci_dev_b(ln);
  181. if ((d->class >> 8) == PCI_CLASS_BRIDGE_HOST)
  182. seen_host_bridge++;
  183. for (mn=ln->next; mn != &b->devices; mn=mn->next) {
  184. e = pci_dev_b(mn);
  185. if (e->devfn != d->devfn + mirror ||
  186. e->vendor != d->vendor ||
  187. e->device != d->device ||
  188. e->class != d->class)
  189. continue;
  190. for(i=0; i<PCI_NUM_RESOURCES; i++)
  191. if (e->resource[i].start != d->resource[i].start ||
  192. e->resource[i].end != d->resource[i].end ||
  193. e->resource[i].flags != d->resource[i].flags)
  194. continue;
  195. break;
  196. }
  197. if (mn == &b->devices)
  198. return;
  199. }
  200. if (!seen_host_bridge)
  201. return;
  202. printk("PCI: Ignoring ghost devices on bus %02x\n", b->number);
  203. ln = &b->devices;
  204. while (ln->next != &b->devices) {
  205. d = pci_dev_b(ln->next);
  206. if (d->devfn >= mirror) {
  207. list_del(&d->global_list);
  208. list_del(&d->bus_list);
  209. kfree(d);
  210. } else
  211. ln = ln->next;
  212. }
  213. }
  214. /*
  215. * Discover remaining PCI buses in case there are peer host bridges.
  216. * We use the number of last PCI bus provided by the PCI BIOS.
  217. */
  218. static void __init pcibios_fixup_peer_bridges(void)
  219. {
  220. struct pci_bus bus;
  221. struct pci_dev dev;
  222. int n;
  223. u16 l;
  224. if (pcibios_last_bus <= 0 || pcibios_last_bus >= 0xff)
  225. return;
  226. printk("PCI: Peer bridge fixup\n");
  227. for (n=0; n <= pcibios_last_bus; n++) {
  228. if (pci_find_bus(0, n))
  229. continue;
  230. bus.number = n;
  231. bus.ops = pci_root_ops;
  232. dev.bus = &bus;
  233. for(dev.devfn=0; dev.devfn<256; dev.devfn += 8)
  234. if (!pci_read_config_word(&dev, PCI_VENDOR_ID, &l) &&
  235. l != 0x0000 && l != 0xffff) {
  236. printk("Found device at %02x:%02x [%04x]\n", n, dev.devfn, l);
  237. printk("PCI: Discovered peer bus %02x\n", n);
  238. pci_scan_bus(n, pci_root_ops, NULL);
  239. break;
  240. }
  241. }
  242. }
  243. /*
  244. * Exceptions for specific devices. Usually work-arounds for fatal design flaws.
  245. */
  246. static void __init pci_fixup_umc_ide(struct pci_dev *d)
  247. {
  248. /*
  249. * UM8886BF IDE controller sets region type bits incorrectly,
  250. * therefore they look like memory despite of them being I/O.
  251. */
  252. int i;
  253. printk("PCI: Fixing base address flags for device %s\n", pci_name(d));
  254. for(i=0; i<4; i++)
  255. d->resource[i].flags |= PCI_BASE_ADDRESS_SPACE_IO;
  256. }
  257. static void __init pci_fixup_ide_bases(struct pci_dev *d)
  258. {
  259. int i;
  260. /*
  261. * PCI IDE controllers use non-standard I/O port decoding, respect it.
  262. */
  263. if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
  264. return;
  265. printk("PCI: IDE base address fixup for %s\n", pci_name(d));
  266. for(i=0; i<4; i++) {
  267. struct resource *r = &d->resource[i];
  268. if ((r->start & ~0x80) == 0x374) {
  269. r->start |= 2;
  270. r->end = r->start;
  271. }
  272. }
  273. }
  274. static void __init pci_fixup_ide_trash(struct pci_dev *d)
  275. {
  276. int i;
  277. /*
  278. * There exist PCI IDE controllers which have utter garbage
  279. * in first four base registers. Ignore that.
  280. */
  281. printk("PCI: IDE base address trash cleared for %s\n", pci_name(d));
  282. for(i=0; i<4; i++)
  283. d->resource[i].start = d->resource[i].end = d->resource[i].flags = 0;
  284. }
  285. static void __devinit pci_fixup_latency(struct pci_dev *d)
  286. {
  287. /*
  288. * SiS 5597 and 5598 chipsets require latency timer set to
  289. * at most 32 to avoid lockups.
  290. */
  291. DBG("PCI: Setting max latency to 32\n");
  292. pcibios_max_latency = 32;
  293. }
  294. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_UMC, PCI_DEVICE_ID_UMC_UM8886BF, pci_fixup_umc_ide);
  295. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5513, pci_fixup_ide_trash);
  296. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, pci_fixup_latency);
  297. DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5598, pci_fixup_latency);
  298. DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
  299. /*
  300. * Called after each bus is probed, but before its children
  301. * are examined.
  302. */
  303. void __init pcibios_fixup_bus(struct pci_bus *bus)
  304. {
  305. #if 0
  306. printk("### PCIBIOS_FIXUP_BUS(%d)\n",bus->number);
  307. #endif
  308. pcibios_fixup_ghosts(bus);
  309. pci_read_bridge_bases(bus);
  310. if (bus->number == 0) {
  311. struct list_head *ln;
  312. struct pci_dev *dev;
  313. for (ln=bus->devices.next; ln != &bus->devices; ln=ln->next) {
  314. dev = pci_dev_b(ln);
  315. if (dev->devfn == 0) {
  316. dev->resource[0].start = 0;
  317. dev->resource[0].end = 0;
  318. }
  319. }
  320. }
  321. }
  322. /*
  323. * Initialization. Try all known PCI access methods. Note that we support
  324. * using both PCI BIOS and direct access: in such cases, we use I/O ports
  325. * to access config space, but we still keep BIOS order of cards to be
  326. * compatible with 2.0.X. This should go away some day.
  327. */
  328. int __init pcibios_init(void)
  329. {
  330. struct pci_ops *dir = NULL;
  331. if (!mb93090_mb00_detected)
  332. return -ENXIO;
  333. __reg_MB86943_sl_ctl |= MB86943_SL_CTL_DRCT_MASTER_SWAP | MB86943_SL_CTL_DRCT_SLAVE_SWAP;
  334. __reg_MB86943_ecs_base(1) = ((__region_CS2 + 0x01000000) >> 9) | 0x08000000;
  335. __reg_MB86943_ecs_base(2) = ((__region_CS2 + 0x00000000) >> 9) | 0x08000000;
  336. *(volatile uint32_t *) (__region_CS1 + 0x848) = 0xe0000000;
  337. *(volatile uint32_t *) (__region_CS1 + 0x8b8) = 0x00000000;
  338. __reg_MB86943_sl_pci_io_base = (__region_CS2 + 0x04000000) >> 9;
  339. __reg_MB86943_sl_pci_mem_base = (__region_CS2 + 0x08000000) >> 9;
  340. __reg_MB86943_pci_sl_io_base = __region_CS2 + 0x04000000;
  341. __reg_MB86943_pci_sl_mem_base = __region_CS2 + 0x08000000;
  342. mb();
  343. *(volatile unsigned long *)(__region_CS2+0x01300014) == 1;
  344. ioport_resource.start = (__reg_MB86943_sl_pci_io_base << 9) & 0xfffffc00;
  345. ioport_resource.end = (__reg_MB86943_sl_pci_io_range << 9) | 0x3ff;
  346. ioport_resource.end += ioport_resource.start;
  347. printk("PCI IO window: %08lx-%08lx\n", ioport_resource.start, ioport_resource.end);
  348. iomem_resource.start = (__reg_MB86943_sl_pci_mem_base << 9) & 0xfffffc00;
  349. /* Reserve somewhere to write to flush posted writes. */
  350. iomem_resource.start += 0x400;
  351. iomem_resource.end = (__reg_MB86943_sl_pci_mem_range << 9) | 0x3ff;
  352. iomem_resource.end += iomem_resource.start;
  353. printk("PCI MEM window: %08lx-%08lx\n", iomem_resource.start, iomem_resource.end);
  354. printk("PCI DMA memory: %08lx-%08lx\n", dma_coherent_mem_start, dma_coherent_mem_end);
  355. if (!pci_probe)
  356. return -ENXIO;
  357. dir = pci_check_direct();
  358. if (dir)
  359. pci_root_ops = dir;
  360. else {
  361. printk("PCI: No PCI bus detected\n");
  362. return -ENXIO;
  363. }
  364. printk("PCI: Probing PCI hardware\n");
  365. pci_root_bus = pci_scan_bus(0, pci_root_ops, NULL);
  366. pcibios_irq_init();
  367. pcibios_fixup_peer_bridges();
  368. pcibios_fixup_irqs();
  369. pcibios_resource_survey();
  370. return 0;
  371. }
  372. arch_initcall(pcibios_init);
  373. char * __init pcibios_setup(char *str)
  374. {
  375. if (!strcmp(str, "off")) {
  376. pci_probe = 0;
  377. return NULL;
  378. } else if (!strncmp(str, "lastbus=", 8)) {
  379. pcibios_last_bus = simple_strtol(str+8, NULL, 0);
  380. return NULL;
  381. }
  382. return str;
  383. }
  384. int pcibios_enable_device(struct pci_dev *dev, int mask)
  385. {
  386. int err;
  387. if ((err = pcibios_enable_resources(dev, mask)) < 0)
  388. return err;
  389. pcibios_enable_irq(dev);
  390. return 0;
  391. }