/arch/frv/mb93090-mb00/pci-frv.c

https://bitbucket.org/evzijst/gittest · C · 288 lines · 188 code · 26 blank · 74 comment · 54 complexity · 5b4ac5afdd33223bc09a9390e3ca5e03 MD5 · raw file

  1. /* pci-frv.c: low-level PCI access routines
  2. *
  3. * Copyright (C) 2003-5 Red Hat, Inc. All Rights Reserved.
  4. * Written by David Howells (dhowells@redhat.com)
  5. * - Derived from the i386 equivalent stuff
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License
  9. * as published by the Free Software Foundation; either version
  10. * 2 of the License, or (at your option) any later version.
  11. */
  12. #include <linux/types.h>
  13. #include <linux/kernel.h>
  14. #include <linux/pci.h>
  15. #include <linux/init.h>
  16. #include <linux/ioport.h>
  17. #include <linux/errno.h>
  18. #include "pci-frv.h"
  19. #if 0
  20. void
  21. pcibios_update_resource(struct pci_dev *dev, struct resource *root,
  22. struct resource *res, int resource)
  23. {
  24. u32 new, check;
  25. int reg;
  26. new = res->start | (res->flags & PCI_REGION_FLAG_MASK);
  27. if (resource < 6) {
  28. reg = PCI_BASE_ADDRESS_0 + 4*resource;
  29. } else if (resource == PCI_ROM_RESOURCE) {
  30. res->flags |= IORESOURCE_ROM_ENABLE;
  31. new |= PCI_ROM_ADDRESS_ENABLE;
  32. reg = dev->rom_base_reg;
  33. } else {
  34. /* Somebody might have asked allocation of a non-standard resource */
  35. return;
  36. }
  37. pci_write_config_dword(dev, reg, new);
  38. pci_read_config_dword(dev, reg, &check);
  39. if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) {
  40. printk(KERN_ERR "PCI: Error while updating region "
  41. "%s/%d (%08x != %08x)\n", pci_name(dev), resource,
  42. new, check);
  43. }
  44. }
  45. #endif
  46. /*
  47. * We need to avoid collisions with `mirrored' VGA ports
  48. * and other strange ISA hardware, so we always want the
  49. * addresses to be allocated in the 0x000-0x0ff region
  50. * modulo 0x400.
  51. *
  52. * Why? Because some silly external IO cards only decode
  53. * the low 10 bits of the IO address. The 0x00-0xff region
  54. * is reserved for motherboard devices that decode all 16
  55. * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  56. * but we want to try to avoid allocating at 0x2900-0x2bff
  57. * which might have be mirrored at 0x0100-0x03ff..
  58. */
  59. void
  60. pcibios_align_resource(void *data, struct resource *res,
  61. unsigned long size, unsigned long align)
  62. {
  63. if (res->flags & IORESOURCE_IO) {
  64. unsigned long start = res->start;
  65. if (start & 0x300) {
  66. start = (start + 0x3ff) & ~0x3ff;
  67. res->start = start;
  68. }
  69. }
  70. }
  71. /*
  72. * Handle resources of PCI devices. If the world were perfect, we could
  73. * just allocate all the resource regions and do nothing more. It isn't.
  74. * On the other hand, we cannot just re-allocate all devices, as it would
  75. * require us to know lots of host bridge internals. So we attempt to
  76. * keep as much of the original configuration as possible, but tweak it
  77. * when it's found to be wrong.
  78. *
  79. * Known BIOS problems we have to work around:
  80. * - I/O or memory regions not configured
  81. * - regions configured, but not enabled in the command register
  82. * - bogus I/O addresses above 64K used
  83. * - expansion ROMs left enabled (this may sound harmless, but given
  84. * the fact the PCI specs explicitly allow address decoders to be
  85. * shared between expansion ROMs and other resource regions, it's
  86. * at least dangerous)
  87. *
  88. * Our solution:
  89. * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
  90. * This gives us fixed barriers on where we can allocate.
  91. * (2) Allocate resources for all enabled devices. If there is
  92. * a collision, just mark the resource as unallocated. Also
  93. * disable expansion ROMs during this step.
  94. * (3) Try to allocate resources for disabled devices. If the
  95. * resources were assigned correctly, everything goes well,
  96. * if they weren't, they won't disturb allocation of other
  97. * resources.
  98. * (4) Assign new addresses to resources which were either
  99. * not configured at all or misconfigured. If explicitly
  100. * requested by the user, configure expansion ROM address
  101. * as well.
  102. */
  103. static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
  104. {
  105. struct list_head *ln;
  106. struct pci_bus *bus;
  107. struct pci_dev *dev;
  108. int idx;
  109. struct resource *r, *pr;
  110. /* Depth-First Search on bus tree */
  111. for (ln=bus_list->next; ln != bus_list; ln=ln->next) {
  112. bus = pci_bus_b(ln);
  113. if ((dev = bus->self)) {
  114. for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
  115. r = &dev->resource[idx];
  116. if (!r->start)
  117. continue;
  118. pr = pci_find_parent_resource(dev, r);
  119. if (!pr || request_resource(pr, r) < 0)
  120. printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, pci_name(dev));
  121. }
  122. }
  123. pcibios_allocate_bus_resources(&bus->children);
  124. }
  125. }
  126. static void __init pcibios_allocate_resources(int pass)
  127. {
  128. struct pci_dev *dev = NULL;
  129. int idx, disabled;
  130. u16 command;
  131. struct resource *r, *pr;
  132. while (dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev),
  133. dev != NULL
  134. ) {
  135. pci_read_config_word(dev, PCI_COMMAND, &command);
  136. for(idx = 0; idx < 6; idx++) {
  137. r = &dev->resource[idx];
  138. if (r->parent) /* Already allocated */
  139. continue;
  140. if (!r->start) /* Address not assigned at all */
  141. continue;
  142. if (r->flags & IORESOURCE_IO)
  143. disabled = !(command & PCI_COMMAND_IO);
  144. else
  145. disabled = !(command & PCI_COMMAND_MEMORY);
  146. if (pass == disabled) {
  147. DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
  148. r->start, r->end, r->flags, disabled, pass);
  149. pr = pci_find_parent_resource(dev, r);
  150. if (!pr || request_resource(pr, r) < 0) {
  151. printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, pci_name(dev));
  152. /* We'll assign a new address later */
  153. r->end -= r->start;
  154. r->start = 0;
  155. }
  156. }
  157. }
  158. if (!pass) {
  159. r = &dev->resource[PCI_ROM_RESOURCE];
  160. if (r->flags & IORESOURCE_ROM_ENABLE) {
  161. /* Turn the ROM off, leave the resource region, but keep it unregistered. */
  162. u32 reg;
  163. DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
  164. r->flags &= ~IORESOURCE_ROM_ENABLE;
  165. pci_read_config_dword(dev, dev->rom_base_reg, &reg);
  166. pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
  167. }
  168. }
  169. }
  170. }
  171. static void __init pcibios_assign_resources(void)
  172. {
  173. struct pci_dev *dev = NULL;
  174. int idx;
  175. struct resource *r;
  176. while (dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev),
  177. dev != NULL
  178. ) {
  179. int class = dev->class >> 8;
  180. /* Don't touch classless devices and host bridges */
  181. if (!class || class == PCI_CLASS_BRIDGE_HOST)
  182. continue;
  183. for(idx=0; idx<6; idx++) {
  184. r = &dev->resource[idx];
  185. /*
  186. * Don't touch IDE controllers and I/O ports of video cards!
  187. */
  188. if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) ||
  189. (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO)))
  190. continue;
  191. /*
  192. * We shall assign a new address to this resource, either because
  193. * the BIOS forgot to do so or because we have decided the old
  194. * address was unusable for some reason.
  195. */
  196. if (!r->start && r->end)
  197. pci_assign_resource(dev, idx);
  198. }
  199. if (pci_probe & PCI_ASSIGN_ROMS) {
  200. r = &dev->resource[PCI_ROM_RESOURCE];
  201. r->end -= r->start;
  202. r->start = 0;
  203. if (r->end)
  204. pci_assign_resource(dev, PCI_ROM_RESOURCE);
  205. }
  206. }
  207. }
  208. void __init pcibios_resource_survey(void)
  209. {
  210. DBG("PCI: Allocating resources\n");
  211. pcibios_allocate_bus_resources(&pci_root_buses);
  212. pcibios_allocate_resources(0);
  213. pcibios_allocate_resources(1);
  214. pcibios_assign_resources();
  215. }
  216. int pcibios_enable_resources(struct pci_dev *dev, int mask)
  217. {
  218. u16 cmd, old_cmd;
  219. int idx;
  220. struct resource *r;
  221. pci_read_config_word(dev, PCI_COMMAND, &cmd);
  222. old_cmd = cmd;
  223. for(idx=0; idx<6; idx++) {
  224. /* Only set up the requested stuff */
  225. if (!(mask & (1<<idx)))
  226. continue;
  227. r = &dev->resource[idx];
  228. if (!r->start && r->end) {
  229. printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
  230. return -EINVAL;
  231. }
  232. if (r->flags & IORESOURCE_IO)
  233. cmd |= PCI_COMMAND_IO;
  234. if (r->flags & IORESOURCE_MEM)
  235. cmd |= PCI_COMMAND_MEMORY;
  236. }
  237. if (dev->resource[PCI_ROM_RESOURCE].start)
  238. cmd |= PCI_COMMAND_MEMORY;
  239. if (cmd != old_cmd) {
  240. printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
  241. pci_write_config_word(dev, PCI_COMMAND, cmd);
  242. }
  243. return 0;
  244. }
  245. /*
  246. * If we set up a device for bus mastering, we need to check the latency
  247. * timer as certain crappy BIOSes forget to set it properly.
  248. */
  249. unsigned int pcibios_max_latency = 255;
  250. void pcibios_set_master(struct pci_dev *dev)
  251. {
  252. u8 lat;
  253. pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
  254. if (lat < 16)
  255. lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
  256. else if (lat > pcibios_max_latency)
  257. lat = pcibios_max_latency;
  258. else
  259. return;
  260. printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
  261. pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
  262. }