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/arch/arm26/lib/io-writesb.S

https://bitbucket.org/evzijst/gittest
Assembly | 122 lines | 102 code | 20 blank | 0 comment | 1 complexity | 0dce303121179e275aa152dec7306278 MD5 | raw file
  1/*
  2 *  linux/arch/arm26/lib/io-writesb.S
  3 *
  4 *  Copyright (C) 1995-2000 Russell King
  5 *
  6 * This program is free software; you can redistribute it and/or modify
  7 * it under the terms of the GNU General Public License version 2 as
  8 * published by the Free Software Foundation.
  9 */
 10#include <linux/linkage.h>
 11#include <asm/assembler.h>
 12#include <asm/hardware.h>
 13
 14.outsb_align:	rsb	ip, ip, #4
 15		cmp	ip, r2
 16		movgt	ip, r2
 17		cmp	ip, #2
 18		ldrb	r3, [r1], #1
 19		strb	r3, [r0]
 20		ldrgeb	r3, [r1], #1
 21		strgeb	r3, [r0]
 22		ldrgtb	r3, [r1], #1
 23		strgtb	r3, [r0]
 24		subs	r2, r2, ip
 25		bne	.outsb_aligned
 26
 27ENTRY(__raw_writesb)
 28		teq	r2, #0		@ do we have to check for the zero len?
 29		moveq	pc, lr
 30		ands	ip, r1, #3
 31		bne	.outsb_align
 32
 33.outsb_aligned:	stmfd	sp!, {r4 - r6, lr}
 34
 35		subs	r2, r2, #16
 36		bmi	.outsb_no_16
 37
 38.outsb_16_lp:	ldmia	r1!, {r3 - r6}
 39
 40		strb	r3, [r0]
 41		mov	r3, r3, lsr #8
 42		strb	r3, [r0]
 43		mov	r3, r3, lsr #8
 44		strb	r3, [r0]
 45		mov	r3, r3, lsr #8
 46		strb	r3, [r0]
 47
 48		strb	r4, [r0]
 49		mov	r4, r4, lsr #8
 50		strb	r4, [r0]
 51		mov	r4, r4, lsr #8
 52		strb	r4, [r0]
 53		mov	r4, r4, lsr #8
 54		strb	r4, [r0]
 55
 56		strb	r5, [r0]
 57		mov	r5, r5, lsr #8
 58		strb	r5, [r0]
 59		mov	r5, r5, lsr #8
 60		strb	r5, [r0]
 61		mov	r5, r5, lsr #8
 62		strb	r5, [r0]
 63
 64		strb	r6, [r0]
 65		mov	r6, r6, lsr #8
 66		strb	r6, [r0]
 67		mov	r6, r6, lsr #8
 68		strb	r6, [r0]
 69		mov	r6, r6, lsr #8
 70		strb	r6, [r0]
 71
 72		subs	r2, r2, #16
 73		bpl	.outsb_16_lp
 74
 75		tst	r2, #15
 76		LOADREGS(eqfd, sp!, {r4 - r6, pc})
 77
 78.outsb_no_16:	tst	r2, #8
 79		beq	.outsb_no_8
 80
 81		ldmia	r1!, {r3, r4}
 82
 83		strb	r3, [r0]
 84		mov	r3, r3, lsr #8
 85		strb	r3, [r0]
 86		mov	r3, r3, lsr #8
 87		strb	r3, [r0]
 88		mov	r3, r3, lsr #8
 89		strb	r3, [r0]
 90
 91		strb	r4, [r0]
 92		mov	r4, r4, lsr #8
 93		strb	r4, [r0]
 94		mov	r4, r4, lsr #8
 95		strb	r4, [r0]
 96		mov	r4, r4, lsr #8
 97		strb	r4, [r0]
 98
 99.outsb_no_8:	tst	r2, #4
100		beq	.outsb_no_4
101
102		ldr	r3, [r1], #4
103		strb	r3, [r0]
104		mov	r3, r3, lsr #8
105		strb	r3, [r0]
106		mov	r3, r3, lsr #8
107		strb	r3, [r0]
108		mov	r3, r3, lsr #8
109		strb	r3, [r0]
110
111.outsb_no_4:	ands	r2, r2, #3
112		LOADREGS(eqfd, sp!, {r4 - r6, pc})
113
114		cmp	r2, #2
115		ldrb	r3, [r1], #1
116		strb	r3, [r0]
117		ldrgeb	r3, [r1], #1
118		strgeb	r3, [r0]
119		ldrgtb	r3, [r1]
120		strgtb	r3, [r0]
121
122		LOADREGS(fd, sp!, {r4 - r6, pc})