/arch/arm/mm/proc-v6.S

https://bitbucket.org/evzijst/gittest · Assembly · 272 lines · 159 code · 31 blank · 82 comment · 3 complexity · 6f3f402c8125f7c25e03a852d6086f0a MD5 · raw file

  1. /*
  2. * linux/arch/arm/mm/proc-v6.S
  3. *
  4. * Copyright (C) 2001 Deep Blue Solutions Ltd.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This is the "shell" of the ARMv6 processor support.
  11. */
  12. #include <linux/linkage.h>
  13. #include <asm/assembler.h>
  14. #include <asm/constants.h>
  15. #include <asm/procinfo.h>
  16. #include <asm/pgtable.h>
  17. #include "proc-macros.S"
  18. #define D_CACHE_LINE_SIZE 32
  19. .macro cpsie, flags
  20. .ifc \flags, f
  21. .long 0xf1080040
  22. .exitm
  23. .endif
  24. .ifc \flags, i
  25. .long 0xf1080080
  26. .exitm
  27. .endif
  28. .ifc \flags, if
  29. .long 0xf10800c0
  30. .exitm
  31. .endif
  32. .err
  33. .endm
  34. .macro cpsid, flags
  35. .ifc \flags, f
  36. .long 0xf10c0040
  37. .exitm
  38. .endif
  39. .ifc \flags, i
  40. .long 0xf10c0080
  41. .exitm
  42. .endif
  43. .ifc \flags, if
  44. .long 0xf10c00c0
  45. .exitm
  46. .endif
  47. .err
  48. .endm
  49. ENTRY(cpu_v6_proc_init)
  50. mov pc, lr
  51. ENTRY(cpu_v6_proc_fin)
  52. mov pc, lr
  53. /*
  54. * cpu_v6_reset(loc)
  55. *
  56. * Perform a soft reset of the system. Put the CPU into the
  57. * same state as it would be if it had been reset, and branch
  58. * to what would be the reset vector.
  59. *
  60. * - loc - location to jump to for soft reset
  61. *
  62. * It is assumed that:
  63. */
  64. .align 5
  65. ENTRY(cpu_v6_reset)
  66. mov pc, r0
  67. /*
  68. * cpu_v6_do_idle()
  69. *
  70. * Idle the processor (eg, wait for interrupt).
  71. *
  72. * IRQs are already disabled.
  73. */
  74. ENTRY(cpu_v6_do_idle)
  75. mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
  76. mov pc, lr
  77. ENTRY(cpu_v6_dcache_clean_area)
  78. #ifndef TLB_CAN_READ_FROM_L1_CACHE
  79. 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
  80. add r0, r0, #D_CACHE_LINE_SIZE
  81. subs r1, r1, #D_CACHE_LINE_SIZE
  82. bhi 1b
  83. #endif
  84. mov pc, lr
  85. /*
  86. * cpu_arm926_switch_mm(pgd_phys, tsk)
  87. *
  88. * Set the translation table base pointer to be pgd_phys
  89. *
  90. * - pgd_phys - physical address of new TTB
  91. *
  92. * It is assumed that:
  93. * - we are not using split page tables
  94. */
  95. ENTRY(cpu_v6_switch_mm)
  96. mov r2, #0
  97. ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
  98. mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
  99. mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
  100. mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
  101. mcr p15, 0, r1, c13, c0, 1 @ set context ID
  102. mov pc, lr
  103. #define nG (1 << 11)
  104. #define APX (1 << 9)
  105. #define AP1 (1 << 5)
  106. #define AP0 (1 << 4)
  107. #define XN (1 << 0)
  108. /*
  109. * cpu_v6_set_pte(ptep, pte)
  110. *
  111. * Set a level 2 translation table entry.
  112. *
  113. * - ptep - pointer to level 2 translation table entry
  114. * (hardware version is stored at -1024 bytes)
  115. * - pte - PTE value to store
  116. *
  117. * Permissions:
  118. * YUWD APX AP1 AP0 SVC User
  119. * 0xxx 0 0 0 no acc no acc
  120. * 100x 1 0 1 r/o no acc
  121. * 10x0 1 0 1 r/o no acc
  122. * 1011 0 0 1 r/w no acc
  123. * 110x 1 1 0 r/o r/o
  124. * 11x0 1 1 0 r/o r/o
  125. * 1111 0 1 1 r/w r/w
  126. */
  127. ENTRY(cpu_v6_set_pte)
  128. str r1, [r0], #-2048 @ linux version
  129. bic r2, r1, #0x00000ff0
  130. bic r2, r2, #0x00000003
  131. orr r2, r2, #AP0 | 2
  132. tst r1, #L_PTE_WRITE
  133. tstne r1, #L_PTE_DIRTY
  134. orreq r2, r2, #APX
  135. tst r1, #L_PTE_USER
  136. orrne r2, r2, #AP1 | nG
  137. tstne r2, #APX
  138. eorne r2, r2, #AP0
  139. tst r1, #L_PTE_YOUNG
  140. biceq r2, r2, #APX | AP1 | AP0
  141. @ tst r1, #L_PTE_EXEC
  142. @ orreq r2, r2, #XN
  143. tst r1, #L_PTE_PRESENT
  144. moveq r2, #0
  145. str r2, [r0]
  146. mcr p15, 0, r0, c7, c10, 1 @ flush_pte
  147. mov pc, lr
  148. cpu_v6_name:
  149. .asciz "Some Random V6 Processor"
  150. .align
  151. .section ".text.init", #alloc, #execinstr
  152. /*
  153. * __v6_setup
  154. *
  155. * Initialise TLB, Caches, and MMU state ready to switch the MMU
  156. * on. Return in r0 the new CP15 C1 control register setting.
  157. *
  158. * We automatically detect if we have a Harvard cache, and use the
  159. * Harvard cache control instructions insead of the unified cache
  160. * control instructions.
  161. *
  162. * This should be able to cover all ARMv6 cores.
  163. *
  164. * It is assumed that:
  165. * - cache type register is implemented
  166. */
  167. __v6_setup:
  168. mov r0, #0
  169. mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
  170. mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
  171. mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
  172. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
  173. mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
  174. mcr p15, 0, r0, c2, c0, 2 @ TTB control register
  175. mcr p15, 0, r4, c2, c0, 1 @ load TTB1
  176. #ifdef CONFIG_VFP
  177. mrc p15, 0, r0, c1, c0, 2
  178. orr r0, r0, #(3 << 20)
  179. mcr p15, 0, r0, c1, c0, 2 @ Enable full access to VFP
  180. #endif
  181. mrc p15, 0, r0, c1, c0, 0 @ read control register
  182. ldr r5, v6_cr1_clear @ get mask for bits to clear
  183. bic r0, r0, r5 @ clear bits them
  184. ldr r5, v6_cr1_set @ get mask for bits to set
  185. orr r0, r0, r5 @ set them
  186. mov pc, lr @ return to head.S:__ret
  187. /*
  188. * V X F I D LR
  189. * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
  190. * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
  191. * 0 110 0011 1.00 .111 1101 < we want
  192. */
  193. .type v6_cr1_clear, #object
  194. .type v6_cr1_set, #object
  195. v6_cr1_clear:
  196. .word 0x01e0fb7f
  197. v6_cr1_set:
  198. .word 0x00c0387d
  199. .type v6_processor_functions, #object
  200. ENTRY(v6_processor_functions)
  201. .word v6_early_abort
  202. .word cpu_v6_proc_init
  203. .word cpu_v6_proc_fin
  204. .word cpu_v6_reset
  205. .word cpu_v6_do_idle
  206. .word cpu_v6_dcache_clean_area
  207. .word cpu_v6_switch_mm
  208. .word cpu_v6_set_pte
  209. .size v6_processor_functions, . - v6_processor_functions
  210. .type cpu_arch_name, #object
  211. cpu_arch_name:
  212. .asciz "armv6"
  213. .size cpu_arch_name, . - cpu_arch_name
  214. .type cpu_elf_name, #object
  215. cpu_elf_name:
  216. .asciz "v6"
  217. .size cpu_elf_name, . - cpu_elf_name
  218. .align
  219. .section ".proc.info", #alloc, #execinstr
  220. /*
  221. * Match any ARMv6 processor core.
  222. */
  223. .type __v6_proc_info, #object
  224. __v6_proc_info:
  225. .long 0x0007b000
  226. .long 0x0007f000
  227. .long PMD_TYPE_SECT | \
  228. PMD_SECT_BUFFERABLE | \
  229. PMD_SECT_CACHEABLE | \
  230. PMD_SECT_AP_WRITE | \
  231. PMD_SECT_AP_READ
  232. b __v6_setup
  233. .long cpu_arch_name
  234. .long cpu_elf_name
  235. .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_VFP|HWCAP_EDSP|HWCAP_JAVA
  236. .long cpu_v6_name
  237. .long v6_processor_functions
  238. .long v6wbi_tlb_fns
  239. .long v6_user_fns
  240. .long v6_cache_fns
  241. .size __v6_proc_info, . - __v6_proc_info