/arch/arm/mm/copypage-v6.c

https://bitbucket.org/evzijst/gittest · C · 155 lines · 86 code · 28 blank · 41 comment · 4 complexity · aa5c891ba9f6ff9ef440c8b0b036b62b MD5 · raw file

  1. /*
  2. * linux/arch/arm/mm/copypage-v6.c
  3. *
  4. * Copyright (C) 2002 Deep Blue Solutions Ltd, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/init.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/mm.h>
  13. #include <asm/page.h>
  14. #include <asm/pgtable.h>
  15. #include <asm/shmparam.h>
  16. #include <asm/tlbflush.h>
  17. #include <asm/cacheflush.h>
  18. #if SHMLBA > 16384
  19. #error FIX ME
  20. #endif
  21. #define from_address (0xffff8000)
  22. #define from_pgprot PAGE_KERNEL
  23. #define to_address (0xffffc000)
  24. #define to_pgprot PAGE_KERNEL
  25. static pte_t *from_pte;
  26. static pte_t *to_pte;
  27. static DEFINE_SPINLOCK(v6_lock);
  28. #define DCACHE_COLOUR(vaddr) ((vaddr & (SHMLBA - 1)) >> PAGE_SHIFT)
  29. /*
  30. * Copy the user page. No aliasing to deal with so we can just
  31. * attack the kernel's existing mapping of these pages.
  32. */
  33. void v6_copy_user_page_nonaliasing(void *kto, const void *kfrom, unsigned long vaddr)
  34. {
  35. copy_page(kto, kfrom);
  36. }
  37. /*
  38. * Clear the user page. No aliasing to deal with so we can just
  39. * attack the kernel's existing mapping of this page.
  40. */
  41. void v6_clear_user_page_nonaliasing(void *kaddr, unsigned long vaddr)
  42. {
  43. clear_page(kaddr);
  44. }
  45. /*
  46. * Copy the page, taking account of the cache colour.
  47. */
  48. void v6_copy_user_page_aliasing(void *kto, const void *kfrom, unsigned long vaddr)
  49. {
  50. unsigned int offset = DCACHE_COLOUR(vaddr);
  51. unsigned long from, to;
  52. /*
  53. * Discard data in the kernel mapping for the new page.
  54. * FIXME: needs this MCRR to be supported.
  55. */
  56. __asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06"
  57. :
  58. : "r" (kto),
  59. "r" ((unsigned long)kto + PAGE_SIZE - L1_CACHE_BYTES)
  60. : "cc");
  61. /*
  62. * Now copy the page using the same cache colour as the
  63. * pages ultimate destination.
  64. */
  65. spin_lock(&v6_lock);
  66. set_pte(from_pte + offset, pfn_pte(__pa(kfrom) >> PAGE_SHIFT, from_pgprot));
  67. set_pte(to_pte + offset, pfn_pte(__pa(kto) >> PAGE_SHIFT, to_pgprot));
  68. from = from_address + (offset << PAGE_SHIFT);
  69. to = to_address + (offset << PAGE_SHIFT);
  70. flush_tlb_kernel_page(from);
  71. flush_tlb_kernel_page(to);
  72. copy_page((void *)to, (void *)from);
  73. spin_unlock(&v6_lock);
  74. }
  75. /*
  76. * Clear the user page. We need to deal with the aliasing issues,
  77. * so remap the kernel page into the same cache colour as the user
  78. * page.
  79. */
  80. void v6_clear_user_page_aliasing(void *kaddr, unsigned long vaddr)
  81. {
  82. unsigned int offset = DCACHE_COLOUR(vaddr);
  83. unsigned long to = to_address + (offset << PAGE_SHIFT);
  84. /*
  85. * Discard data in the kernel mapping for the new page
  86. * FIXME: needs this MCRR to be supported.
  87. */
  88. __asm__("mcrr p15, 0, %1, %0, c6 @ 0xec401f06"
  89. :
  90. : "r" (kaddr),
  91. "r" ((unsigned long)kaddr + PAGE_SIZE - L1_CACHE_BYTES)
  92. : "cc");
  93. /*
  94. * Now clear the page using the same cache colour as
  95. * the pages ultimate destination.
  96. */
  97. spin_lock(&v6_lock);
  98. set_pte(to_pte + offset, pfn_pte(__pa(kaddr) >> PAGE_SHIFT, to_pgprot));
  99. flush_tlb_kernel_page(to);
  100. clear_page((void *)to);
  101. spin_unlock(&v6_lock);
  102. }
  103. struct cpu_user_fns v6_user_fns __initdata = {
  104. .cpu_clear_user_page = v6_clear_user_page_nonaliasing,
  105. .cpu_copy_user_page = v6_copy_user_page_nonaliasing,
  106. };
  107. static int __init v6_userpage_init(void)
  108. {
  109. if (cache_is_vipt_aliasing()) {
  110. pgd_t *pgd;
  111. pmd_t *pmd;
  112. pgd = pgd_offset_k(from_address);
  113. pmd = pmd_alloc(&init_mm, pgd, from_address);
  114. if (!pmd)
  115. BUG();
  116. from_pte = pte_alloc_kernel(&init_mm, pmd, from_address);
  117. if (!from_pte)
  118. BUG();
  119. to_pte = pte_alloc_kernel(&init_mm, pmd, to_address);
  120. if (!to_pte)
  121. BUG();
  122. cpu_user.cpu_clear_user_page = v6_clear_user_page_aliasing;
  123. cpu_user.cpu_copy_user_page = v6_copy_user_page_aliasing;
  124. }
  125. return 0;
  126. }
  127. __initcall(v6_userpage_init);