/arch/arm/mach-omap/time.c

https://bitbucket.org/evzijst/gittest · C · 384 lines · 211 code · 54 blank · 119 comment · 1 complexity · fea7a357139de8bd65f0bf6fad07a15a MD5 · raw file

  1. /*
  2. * linux/arch/arm/mach-omap/time.c
  3. *
  4. * OMAP Timers
  5. *
  6. * Copyright (C) 2004 Nokia Corporation
  7. * Partial timer rewrite and additional VST timer support by
  8. * Tony Lindgen <tony@atomide.com> and
  9. * Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
  10. *
  11. * MPU timer code based on the older MPU timer code for OMAP
  12. * Copyright (C) 2000 RidgeRun, Inc.
  13. * Author: Greg Lonnon <glonnon@ridgerun.com>
  14. *
  15. * This program is free software; you can redistribute it and/or modify it
  16. * under the terms of the GNU General Public License as published by the
  17. * Free Software Foundation; either version 2 of the License, or (at your
  18. * option) any later version.
  19. *
  20. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30. *
  31. * You should have received a copy of the GNU General Public License along
  32. * with this program; if not, write to the Free Software Foundation, Inc.,
  33. * 675 Mass Ave, Cambridge, MA 02139, USA.
  34. */
  35. #include <linux/config.h>
  36. #include <linux/kernel.h>
  37. #include <linux/init.h>
  38. #include <linux/delay.h>
  39. #include <linux/interrupt.h>
  40. #include <linux/sched.h>
  41. #include <linux/spinlock.h>
  42. #include <asm/system.h>
  43. #include <asm/hardware.h>
  44. #include <asm/io.h>
  45. #include <asm/leds.h>
  46. #include <asm/irq.h>
  47. #include <asm/mach/irq.h>
  48. #include <asm/mach/time.h>
  49. struct sys_timer omap_timer;
  50. #ifdef CONFIG_OMAP_MPU_TIMER
  51. /*
  52. * ---------------------------------------------------------------------------
  53. * MPU timer
  54. * ---------------------------------------------------------------------------
  55. */
  56. #define OMAP_MPU_TIMER1_BASE (0xfffec500)
  57. #define OMAP_MPU_TIMER2_BASE (0xfffec600)
  58. #define OMAP_MPU_TIMER3_BASE (0xfffec700)
  59. #define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
  60. #define OMAP_MPU_TIMER_OFFSET 0x100
  61. #define MPU_TIMER_FREE (1 << 6)
  62. #define MPU_TIMER_CLOCK_ENABLE (1 << 5)
  63. #define MPU_TIMER_AR (1 << 1)
  64. #define MPU_TIMER_ST (1 << 0)
  65. /* cycles to nsec conversions taken from arch/i386/kernel/timers/timer_tsc.c,
  66. * converted to use kHz by Kevin Hilman */
  67. /* convert from cycles(64bits) => nanoseconds (64bits)
  68. * basic equation:
  69. * ns = cycles / (freq / ns_per_sec)
  70. * ns = cycles * (ns_per_sec / freq)
  71. * ns = cycles * (10^9 / (cpu_khz * 10^3))
  72. * ns = cycles * (10^6 / cpu_khz)
  73. *
  74. * Then we use scaling math (suggested by george at mvista.com) to get:
  75. * ns = cycles * (10^6 * SC / cpu_khz / SC
  76. * ns = cycles * cyc2ns_scale / SC
  77. *
  78. * And since SC is a constant power of two, we can convert the div
  79. * into a shift.
  80. * -johnstul at us.ibm.com "math is hard, lets go shopping!"
  81. */
  82. static unsigned long cyc2ns_scale;
  83. #define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
  84. static inline void set_cyc2ns_scale(unsigned long cpu_khz)
  85. {
  86. cyc2ns_scale = (1000000 << CYC2NS_SCALE_FACTOR)/cpu_khz;
  87. }
  88. static inline unsigned long long cycles_2_ns(unsigned long long cyc)
  89. {
  90. return (cyc * cyc2ns_scale) >> CYC2NS_SCALE_FACTOR;
  91. }
  92. /*
  93. * MPU_TICKS_PER_SEC must be an even number, otherwise machinecycles_to_usecs
  94. * will break. On P2, the timer count rate is 6.5 MHz after programming PTV
  95. * with 0. This divides the 13MHz input by 2, and is undocumented.
  96. */
  97. #ifdef CONFIG_MACH_OMAP_PERSEUS2
  98. /* REVISIT: This ifdef construct should be replaced by a query to clock
  99. * framework to see if timer base frequency is 12.0, 13.0 or 19.2 MHz.
  100. */
  101. #define MPU_TICKS_PER_SEC (13000000 / 2)
  102. #else
  103. #define MPU_TICKS_PER_SEC (12000000 / 2)
  104. #endif
  105. #define MPU_TIMER_TICK_PERIOD ((MPU_TICKS_PER_SEC / HZ) - 1)
  106. typedef struct {
  107. u32 cntl; /* CNTL_TIMER, R/W */
  108. u32 load_tim; /* LOAD_TIM, W */
  109. u32 read_tim; /* READ_TIM, R */
  110. } omap_mpu_timer_regs_t;
  111. #define omap_mpu_timer_base(n) \
  112. ((volatile omap_mpu_timer_regs_t*)IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
  113. (n)*OMAP_MPU_TIMER_OFFSET))
  114. static inline unsigned long omap_mpu_timer_read(int nr)
  115. {
  116. volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
  117. return timer->read_tim;
  118. }
  119. static inline void omap_mpu_timer_start(int nr, unsigned long load_val)
  120. {
  121. volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
  122. timer->cntl = MPU_TIMER_CLOCK_ENABLE;
  123. udelay(1);
  124. timer->load_tim = load_val;
  125. udelay(1);
  126. timer->cntl = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_AR | MPU_TIMER_ST);
  127. }
  128. unsigned long omap_mpu_timer_ticks_to_usecs(unsigned long nr_ticks)
  129. {
  130. unsigned long long nsec;
  131. nsec = cycles_2_ns((unsigned long long)nr_ticks);
  132. return (unsigned long)nsec / 1000;
  133. }
  134. /*
  135. * Last processed system timer interrupt
  136. */
  137. static unsigned long omap_mpu_timer_last = 0;
  138. /*
  139. * Returns elapsed usecs since last system timer interrupt
  140. */
  141. static unsigned long omap_mpu_timer_gettimeoffset(void)
  142. {
  143. unsigned long now = 0 - omap_mpu_timer_read(0);
  144. unsigned long elapsed = now - omap_mpu_timer_last;
  145. return omap_mpu_timer_ticks_to_usecs(elapsed);
  146. }
  147. /*
  148. * Elapsed time between interrupts is calculated using timer0.
  149. * Latency during the interrupt is calculated using timer1.
  150. * Both timer0 and timer1 are counting at 6MHz (P2 6.5MHz).
  151. */
  152. static irqreturn_t omap_mpu_timer_interrupt(int irq, void *dev_id,
  153. struct pt_regs *regs)
  154. {
  155. unsigned long now, latency;
  156. write_seqlock(&xtime_lock);
  157. now = 0 - omap_mpu_timer_read(0);
  158. latency = MPU_TICKS_PER_SEC / HZ - omap_mpu_timer_read(1);
  159. omap_mpu_timer_last = now - latency;
  160. timer_tick(regs);
  161. write_sequnlock(&xtime_lock);
  162. return IRQ_HANDLED;
  163. }
  164. static struct irqaction omap_mpu_timer_irq = {
  165. .name = "mpu timer",
  166. .flags = SA_INTERRUPT,
  167. .handler = omap_mpu_timer_interrupt
  168. };
  169. static unsigned long omap_mpu_timer1_overflows;
  170. static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id,
  171. struct pt_regs *regs)
  172. {
  173. omap_mpu_timer1_overflows++;
  174. return IRQ_HANDLED;
  175. }
  176. static struct irqaction omap_mpu_timer1_irq = {
  177. .name = "mpu timer1 overflow",
  178. .flags = SA_INTERRUPT,
  179. .handler = omap_mpu_timer1_interrupt
  180. };
  181. static __init void omap_init_mpu_timer(void)
  182. {
  183. set_cyc2ns_scale(MPU_TICKS_PER_SEC / 1000);
  184. omap_timer.offset = omap_mpu_timer_gettimeoffset;
  185. setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
  186. setup_irq(INT_TIMER2, &omap_mpu_timer_irq);
  187. omap_mpu_timer_start(0, 0xffffffff);
  188. omap_mpu_timer_start(1, MPU_TIMER_TICK_PERIOD);
  189. }
  190. /*
  191. * Scheduler clock - returns current time in nanosec units.
  192. */
  193. unsigned long long sched_clock(void)
  194. {
  195. unsigned long ticks = 0 - omap_mpu_timer_read(0);
  196. unsigned long long ticks64;
  197. ticks64 = omap_mpu_timer1_overflows;
  198. ticks64 <<= 32;
  199. ticks64 |= ticks;
  200. return cycles_2_ns(ticks64);
  201. }
  202. #endif /* CONFIG_OMAP_MPU_TIMER */
  203. #ifdef CONFIG_OMAP_32K_TIMER
  204. #ifdef CONFIG_ARCH_OMAP1510
  205. #error OMAP 32KHz timer does not currently work on 1510!
  206. #endif
  207. /*
  208. * ---------------------------------------------------------------------------
  209. * 32KHz OS timer
  210. *
  211. * This currently works only on 16xx, as 1510 does not have the continuous
  212. * 32KHz synchronous timer. The 32KHz synchronous timer is used to keep track
  213. * of time in addition to the 32KHz OS timer. Using only the 32KHz OS timer
  214. * on 1510 would be possible, but the timer would not be as accurate as
  215. * with the 32KHz synchronized timer.
  216. * ---------------------------------------------------------------------------
  217. */
  218. #define OMAP_32K_TIMER_BASE 0xfffb9000
  219. #define OMAP_32K_TIMER_CR 0x08
  220. #define OMAP_32K_TIMER_TVR 0x00
  221. #define OMAP_32K_TIMER_TCR 0x04
  222. #define OMAP_32K_TICKS_PER_HZ (32768 / HZ)
  223. /*
  224. * TRM says 1 / HZ = ( TVR + 1) / 32768, so TRV = (32768 / HZ) - 1
  225. * so with HZ = 100, TVR = 327.68.
  226. */
  227. #define OMAP_32K_TIMER_TICK_PERIOD ((32768 / HZ) - 1)
  228. #define MAX_SKIP_JIFFIES 25
  229. #define TIMER_32K_SYNCHRONIZED 0xfffbc410
  230. #define JIFFIES_TO_HW_TICKS(nr_jiffies, clock_rate) \
  231. (((nr_jiffies) * (clock_rate)) / HZ)
  232. static inline void omap_32k_timer_write(int val, int reg)
  233. {
  234. omap_writew(val, reg + OMAP_32K_TIMER_BASE);
  235. }
  236. static inline unsigned long omap_32k_timer_read(int reg)
  237. {
  238. return omap_readl(reg + OMAP_32K_TIMER_BASE) & 0xffffff;
  239. }
  240. /*
  241. * The 32KHz synchronized timer is an additional timer on 16xx.
  242. * It is always running.
  243. */
  244. static inline unsigned long omap_32k_sync_timer_read(void)
  245. {
  246. return omap_readl(TIMER_32K_SYNCHRONIZED);
  247. }
  248. static inline void omap_32k_timer_start(unsigned long load_val)
  249. {
  250. omap_32k_timer_write(load_val, OMAP_32K_TIMER_TVR);
  251. omap_32k_timer_write(0x0f, OMAP_32K_TIMER_CR);
  252. }
  253. static inline void omap_32k_timer_stop(void)
  254. {
  255. omap_32k_timer_write(0x0, OMAP_32K_TIMER_CR);
  256. }
  257. /*
  258. * Rounds down to nearest usec
  259. */
  260. static inline unsigned long omap_32k_ticks_to_usecs(unsigned long ticks_32k)
  261. {
  262. return (ticks_32k * 5*5*5*5*5*5) >> 9;
  263. }
  264. static unsigned long omap_32k_last_tick = 0;
  265. /*
  266. * Returns elapsed usecs since last 32k timer interrupt
  267. */
  268. static unsigned long omap_32k_timer_gettimeoffset(void)
  269. {
  270. unsigned long now = omap_32k_sync_timer_read();
  271. return omap_32k_ticks_to_usecs(now - omap_32k_last_tick);
  272. }
  273. /*
  274. * Timer interrupt for 32KHz timer. When dynamic tick is enabled, this
  275. * function is also called from other interrupts to remove latency
  276. * issues with dynamic tick. In the dynamic tick case, we need to lock
  277. * with irqsave.
  278. */
  279. static irqreturn_t omap_32k_timer_interrupt(int irq, void *dev_id,
  280. struct pt_regs *regs)
  281. {
  282. unsigned long flags;
  283. unsigned long now;
  284. write_seqlock_irqsave(&xtime_lock, flags);
  285. now = omap_32k_sync_timer_read();
  286. while (now - omap_32k_last_tick >= OMAP_32K_TICKS_PER_HZ) {
  287. omap_32k_last_tick += OMAP_32K_TICKS_PER_HZ;
  288. timer_tick(regs);
  289. }
  290. /* Restart timer so we don't drift off due to modulo or dynamic tick.
  291. * By default we program the next timer to be continuous to avoid
  292. * latencies during high system load. During dynamic tick operation the
  293. * continuous timer can be overridden from pm_idle to be longer.
  294. */
  295. omap_32k_timer_start(omap_32k_last_tick + OMAP_32K_TICKS_PER_HZ - now);
  296. write_sequnlock_irqrestore(&xtime_lock, flags);
  297. return IRQ_HANDLED;
  298. }
  299. static struct irqaction omap_32k_timer_irq = {
  300. .name = "32KHz timer",
  301. .flags = SA_INTERRUPT,
  302. .handler = omap_32k_timer_interrupt
  303. };
  304. static __init void omap_init_32k_timer(void)
  305. {
  306. setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
  307. omap_timer.offset = omap_32k_timer_gettimeoffset;
  308. omap_32k_last_tick = omap_32k_sync_timer_read();
  309. omap_32k_timer_start(OMAP_32K_TIMER_TICK_PERIOD);
  310. }
  311. #endif /* CONFIG_OMAP_32K_TIMER */
  312. /*
  313. * ---------------------------------------------------------------------------
  314. * Timer initialization
  315. * ---------------------------------------------------------------------------
  316. */
  317. void __init omap_timer_init(void)
  318. {
  319. #if defined(CONFIG_OMAP_MPU_TIMER)
  320. omap_init_mpu_timer();
  321. #elif defined(CONFIG_OMAP_32K_TIMER)
  322. omap_init_32k_timer();
  323. #else
  324. #error No system timer selected in Kconfig!
  325. #endif
  326. }
  327. struct sys_timer omap_timer = {
  328. .init = omap_timer_init,
  329. .offset = NULL, /* Initialized later */
  330. };