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/arch/arm/mach-iop3xx/iop321-setup.c

https://bitbucket.org/evzijst/gittest
C | 169 lines | 133 code | 18 blank | 18 comment | 2 complexity | 5d2dfafdaa08e83d41d28dd114c5c245 MD5 | raw file
  1/*
  2 * linux/arch/arm/mach-iop3xx/iop321-setup.c
  3 *
  4 * Author: Nicolas Pitre <nico@cam.org>
  5 * Copyright (C) 2001 MontaVista Software, Inc.
  6 * Copyright (C) 2004 Intel Corporation.
  7 *
  8 * This program is free software; you can redistribute it and/or modify
  9 * it under the terms of the GNU General Public License version 2 as
 10 * published by the Free Software Foundation.
 11 *
 12 */
 13#include <linux/mm.h>
 14#include <linux/init.h>
 15#include <linux/config.h>
 16#include <linux/init.h>
 17#include <linux/major.h>
 18#include <linux/fs.h>
 19#include <linux/device.h>
 20#include <linux/serial.h>
 21#include <linux/tty.h>
 22#include <linux/serial_core.h>
 23
 24#include <asm/io.h>
 25#include <asm/pgtable.h>
 26#include <asm/page.h>
 27#include <asm/mach/map.h>
 28#include <asm/setup.h>
 29#include <asm/system.h>
 30#include <asm/memory.h>
 31#include <asm/hardware.h>
 32#include <asm/mach-types.h>
 33#include <asm/mach/arch.h>
 34
 35#define IOP321_UART_XTAL 1843200
 36
 37/*
 38 * Standard IO mapping for all IOP321 based systems
 39 */
 40static struct map_desc iop321_std_desc[] __initdata = {
 41 /* virtual     physical      length      type */
 42
 43 /* mem mapped registers */
 44 { IOP321_VIRT_MEM_BASE,  IOP321_PHYS_MEM_BASE,   0x00002000,  MT_DEVICE },
 45
 46 /* PCI IO space */
 47 { IOP321_PCI_LOWER_IO_VA,  IOP321_PCI_LOWER_IO_PA,   IOP321_PCI_IO_WINDOW_SIZE,  MT_DEVICE }
 48};
 49
 50#ifdef CONFIG_ARCH_IQ80321
 51#define UARTBASE IQ80321_UART
 52#define IRQ_UART IRQ_IQ80321_UART
 53#endif
 54
 55#ifdef CONFIG_ARCH_IQ31244
 56#define UARTBASE IQ31244_UART
 57#define IRQ_UART IRQ_IQ31244_UART
 58#endif
 59
 60static struct uart_port iop321_serial_ports[] = {
 61	{
 62		.membase	= (char*)(UARTBASE),
 63		.mapbase	= (UARTBASE),
 64		.irq		= IRQ_UART,
 65		.flags		= UPF_SKIP_TEST,
 66		.iotype		= UPIO_MEM,
 67		.regshift	= 0,
 68		.uartclk	= IOP321_UART_XTAL,
 69		.line		= 0,
 70		.type		= PORT_16550A,
 71		.fifosize	= 16
 72	}
 73};
 74
 75static struct resource iop32x_i2c_0_resources[] = {
 76	[0] = {
 77		.start = 0xfffff680,
 78		.end = 0xfffff698,
 79		.flags = IORESOURCE_MEM,
 80	},
 81	[1] = {
 82		.start = IRQ_IOP321_I2C_0,
 83		.end = IRQ_IOP321_I2C_0,
 84		.flags = IORESOURCE_IRQ
 85	}
 86};
 87
 88static struct resource iop32x_i2c_1_resources[] = {
 89	[0] = {
 90		.start = 0xfffff6a0,
 91		.end = 0xfffff6b8,
 92		.flags = IORESOURCE_MEM,
 93	},
 94	[1] = {
 95		.start = IRQ_IOP321_I2C_1,
 96		.end = IRQ_IOP321_I2C_1,
 97		.flags = IORESOURCE_IRQ
 98	}
 99};
100
101static struct platform_device iop32x_i2c_0_controller = {
102	.name = "IOP3xx-I2C",
103	.id = 0,
104	.num_resources = 2,
105	.resource = iop32x_i2c_0_resources
106};
107
108static struct platform_device iop32x_i2c_1_controller = {
109	.name = "IOP3xx-I2C",
110	.id = 1,
111	.num_resources = 2,
112	.resource = iop32x_i2c_1_resources
113};
114
115static struct platform_device *iop32x_devices[] __initdata = {
116	&iop32x_i2c_0_controller,
117	&iop32x_i2c_1_controller
118};
119
120void __init iop32x_init(void)
121{
122	if(iop_is_321())
123	{
124		platform_add_devices(iop32x_devices,
125				ARRAY_SIZE(iop32x_devices));
126	}
127}
128
129void __init iop321_map_io(void)
130{
131	iotable_init(iop321_std_desc, ARRAY_SIZE(iop321_std_desc));
132	early_serial_setup(&iop321_serial_ports[0]);
133}
134
135#ifdef CONFIG_ARCH_IQ80321
136extern void iq80321_map_io(void);
137extern struct sys_timer iop321_timer;
138extern void iop321_init_time(void);
139#endif
140
141#ifdef CONFIG_ARCH_IQ31244
142extern void iq31244_map_io(void);
143extern struct sys_timer iop321_timer;
144extern void iop321_init_time(void);
145#endif
146
147#if defined(CONFIG_ARCH_IQ80321)
148MACHINE_START(IQ80321, "Intel IQ80321")
149	MAINTAINER("Intel Corporation")
150	BOOT_MEM(PHYS_OFFSET, IQ80321_UART, IQ80321_UART)
151	MAPIO(iq80321_map_io)
152	INITIRQ(iop321_init_irq)
153	.timer		= &iop321_timer,
154    BOOT_PARAMS(0xa0000100)
155	INIT_MACHINE(iop32x_init)
156MACHINE_END
157#elif defined(CONFIG_ARCH_IQ31244)
158MACHINE_START(IQ31244, "Intel IQ31244")
159    MAINTAINER("Intel Corp.")
160    BOOT_MEM(PHYS_OFFSET, IQ31244_UART, IQ31244_UART)
161    MAPIO(iq31244_map_io)
162    INITIRQ(iop321_init_irq)
163	.timer		= &iop321_timer,
164    BOOT_PARAMS(0xa0000100)
165	INIT_MACHINE(iop32x_init)
166MACHINE_END
167#else
168#error No machine descriptor defined for this IOP3XX implementation
169#endif