/arch/arm/boot/compressed/head.S

https://bitbucket.org/evzijst/gittest · Assembly · 786 lines · 547 code · 67 blank · 172 comment · 7 complexity · b6d53ea56fe19d0044ffec56ef66113d MD5 · raw file

  1. /*
  2. * linux/arch/arm/boot/compressed/head.S
  3. *
  4. * Copyright (C) 1996-2002 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/config.h>
  11. #include <linux/linkage.h>
  12. /*
  13. * Debugging stuff
  14. *
  15. * Note that these macros must not contain any code which is not
  16. * 100% relocatable. Any attempt to do so will result in a crash.
  17. * Please select one of the following when turning on debugging.
  18. */
  19. #ifdef DEBUG
  20. #if defined(CONFIG_DEBUG_DC21285_PORT)
  21. .macro loadsp, rb
  22. mov \rb, #0x42000000
  23. .endm
  24. .macro writeb, rb
  25. str \rb, [r3, #0x160]
  26. .endm
  27. #elif defined(CONFIG_DEBUG_ICEDCC)
  28. .macro loadsp, rb
  29. .endm
  30. .macro writeb, rb
  31. mcr p14, 0, \rb, c0, c1, 0
  32. .endm
  33. #elif defined(CONFIG_FOOTBRIDGE)
  34. .macro loadsp, rb
  35. mov \rb, #0x7c000000
  36. .endm
  37. .macro writeb, rb
  38. strb \rb, [r3, #0x3f8]
  39. .endm
  40. #elif defined(CONFIG_ARCH_RPC)
  41. .macro loadsp, rb
  42. mov \rb, #0x03000000
  43. orr \rb, \rb, #0x00010000
  44. .endm
  45. .macro writeb, rb
  46. strb \rb, [r3, #0x3f8 << 2]
  47. .endm
  48. #elif defined(CONFIG_ARCH_INTEGRATOR)
  49. .macro loadsp, rb
  50. mov \rb, #0x16000000
  51. .endm
  52. .macro writeb, rb
  53. strb \rb, [r3, #0]
  54. .endm
  55. #elif defined(CONFIG_ARCH_PXA) /* Xscale-type */
  56. .macro loadsp, rb
  57. mov \rb, #0x40000000
  58. orr \rb, \rb, #0x00100000
  59. .endm
  60. .macro writeb, rb
  61. strb \rb, [r3, #0]
  62. .endm
  63. #elif defined(CONFIG_ARCH_SA1100)
  64. .macro loadsp, rb
  65. mov \rb, #0x80000000 @ physical base address
  66. # if defined(CONFIG_DEBUG_LL_SER3)
  67. add \rb, \rb, #0x00050000 @ Ser3
  68. # else
  69. add \rb, \rb, #0x00010000 @ Ser1
  70. # endif
  71. .endm
  72. .macro writeb, rb
  73. str \rb, [r3, #0x14] @ UTDR
  74. .endm
  75. #elif defined(CONFIG_ARCH_IXP4XX)
  76. .macro loadsp, rb
  77. mov \rb, #0xc8000000
  78. .endm
  79. .macro writeb, rb
  80. str \rb, [r3, #0]
  81. #elif defined(CONFIG_ARCH_IXP2000)
  82. .macro loadsp, rb
  83. mov \rb, #0xc0000000
  84. orr \rb, \rb, #0x00030000
  85. .endm
  86. .macro writeb, rb
  87. str \rb, [r3, #0]
  88. .endm
  89. #elif defined(CONFIG_ARCH_LH7A40X)
  90. .macro loadsp, rb
  91. ldr \rb, =0x80000700 @ UART2 UARTBASE
  92. .endm
  93. .macro writeb, rb
  94. strb \rb, [r3, #0]
  95. .endm
  96. #elif defined(CONFIG_ARCH_OMAP)
  97. .macro loadsp, rb
  98. mov \rb, #0xff000000 @ physical base address
  99. add \rb, \rb, #0x00fb0000
  100. #if defined(CONFIG_OMAP_LL_DEBUG_UART2) || defined(CONFIG_OMAP_LL_DEBUG_UART3)
  101. add \rb, \rb, #0x00000800
  102. #endif
  103. #ifdef CONFIG_OMAP_LL_DEBUG_UART3
  104. add \rb, \rb, #0x00009000
  105. #endif
  106. .endm
  107. .macro writeb, rb
  108. strb \rb, [r3]
  109. .endm
  110. #elif defined(CONFIG_ARCH_IOP331)
  111. .macro loadsp, rb
  112. mov \rb, #0xff000000
  113. orr \rb, \rb, #0x00ff0000
  114. orr \rb, \rb, #0x0000f700 @ location of the UART
  115. .endm
  116. .macro writeb, rb
  117. str \rb, [r3, #0]
  118. .endm
  119. #elif defined(CONFIG_ARCH_S3C2410)
  120. .macro loadsp, rb
  121. mov \rb, #0x50000000
  122. add \rb, \rb, #0x4000 * CONFIG_S3C2410_LOWLEVEL_UART_PORT
  123. .endm
  124. .macro writeb, rb
  125. strb \rb, [r3, #0x20]
  126. .endm
  127. #else
  128. #error no serial architecture defined
  129. #endif
  130. #endif
  131. .macro kputc,val
  132. mov r0, \val
  133. bl putc
  134. .endm
  135. .macro kphex,val,len
  136. mov r0, \val
  137. mov r1, #\len
  138. bl phex
  139. .endm
  140. .macro debug_reloc_start
  141. #ifdef DEBUG
  142. kputc #'\n'
  143. kphex r6, 8 /* processor id */
  144. kputc #':'
  145. kphex r7, 8 /* architecture id */
  146. kputc #':'
  147. mrc p15, 0, r0, c1, c0
  148. kphex r0, 8 /* control reg */
  149. kputc #'\n'
  150. kphex r5, 8 /* decompressed kernel start */
  151. kputc #'-'
  152. kphex r8, 8 /* decompressed kernel end */
  153. kputc #'>'
  154. kphex r4, 8 /* kernel execution address */
  155. kputc #'\n'
  156. #endif
  157. .endm
  158. .macro debug_reloc_end
  159. #ifdef DEBUG
  160. kphex r5, 8 /* end of kernel */
  161. kputc #'\n'
  162. mov r0, r4
  163. bl memdump /* dump 256 bytes at start of kernel */
  164. #endif
  165. .endm
  166. .section ".start", #alloc, #execinstr
  167. /*
  168. * sort out different calling conventions
  169. */
  170. .align
  171. start:
  172. .type start,#function
  173. .rept 8
  174. mov r0, r0
  175. .endr
  176. b 1f
  177. .word 0x016f2818 @ Magic numbers to help the loader
  178. .word start @ absolute load/run zImage address
  179. .word _edata @ zImage end address
  180. 1: mov r7, r1 @ save architecture ID
  181. mov r8, #0 @ save r0
  182. #ifndef __ARM_ARCH_2__
  183. /*
  184. * Booting from Angel - need to enter SVC mode and disable
  185. * FIQs/IRQs (numeric definitions from angel arm.h source).
  186. * We only do this if we were in user mode on entry.
  187. */
  188. mrs r2, cpsr @ get current mode
  189. tst r2, #3 @ not user?
  190. bne not_angel
  191. mov r0, #0x17 @ angel_SWIreason_EnterSVC
  192. swi 0x123456 @ angel_SWI_ARM
  193. not_angel:
  194. mrs r2, cpsr @ turn off interrupts to
  195. orr r2, r2, #0xc0 @ prevent angel from running
  196. msr cpsr_c, r2
  197. #else
  198. teqp pc, #0x0c000003 @ turn off interrupts
  199. #endif
  200. /*
  201. * Note that some cache flushing and other stuff may
  202. * be needed here - is there an Angel SWI call for this?
  203. */
  204. /*
  205. * some architecture specific code can be inserted
  206. * by the linker here, but it should preserve r7 and r8.
  207. */
  208. .text
  209. adr r0, LC0
  210. ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
  211. subs r0, r0, r1 @ calculate the delta offset
  212. @ if delta is zero, we are
  213. beq not_relocated @ running at the address we
  214. @ were linked at.
  215. /*
  216. * We're running at a different address. We need to fix
  217. * up various pointers:
  218. * r5 - zImage base address
  219. * r6 - GOT start
  220. * ip - GOT end
  221. */
  222. add r5, r5, r0
  223. add r6, r6, r0
  224. add ip, ip, r0
  225. #ifndef CONFIG_ZBOOT_ROM
  226. /*
  227. * If we're running fully PIC === CONFIG_ZBOOT_ROM = n,
  228. * we need to fix up pointers into the BSS region.
  229. * r2 - BSS start
  230. * r3 - BSS end
  231. * sp - stack pointer
  232. */
  233. add r2, r2, r0
  234. add r3, r3, r0
  235. add sp, sp, r0
  236. /*
  237. * Relocate all entries in the GOT table.
  238. */
  239. 1: ldr r1, [r6, #0] @ relocate entries in the GOT
  240. add r1, r1, r0 @ table. This fixes up the
  241. str r1, [r6], #4 @ C references.
  242. cmp r6, ip
  243. blo 1b
  244. #else
  245. /*
  246. * Relocate entries in the GOT table. We only relocate
  247. * the entries that are outside the (relocated) BSS region.
  248. */
  249. 1: ldr r1, [r6, #0] @ relocate entries in the GOT
  250. cmp r1, r2 @ entry < bss_start ||
  251. cmphs r3, r1 @ _end < entry
  252. addlo r1, r1, r0 @ table. This fixes up the
  253. str r1, [r6], #4 @ C references.
  254. cmp r6, ip
  255. blo 1b
  256. #endif
  257. not_relocated: mov r0, #0
  258. 1: str r0, [r2], #4 @ clear bss
  259. str r0, [r2], #4
  260. str r0, [r2], #4
  261. str r0, [r2], #4
  262. cmp r2, r3
  263. blo 1b
  264. /*
  265. * The C runtime environment should now be setup
  266. * sufficiently. Turn the cache on, set up some
  267. * pointers, and start decompressing.
  268. */
  269. bl cache_on
  270. mov r1, sp @ malloc space above stack
  271. add r2, sp, #0x10000 @ 64k max
  272. /*
  273. * Check to see if we will overwrite ourselves.
  274. * r4 = final kernel address
  275. * r5 = start of this image
  276. * r2 = end of malloc space (and therefore this image)
  277. * We basically want:
  278. * r4 >= r2 -> OK
  279. * r4 + image length <= r5 -> OK
  280. */
  281. cmp r4, r2
  282. bhs wont_overwrite
  283. add r0, r4, #4096*1024 @ 4MB largest kernel size
  284. cmp r0, r5
  285. bls wont_overwrite
  286. mov r5, r2 @ decompress after malloc space
  287. mov r0, r5
  288. mov r3, r7
  289. bl decompress_kernel
  290. add r0, r0, #127
  291. bic r0, r0, #127 @ align the kernel length
  292. /*
  293. * r0 = decompressed kernel length
  294. * r1-r3 = unused
  295. * r4 = kernel execution address
  296. * r5 = decompressed kernel start
  297. * r6 = processor ID
  298. * r7 = architecture ID
  299. * r8-r14 = unused
  300. */
  301. add r1, r5, r0 @ end of decompressed kernel
  302. adr r2, reloc_start
  303. ldr r3, LC1
  304. add r3, r2, r3
  305. 1: ldmia r2!, {r8 - r13} @ copy relocation code
  306. stmia r1!, {r8 - r13}
  307. ldmia r2!, {r8 - r13}
  308. stmia r1!, {r8 - r13}
  309. cmp r2, r3
  310. blo 1b
  311. bl cache_clean_flush
  312. add pc, r5, r0 @ call relocation code
  313. /*
  314. * We're not in danger of overwriting ourselves. Do this the simple way.
  315. *
  316. * r4 = kernel execution address
  317. * r7 = architecture ID
  318. */
  319. wont_overwrite: mov r0, r4
  320. mov r3, r7
  321. bl decompress_kernel
  322. b call_kernel
  323. .type LC0, #object
  324. LC0: .word LC0 @ r1
  325. .word __bss_start @ r2
  326. .word _end @ r3
  327. .word zreladdr @ r4
  328. .word _start @ r5
  329. .word _got_start @ r6
  330. .word _got_end @ ip
  331. .word user_stack+4096 @ sp
  332. LC1: .word reloc_end - reloc_start
  333. .size LC0, . - LC0
  334. #ifdef CONFIG_ARCH_RPC
  335. .globl params
  336. params: ldr r0, =params_phys
  337. mov pc, lr
  338. .ltorg
  339. .align
  340. #endif
  341. /*
  342. * Turn on the cache. We need to setup some page tables so that we
  343. * can have both the I and D caches on.
  344. *
  345. * We place the page tables 16k down from the kernel execution address,
  346. * and we hope that nothing else is using it. If we're using it, we
  347. * will go pop!
  348. *
  349. * On entry,
  350. * r4 = kernel execution address
  351. * r6 = processor ID
  352. * r7 = architecture number
  353. * r8 = run-time address of "start"
  354. * On exit,
  355. * r1, r2, r3, r8, r9, r12 corrupted
  356. * This routine must preserve:
  357. * r4, r5, r6, r7
  358. */
  359. .align 5
  360. cache_on: mov r3, #8 @ cache_on function
  361. b call_cache_fn
  362. __setup_mmu: sub r3, r4, #16384 @ Page directory size
  363. bic r3, r3, #0xff @ Align the pointer
  364. bic r3, r3, #0x3f00
  365. /*
  366. * Initialise the page tables, turning on the cacheable and bufferable
  367. * bits for the RAM area only.
  368. */
  369. mov r0, r3
  370. mov r8, r0, lsr #18
  371. mov r8, r8, lsl #18 @ start of RAM
  372. add r9, r8, #0x10000000 @ a reasonable RAM size
  373. mov r1, #0x12
  374. orr r1, r1, #3 << 10
  375. add r2, r3, #16384
  376. 1: cmp r1, r8 @ if virt > start of RAM
  377. orrhs r1, r1, #0x0c @ set cacheable, bufferable
  378. cmp r1, r9 @ if virt > end of RAM
  379. bichs r1, r1, #0x0c @ clear cacheable, bufferable
  380. str r1, [r0], #4 @ 1:1 mapping
  381. add r1, r1, #1048576
  382. teq r0, r2
  383. bne 1b
  384. /*
  385. * If ever we are running from Flash, then we surely want the cache
  386. * to be enabled also for our execution instance... We map 2MB of it
  387. * so there is no map overlap problem for up to 1 MB compressed kernel.
  388. * If the execution is in RAM then we would only be duplicating the above.
  389. */
  390. mov r1, #0x1e
  391. orr r1, r1, #3 << 10
  392. mov r2, pc, lsr #20
  393. orr r1, r1, r2, lsl #20
  394. add r0, r3, r2, lsl #2
  395. str r1, [r0], #4
  396. add r1, r1, #1048576
  397. str r1, [r0]
  398. mov pc, lr
  399. __armv4_cache_on:
  400. mov r12, lr
  401. bl __setup_mmu
  402. mov r0, #0
  403. mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
  404. mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
  405. mrc p15, 0, r0, c1, c0, 0 @ read control reg
  406. orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement
  407. orr r0, r0, #0x0030
  408. bl __common_cache_on
  409. mov r0, #0
  410. mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
  411. mov pc, r12
  412. __arm6_cache_on:
  413. mov r12, lr
  414. bl __setup_mmu
  415. mov r0, #0
  416. mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
  417. mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
  418. mov r0, #0x30
  419. bl __common_cache_on
  420. mov r0, #0
  421. mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
  422. mov pc, r12
  423. __common_cache_on:
  424. #ifndef DEBUG
  425. orr r0, r0, #0x000d @ Write buffer, mmu
  426. #endif
  427. mov r1, #-1
  428. mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
  429. mcr p15, 0, r1, c3, c0, 0 @ load domain access control
  430. mcr p15, 0, r0, c1, c0, 0 @ load control register
  431. mov pc, lr
  432. /*
  433. * All code following this line is relocatable. It is relocated by
  434. * the above code to the end of the decompressed kernel image and
  435. * executed there. During this time, we have no stacks.
  436. *
  437. * r0 = decompressed kernel length
  438. * r1-r3 = unused
  439. * r4 = kernel execution address
  440. * r5 = decompressed kernel start
  441. * r6 = processor ID
  442. * r7 = architecture ID
  443. * r8-r14 = unused
  444. */
  445. .align 5
  446. reloc_start: add r8, r5, r0
  447. debug_reloc_start
  448. mov r1, r4
  449. 1:
  450. .rept 4
  451. ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
  452. stmia r1!, {r0, r2, r3, r9 - r13}
  453. .endr
  454. cmp r5, r8
  455. blo 1b
  456. debug_reloc_end
  457. call_kernel: bl cache_clean_flush
  458. bl cache_off
  459. mov r0, #0
  460. mov r1, r7 @ restore architecture number
  461. mov pc, r4 @ call kernel
  462. /*
  463. * Here follow the relocatable cache support functions for the
  464. * various processors. This is a generic hook for locating an
  465. * entry and jumping to an instruction at the specified offset
  466. * from the start of the block. Please note this is all position
  467. * independent code.
  468. *
  469. * r1 = corrupted
  470. * r2 = corrupted
  471. * r3 = block offset
  472. * r6 = corrupted
  473. * r12 = corrupted
  474. */
  475. call_cache_fn: adr r12, proc_types
  476. mrc p15, 0, r6, c0, c0 @ get processor ID
  477. 1: ldr r1, [r12, #0] @ get value
  478. ldr r2, [r12, #4] @ get mask
  479. eor r1, r1, r6 @ (real ^ match)
  480. tst r1, r2 @ & mask
  481. addeq pc, r12, r3 @ call cache function
  482. add r12, r12, #4*5
  483. b 1b
  484. /*
  485. * Table for cache operations. This is basically:
  486. * - CPU ID match
  487. * - CPU ID mask
  488. * - 'cache on' method instruction
  489. * - 'cache off' method instruction
  490. * - 'cache flush' method instruction
  491. *
  492. * We match an entry using: ((real_id ^ match) & mask) == 0
  493. *
  494. * Writethrough caches generally only need 'on' and 'off'
  495. * methods. Writeback caches _must_ have the flush method
  496. * defined.
  497. */
  498. .type proc_types,#object
  499. proc_types:
  500. .word 0x41560600 @ ARM6/610
  501. .word 0xffffffe0
  502. b __arm6_cache_off @ works, but slow
  503. b __arm6_cache_off
  504. mov pc, lr
  505. @ b __arm6_cache_on @ untested
  506. @ b __arm6_cache_off
  507. @ b __armv3_cache_flush
  508. .word 0x00000000 @ old ARM ID
  509. .word 0x0000f000
  510. mov pc, lr
  511. mov pc, lr
  512. mov pc, lr
  513. .word 0x41007000 @ ARM7/710
  514. .word 0xfff8fe00
  515. b __arm7_cache_off
  516. b __arm7_cache_off
  517. mov pc, lr
  518. .word 0x41807200 @ ARM720T (writethrough)
  519. .word 0xffffff00
  520. b __armv4_cache_on
  521. b __armv4_cache_off
  522. mov pc, lr
  523. .word 0x00007000 @ ARM7 IDs
  524. .word 0x0000f000
  525. mov pc, lr
  526. mov pc, lr
  527. mov pc, lr
  528. @ Everything from here on will be the new ID system.
  529. .word 0x4401a100 @ sa110 / sa1100
  530. .word 0xffffffe0
  531. b __armv4_cache_on
  532. b __armv4_cache_off
  533. b __armv4_cache_flush
  534. .word 0x6901b110 @ sa1110
  535. .word 0xfffffff0
  536. b __armv4_cache_on
  537. b __armv4_cache_off
  538. b __armv4_cache_flush
  539. @ These match on the architecture ID
  540. .word 0x00020000 @ ARMv4T
  541. .word 0x000f0000
  542. b __armv4_cache_on
  543. b __armv4_cache_off
  544. b __armv4_cache_flush
  545. .word 0x00050000 @ ARMv5TE
  546. .word 0x000f0000
  547. b __armv4_cache_on
  548. b __armv4_cache_off
  549. b __armv4_cache_flush
  550. .word 0x00060000 @ ARMv5TEJ
  551. .word 0x000f0000
  552. b __armv4_cache_on
  553. b __armv4_cache_off
  554. b __armv4_cache_flush
  555. .word 0x00070000 @ ARMv6
  556. .word 0x000f0000
  557. b __armv4_cache_on
  558. b __armv4_cache_off
  559. b __armv6_cache_flush
  560. .word 0 @ unrecognised type
  561. .word 0
  562. mov pc, lr
  563. mov pc, lr
  564. mov pc, lr
  565. .size proc_types, . - proc_types
  566. /*
  567. * Turn off the Cache and MMU. ARMv3 does not support
  568. * reading the control register, but ARMv4 does.
  569. *
  570. * On entry, r6 = processor ID
  571. * On exit, r0, r1, r2, r3, r12 corrupted
  572. * This routine must preserve: r4, r6, r7
  573. */
  574. .align 5
  575. cache_off: mov r3, #12 @ cache_off function
  576. b call_cache_fn
  577. __armv4_cache_off:
  578. mrc p15, 0, r0, c1, c0
  579. bic r0, r0, #0x000d
  580. mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
  581. mov r0, #0
  582. mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
  583. mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
  584. mov pc, lr
  585. __arm6_cache_off:
  586. mov r0, #0x00000030 @ ARM6 control reg.
  587. b __armv3_cache_off
  588. __arm7_cache_off:
  589. mov r0, #0x00000070 @ ARM7 control reg.
  590. b __armv3_cache_off
  591. __armv3_cache_off:
  592. mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
  593. mov r0, #0
  594. mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
  595. mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
  596. mov pc, lr
  597. /*
  598. * Clean and flush the cache to maintain consistency.
  599. *
  600. * On entry,
  601. * r6 = processor ID
  602. * On exit,
  603. * r1, r2, r3, r11, r12 corrupted
  604. * This routine must preserve:
  605. * r0, r4, r5, r6, r7
  606. */
  607. .align 5
  608. cache_clean_flush:
  609. mov r3, #16
  610. b call_cache_fn
  611. __armv6_cache_flush:
  612. mov r1, #0
  613. mcr p15, 0, r1, c7, c14, 0 @ clean+invalidate D
  614. mcr p15, 0, r1, c7, c5, 0 @ invalidate I+BTB
  615. mcr p15, 0, r1, c7, c15, 0 @ clean+invalidate unified
  616. mcr p15, 0, r1, c7, c10, 4 @ drain WB
  617. mov pc, lr
  618. __armv4_cache_flush:
  619. mov r2, #64*1024 @ default: 32K dcache size (*2)
  620. mov r11, #32 @ default: 32 byte line size
  621. mrc p15, 0, r3, c0, c0, 1 @ read cache type
  622. teq r3, r6 @ cache ID register present?
  623. beq no_cache_id
  624. mov r1, r3, lsr #18
  625. and r1, r1, #7
  626. mov r2, #1024
  627. mov r2, r2, lsl r1 @ base dcache size *2
  628. tst r3, #1 << 14 @ test M bit
  629. addne r2, r2, r2, lsr #1 @ +1/2 size if M == 1
  630. mov r3, r3, lsr #12
  631. and r3, r3, #3
  632. mov r11, #8
  633. mov r11, r11, lsl r3 @ cache line size in bytes
  634. no_cache_id:
  635. bic r1, pc, #63 @ align to longest cache line
  636. add r2, r1, r2
  637. 1: ldr r3, [r1], r11 @ s/w flush D cache
  638. teq r1, r2
  639. bne 1b
  640. mcr p15, 0, r1, c7, c5, 0 @ flush I cache
  641. mcr p15, 0, r1, c7, c6, 0 @ flush D cache
  642. mcr p15, 0, r1, c7, c10, 4 @ drain WB
  643. mov pc, lr
  644. __armv3_cache_flush:
  645. mov r1, #0
  646. mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
  647. mov pc, lr
  648. /*
  649. * Various debugging routines for printing hex characters and
  650. * memory, which again must be relocatable.
  651. */
  652. #ifdef DEBUG
  653. .type phexbuf,#object
  654. phexbuf: .space 12
  655. .size phexbuf, . - phexbuf
  656. phex: adr r3, phexbuf
  657. mov r2, #0
  658. strb r2, [r3, r1]
  659. 1: subs r1, r1, #1
  660. movmi r0, r3
  661. bmi puts
  662. and r2, r0, #15
  663. mov r0, r0, lsr #4
  664. cmp r2, #10
  665. addge r2, r2, #7
  666. add r2, r2, #'0'
  667. strb r2, [r3, r1]
  668. b 1b
  669. puts: loadsp r3
  670. 1: ldrb r2, [r0], #1
  671. teq r2, #0
  672. moveq pc, lr
  673. 2: writeb r2
  674. mov r1, #0x00020000
  675. 3: subs r1, r1, #1
  676. bne 3b
  677. teq r2, #'\n'
  678. moveq r2, #'\r'
  679. beq 2b
  680. teq r0, #0
  681. bne 1b
  682. mov pc, lr
  683. putc:
  684. mov r2, r0
  685. mov r0, #0
  686. loadsp r3
  687. b 2b
  688. memdump: mov r12, r0
  689. mov r10, lr
  690. mov r11, #0
  691. 2: mov r0, r11, lsl #2
  692. add r0, r0, r12
  693. mov r1, #8
  694. bl phex
  695. mov r0, #':'
  696. bl putc
  697. 1: mov r0, #' '
  698. bl putc
  699. ldr r0, [r12, r11, lsl #2]
  700. mov r1, #8
  701. bl phex
  702. and r0, r11, #7
  703. teq r0, #3
  704. moveq r0, #' '
  705. bleq putc
  706. and r0, r11, #7
  707. add r11, r11, #1
  708. teq r0, #7
  709. bne 1b
  710. mov r0, #'\n'
  711. bl putc
  712. cmp r11, #64
  713. blt 2b
  714. mov pc, r10
  715. #endif
  716. reloc_end:
  717. .align
  718. .section ".stack", "w"
  719. user_stack: .space 4096