PageRenderTime 57ms CodeModel.GetById 28ms RepoModel.GetById 1ms app.codeStats 0ms

/nuttx/configs/stm3210e-eval/src/up_selectsram.c

https://github.com/l--putt/nuttx-bb
C | 145 lines | 28 code | 31 blank | 86 comment | 0 complexity | a47397e9a8ebe63bf0ef2d53ec76214b MD5 | raw file
  1. /************************************************************************************
  2. * configs/stm3210e-eval/src/up_selectsram.c
  3. * arch/arm/src/board/up_selectsram.c
  4. *
  5. * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
  6. * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
  7. *
  8. * Redistribution and use in source and binary forms, with or without
  9. * modification, are permitted provided that the following conditions
  10. * are met:
  11. *
  12. * 1. Redistributions of source code must retain the above copyright
  13. * notice, this list of conditions and the following disclaimer.
  14. * 2. Redistributions in binary form must reproduce the above copyright
  15. * notice, this list of conditions and the following disclaimer in
  16. * the documentation and/or other materials provided with the
  17. * distribution.
  18. * 3. Neither the name NuttX nor the names of its contributors may be
  19. * used to endorse or promote products derived from this software
  20. * without specific prior written permission.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  23. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  24. * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  25. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  26. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  27. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  28. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
  29. * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
  30. * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  31. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  32. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  33. * POSSIBILITY OF SUCH DAMAGE.
  34. *
  35. ************************************************************************************/
  36. /************************************************************************************
  37. * Included Files
  38. ************************************************************************************/
  39. #include <nuttx/config.h>
  40. #include <stdint.h>
  41. #include <debug.h>
  42. #include "chip.h"
  43. #include "up_arch.h"
  44. #include "stm32.h"
  45. #include "stm3210e-internal.h"
  46. #ifdef CONFIG_STM32_FSMC
  47. /************************************************************************************
  48. * Pre-processor Definitions
  49. ************************************************************************************/
  50. #if STM32_NGPIO_PORTS < 6
  51. # error "Required GPIO ports not enabled"
  52. #endif
  53. /************************************************************************************
  54. * Public Data
  55. ************************************************************************************/
  56. /************************************************************************************
  57. * Private Data
  58. ************************************************************************************/
  59. /* 512Kx16 SRAM is connected to bank2 of the FSMC interface and both 8- and 16-bit
  60. * accesses are allowed by BLN0 and BLN1 connected to BLE and BHE of SRAM,
  61. * respectively.
  62. *
  63. * Pin Usage (per schematic)
  64. * FLASH SRAM NAND
  65. * D[0..15] [0..15] [0..15] [0..7]
  66. * A[0..23] [0..22] [0..18] [16,17]
  67. * PSMC_NE3 PG10 OUT ~CE --- ---
  68. * PSMC_NBL0 PE0 OUT ~BLE --- ---
  69. * PSMC_NBL1 PE1 OUT ~BHE --- ---
  70. * PSMC_NE2 PG9 OUT --- ~E ---
  71. * PSMC_NWE PD5 OUT ~WE ~W ~W
  72. * PSMC_NOE PD4 OUT ~OE ~G ~R
  73. * PSMC_NWAIT PD6 IN --- R~B ---
  74. * PSMC_INT2 PG6* IN --- --- R~B
  75. *
  76. * *JP7 will switch to PD6
  77. */
  78. /* GPIO configurations unique to SRAM */
  79. static const uint16_t g_sramconfig[] =
  80. {
  81. /* NE3, NBL0, NBL1, */
  82. GPIO_NPS_NE3, GPIO_NPS_NBL0, GPIO_NPS_NBL1
  83. };
  84. #define NSRAM_CONFIG (sizeof(g_sramconfig)/sizeof(uint16_t))
  85. /************************************************************************************
  86. * Private Functions
  87. ************************************************************************************/
  88. /************************************************************************************
  89. * Public Functions
  90. ************************************************************************************/
  91. /************************************************************************************
  92. * Name: stm32_selectsram
  93. *
  94. * Description:
  95. * Initialize to access external SRAM
  96. *
  97. ************************************************************************************/
  98. void stm32_selectsram(void)
  99. {
  100. /* Configure new GPIO state */
  101. stm32_extmemgpios(g_commonconfig, NCOMMON_CONFIG);
  102. stm32_extmemgpios(g_sramconfig, NSRAM_CONFIG);
  103. /* Enable AHB clocking to the FSMC */
  104. stm32_enablefsmc();
  105. /* Bank1 NOR/SRAM control register configuration */
  106. putreg32(FSMC_BCR_MWID16|FSMC_BCR_WREN, STM32_FSMC_BCR3);
  107. /* Bank1 NOR/SRAM timing register configuration */
  108. putreg32(FSMC_BTR_ADDSET(1)|FSMC_BTR_ADDHLD(1)|FSMC_BTR_DATAST(3)|FSMC_BTR_BUSTRUN(1)|
  109. FSMC_BTR_CLKDIV(1)|FSMC_BTR_DATLAT(2)|FSMC_BTR_ACCMODA, STM32_FSMC_BTR3);
  110. putreg32(0xffffffff, STM32_FSMC_BCR3);
  111. /* Enable the bank */
  112. putreg32(FSMC_BCR_MBKEN|FSMC_BCR_MWID16|FSMC_BCR_WREN, STM32_FSMC_BCR3);
  113. }
  114. #endif /* CONFIG_STM32_FSMC */