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/efe/src/efe.h

https://bitbucket.org/0xffea/driver-gate
C++ Header | 458 lines | 350 code | 61 blank | 47 comment | 0 complexity | 25194e03e38de7725189f62460f93a88 MD5 | raw file
  1/*
  2 * Copyright (c) 2010 Steven Stallion.  All rights reserved.
  3 *
  4 * Redistribution and use in source and binary forms, with or without
  5 * modification, are permitted provided that the following conditions are
  6 * met:
  7 *
  8 *     1. Redistributions of source code must retain the above copyright
  9 *        notice, this list of conditions and the following disclaimer.
 10 *     2. Redistributions in binary form must reproduce the above
 11 *        copyright notice, this list of conditions and the following
 12 *        disclaimer in the documentation and/or other materials provided
 13 *        with the distribution.
 14 *     3. Neither the name of the copyright owner nor the names of any
 15 *        contributors may be used to endorse or promote products derived
 16 *        from this software without specific prior written permission.
 17 *
 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS "AS IS" AND
 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
 21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
 22 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
 23 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 24 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
 25 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 26 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 27 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 29 */
 30
 31#ifndef	_EFE_H
 32#define	_EFE_H
 33
 34#ifdef	__cplusplus
 35extern "C" {
 36#endif
 37
 38#define	VENDOR_ID		0x10B8
 39#define	DEVICE_ID		0x0005
 40
 41#define	RESET_DELAY		1
 42#define	RESET_TEST_CYCLES	16
 43
 44#define	STOP_DELAY		10
 45#define	STOP_DELAY_CYCLES	160
 46
 47#define	MII_DELAY		1
 48#define	MII_DELAY_CYCLES	16
 49
 50#define	EEPROM_DELAY		3
 51#define	EEPROM_WORDSZ		16
 52
 53#define	AT93C46_ADDRLEN		6
 54#define	AT93C56_ADDRLEN		8
 55
 56#define	FLAG_RUNNING		(1UL << 0)
 57#define	FLAG_SUSPENDED		(1UL << 1)
 58
 59#define	MCHASHL			64
 60#define	MCHASHSZ		16
 61
 62#define	BURSTLEN		0x3F
 63
 64#define	RXDESCL			128
 65#define	TXDESCL			128
 66
 67#define	BUFSZ			1536
 68
 69/*
 70 * Control/Status registers.
 71 */
 72#define	CSR_COMMAND	0x00	/* Control Register */
 73#define	CSR_INTSTAT	0x04	/* Interrupt Status Register */
 74#define	CSR_INTMASK	0x08	/* Interrupt Mask Register */
 75#define	CSR_GENCTL	0x0C	/* General Control Register */
 76#define	CSR_NVCTL	0x10	/* Non-volatile Control Register */
 77#define	CSR_EECTL	0x14	/* EEPROM Control Register */
 78#define	CSR_PBLCNT	0x18	/* Programmable Burst Length Counter */
 79#define	CSR_TEST	0x1C	/* Test Register */
 80#define	CSR_CRCCNT	0x20	/* CRC Error Counter */
 81#define	CSR_ALICNT	0x24	/* Frame Alignment Error Counter */
 82#define	CSR_MPCNT	0x28	/* Missed Packet Counter */
 83#define	CSR_RXFIFO	0x2C	/* Receive FIFO Contents */
 84#define	CSR_MMCTL	0x30	/* MII Control Register */
 85#define	CSR_MMDATA	0x34	/* MII Interface Register */
 86#define	CSR_MMCFG	0x38	/* MII Configuration Register */
 87#define	CSR_IPG		0x3C	/* Interpacket Gap Register */
 88#define	CSR_LAN0	0x40	/* LAN Address Register 0 */
 89#define	CSR_LAN1	0x44	/* LAN Address Register 1 */
 90#define	CSR_LAN2	0x48	/* LAN Address Register 2 */
 91#define	CSR_IDCHK	0x4C	/* Board ID/Checksum Register */
 92#define	CSR_MC0		0x50	/* Multicast Address Register 0 */
 93#define	CSR_MC1		0x54	/* Multicast Address Register 1 */
 94#define	CSR_MC2		0x58	/* Multicast Address Register 2 */
 95#define	CSR_MC3		0x5C	/* Multicast Address Register 3 */
 96#define	CSR_RXCON	0x60	/* Receive Control Register */
 97#define	CSR_RXSTAT	0x64	/* Receive Status Register */
 98#define	CSR_RXCNT	0x68	/* Receive Byte Count */
 99#define	CSR_RXTEST	0x6C	/* Receive Test */
100#define	CSR_TXCON	0x70	/* Transmit Control Register */
101#define	CSR_TXSTAT	0x74	/* Transmit Status Register */
102#define	CSR_TDPAR	0x78	/* Transmit Packet Address */
103#define	CSR_TXTEST	0x7C	/* Transmit Test */
104#define	CSR_PRFDAR	0x80	/* PCI Receive First Descriptor Address */
105#define	CSR_PRCDAR	0x84	/* PCI Receive Current Descriptor Address */
106#define	CSR_PRHDAR	0x88	/* PCI Receive Host Data Address */
107#define	CSR_PRFLAR	0x8C	/* PCI Receive Fragment List Address */
108#define	CSR_PRDLGTH	0x90	/* PCI Receive DMA Length/Control */
109#define	CSR_PRFCNT	0x94	/* PCI Receive Fragment Count */
110#define	CSR_PRLCAR	0x98	/* PCI Receive RAM Current Address */
111#define	CSR_PRLPAR	0x9C	/* PCI Receive RAM Packet Address */
112#define	CSR_PREFAR	0xA0	/* PCI Receive End of Frame Address */
113#define	CSR_PRSTAT	0xA4	/* PCI Receive DMA Status Register */
114#define	CSR_PRBUF	0xA8	/* Receive RAM Buffer */
115#define	CSR_RDNCAR	0xAC	/* Receive MTU Current Address */
116#define	CSR_PRCPTHR	0xB0	/* PCI Receive Copy Threshold Register */
117#define	CSR_ROMDATA	0xB4	/* ROMDATA */
118#define	CSR_PREEMPR	0xBC	/* Preemptive Interrupt */
119#define	CSR_PTFDAR	0xC0	/* PCI Transmit First Descriptor Address */
120#define	CSR_PTCDAR	0xC4	/* PCI Transmit Current Descriptor Address */
121#define	CSR_PTHDAR	0xC8	/* PCI Transmit Host Data Address */
122#define	CSR_PTFLAR	0xCC	/* PCI Transmit Fragment List Address */
123#define	CSR_PTDLGTH	0xD0	/* PCI Transmit DMA Length/Control */
124#define	CSR_PTFCNT	0xD4	/* PCI Transmit Fragment Count */
125#define	CSR_PTLCAR	0xD8	/* PCI Transmit RAM Current Address */
126#define	CSR_ETXTHR	0xDC	/* PCI Early Transmit Threshold Register */
127#define	CSR_PTETXC	0xE0	/* PCI Early Transmit Count */
128#define	CSR_PTSTAT	0xE4	/* PCI Transmit DMA Status */
129#define	CSR_PTBUF	0xE8	/* Transmit RAM Buffer */
130#define	CSR_PTFDAR2	0xEC	/* PCI Transmit 2 First Descriptor Address */
131#define	CSR_FEVTR	0xF0	/* CardBus (UNUSED) */
132#define	CSR_FEVTRMSKR	0xF4	/* CardBus (UNUSED) */
133#define	CSR_FPRSTSTR	0xF8	/* CardBus (UNUSED) */
134#define	CSR_FFRCEVTR	0xFF	/* CardBus (UNUSED) */
135
136/*
137 * Register fields.
138 */
139#define	COMMAND_STOP_RX		(1UL << 0)	/* Stop Receiver */
140#define	COMMAND_START_RX	(1UL << 1)	/* Start Receiver */
141#define	COMMAND_TXQUEUED	(1UL << 2)	/* Queue TX Descriptor */
142#define	COMMAND_RXQUEUED	(1UL << 3)	/* Queue RX Descriptor */
143#define	COMMAND_NEXTFRAME	(1UL << 4)	/* Release RX Frame */
144#define	COMMAND_STOP_TDMA	(1UL << 5)	/* Stop TX DMA */
145#define	COMMAND_STOP_RDMA	(1UL << 6)	/* Stop RX DMA */
146#define	COMMAND_TXUGO		(1UL << 7)	/* Restart Transmission */
147
148#define	INTSTAT_RCC	(1UL << 0)	/* Receive Copy Complete */
149#define	INTSTAT_HCC	(1UL << 1)	/* Header Copy Complete */
150#define	INTSTAT_RQE	(1UL << 2)	/* Receive Queue Empty */
151#define	INTSTAT_OVW	(1UL << 3)	/* Receive Overflow */
152#define	INTSTAT_RXE	(1UL << 4)	/* Receive Error */
153#define	INTSTAT_TXC	(1UL << 5)	/* Transmit Complete */
154#define	INTSTAT_TCC	(1UL << 6)	/* Transmit Chain Complete */
155#define	INTSTAT_TQE	(1UL << 7)	/* Transmit Queue Empty */
156#define	INTSTAT_TXU	(1UL << 8)	/* Transmit Underrun */
157#define	INTSTAT_CNT	(1UL << 9)	/* Counter Overflow */
158#define	INTSTAT_PREI	(1UL << 10)	/* Preemptive Interrupt */
159#define	INTSTAT_RCT	(1UL << 11)	/* Receive Copy Threshold */
160#define	INTSTAT_FATAL	(1UL << 12)	/* Fatal Error */
161#define	INTSTAT_PME	(1UL << 14)	/* Power Management Event */
162#define	INTSTAT_GP2	(1UL << 15)	/* GPIO Event */
163#define	INTSTAT_ACTV	(1UL << 16)	/* Interrupt Active */
164#define	INTSTAT_RXIDLE	(1UL << 17)	/* Receive Idle */
165#define	INTSTAT_TXIDLE	(1UL << 18)	/* Transmit Idle */
166#define	INTSTAT_RCIP	(1UL << 19)	/* Receive Copy in Progress */
167#define	INTSTAT_TCIP	(1UL << 20)	/* Transmit Copy in Progress */
168#define	INTSTAT_RBE	(1UL << 21)	/* Receive Buffers Empty */
169#define	INTSTAT_RCTS	(1UL << 22)	/* Receive Copy Threshold Status */
170#define	INTSTAT_RSV	(1UL << 23)	/* Receive Status Valid */
171#define	INTSTAT_DPE	(1UL << 24)	/* PCI Data Parity Error */
172#define	INTSTAT_APE	(1UL << 25)	/* PCI Address Parity Error */
173#define	INTSTAT_PMA	(1UL << 26)	/* PCI Master Abort */
174#define	INTSTAT_PTA	(1UL << 27)	/* PCI Target Abort */
175
176#define	INTMASK_RCC	(1UL << 0)	/* Receive Copy Complete */
177#define	INTMASK_HCC	(1UL << 1)	/* Header Copy Complete */
178#define	INTMASK_RQE	(1UL << 2)	/* Receive Queue Empty */
179#define	INTMASK_OVW	(1UL << 3)	/* Receive Overflow */
180#define	INTMASK_RXE	(1UL << 4)	/* Receive Error */
181#define	INTMASK_TXC	(1UL << 5)	/* Transmit Complete */
182#define	INTMASK_TCC	(1UL << 6)	/* Transmit Chain Complete */
183#define	INTMASK_TQE	(1UL << 7)	/* Transmit Queue Empty */
184#define	INTMASK_TXU	(1UL << 8)	/* Transmit Underrun */
185#define	INTMASK_CNT	(1UL << 9)	/* Counter Overflow */
186#define	INTMASK_PREI	(1UL << 10)	/* Preemptive Interrupt */
187#define	INTMASK_RCT	(1UL << 11)	/* Receive Copy Threshold */
188#define	INTMASK_FATAL	(1UL << 12)	/* Fatal Error */
189#define	INTMASK_PME	(1UL << 14)	/* Power Management Event */
190#define	INTMASK_GP2	(1UL << 15)	/* GPIO Event */
191
192#define	GENCTL_RESET	(1UL << 0)	/* Soft Reset */
193#define	GENCTL_INT	(1UL << 1)	/* Interrupt Enable */
194#define	GENCTL_SWINT	(1UL << 2)	/* Software Interrupt */
195#define	GENCTL_PWRDWN	(1UL << 3)	/* Power Down */
196#define	GENCTL_ONECOPY	(1UL << 4)	/* One Copy per Receive Frame */
197#define	GENCTL_BE	(1UL << 5)	/* Big Endian */
198#define	GENCTL_RDP	(1UL << 6)	/* Receive DMA Priority */
199#define	GENCTL_TDP	(1UL << 7)	/* Transmit DMA Priority */
200#define	GENCTL_RFT_32	(0UL << 8)	/* Receive FIFO Threshold (1/4) */
201#define	GENCTL_RFT_64	(1UL << 8)	/* Receive FIFO Threshold (1/2) */
202#define	GENCTL_RFT_96	(2UL << 8)	/* Receive FIFO Threshold (3/4) */
203#define	GENCTL_RFT_128	(3UL << 8)	/* Receive FIFO Threshold (FULL) */
204#define	GENCTL_MRM	(1UL << 10)	/* Memory Read Multiple */
205#define	GENCTL_MRL	(1UL << 11)	/* Memory Read Line */
206#define	GENCTL_SOFT0	(1UL << 12)	/* Software Bit 0 */
207#define	GENCTL_SOFT1	(1UL << 13)	/* Software Bit 1 */
208#define	GENCTL_RSTPHY	(1UL << 14)	/* PHY Reset */
209#define	GENCTL_SCLK	(1UL << 16)	/* System Clock */
210#define	GENCTL_RD	(1UL << 17)	/* Reset Disable */
211#define	GENCTL_MPE	(1UL << 18)	/* Magic Packet Enable */
212#define	GENCTL_PME	(1UL << 19)	/* PME Interrupt Enable */
213#define	GENCTL_PS_00	(0UL << 20)	/* Power State "00" */
214#define	GENCTL_PS_01	(1UL << 20)	/* Power State "01" */
215#define	GENCTL_PS_10	(2UL << 20)	/* Power State "10" */
216#define	GENCTL_PS_11	(3UL << 20)	/* Power State "11" */
217#define	GENCTL_OPLE	(1UL << 22)	/* On Power Loss Enable */
218
219#define	NVCTL_EMM	(1UL << 0)	/* Enable Memory Map */
220#define	NVCTL_CRS	(1UL << 1)	/* Clock Run Supported */
221#define	NVCTL_GPOE1	(1UL << 2)	/* General Purpose Output Enable 1 */
222#define	NVCTL_GPOE2	(1UL << 3)	/* General Purpose Output Enable 2 */
223#define	NVCTL_GPIO1	(1UL << 4)	/* General Purpose I/O 1 */
224#define	NVCTL_GPIO2	(1UL << 5)	/* General Purpose I/O 2 */
225#define	NVCTL_CB_MODE	(1UL << 6)	/* CardBus (UNUSED) */
226#define	NVCTL_IPG_DLY	7		/* Inter-packet Gap Timer Delay */
227
228#define	EECTL_ENABLE	(1UL << 0)	/* EEPROM Enable */
229#define	EECTL_EECS	(1UL << 1)	/* EEPROM Chip Select */
230#define	EECTL_EESK	(1UL << 2)	/* EEPROM Clock */
231#define	EECTL_EEDI	(1UL << 3)	/* EEPROM Data Input */
232#define	EECTL_EEDO	(1UL << 4)	/* EEPROM Data Output */
233#define	EECTL_EERDY	(1UL << 5)	/* EEPROM Ready */
234#define	EECTL_SIZE	(1UL << 6)	/* EEPROM Size */
235
236#define	TEST_CLOCK	(1UL << 3)	/* Clock Test */
237
238#define	MMCTL_READ	(1UL << 0)	/* MII Read */
239#define	MMCTL_WRITE	(1UL << 1)	/* MII Write */
240#define	MMCTL_RESPONDER	(1UL << 3)	/* MII Responder */
241#define	MMCTL_PHYREG	4		/* PHY Address */
242#define	MMCTL_PHYADDR	9		/* PHY Register Address */
243
244#define	MMCFG_SME	(1UL << 0)	/* Serial Mode Enable */
245#define	MMCFG_EN694	(1UL << 1)	/* EN694 Pin */
246#define	MMCFG_694LNK	(1UL << 2)	/* 694LNK Pin */
247#define	MMCFG_PHY	(1UL << 3)	/* PHY Present */
248#define	MMCFG_SMI	(1UL << 4)	/* Enable Serial Management */
249#define	MMCFG_ALTCS	(1UL << 5)	/* Alternate Clock Source */
250#define	MMCFG_ALTDATA	(1UL << 6)	/* Alternate Data */
251#define	MMCFG_STXC	(1UL << 14)	/* Select TX Clock */
252#define	MMCFG_SNTXC	(1UL << 15)	/* Set No TX Clock */
253
254#define	RXCON_SEP	(1UL << 0)	/* Save Errored Packets */
255#define	RXCON_RRF	(1UL << 1)	/* Receive Runt Frames */
256#define	RXCON_RBF	(1UL << 2)	/* Receive Broadcast Frames */
257#define	RXCON_RMF	(1UL << 3)	/* Receive Multicast Frames */
258#define	RXCON_RIIA	(1UL << 4)	/* Receive Inverse Addresses */
259#define	RXCON_PROMISC	(1UL << 5)	/* Promiscuous Mode */
260#define	RXCON_MONITOR	(1UL << 6)	/* Monitor Mode */
261#define	RXCON_ERE	(1UL << 7)	/* Early Receive Enable */
262#define	RXCON_EB_INT	(0UL << 8)	/* External Buffer (Inernal) */
263#define	RXCON_EB_16K	(1UL << 8)	/* External Buffer (16K) */
264#define	RXCON_EB_32K	(2UL << 8)	/* External Buffer (32K) */
265#define	RXCON_EB_128K	(3UL << 8)	/* External Buffer (128K) */
266
267#define	RXSTAT_PRI	(1UL << 0)	/* Packet Received Intact */
268#define	RXSTAT_FAE	(1UL << 1)	/* Frame Alignment Error */
269#define	RXSTAT_CRC	(1UL << 2)	/* CRC Error */
270#define	RXSTAT_MP	(1UL << 3)	/* Missed Packet */
271#define	RXSTAT_MAR	(1UL << 4)	/* Multicast Address Recognized */
272#define	RXSTAT_BAR	(1UL << 5)	/* Broadcast Address Recognized */
273#define	RXSTAT_RD	(1UL << 6)	/* Receiver Disabled */
274#define	RXSTAT_NSV	(1UL << 12)	/* Network Status Valid */
275#define	RXSTAT_FLE	(1UL << 13)	/* Fragment List Error */
276#define	RXSTAT_HC	(1UL << 14)	/* Header Copied */
277#define	RXSTAT_OWNER	(1UL << 15)	/* Descriptor Ownership Bit */
278
279#define	RXCTL_FRAGLIST	(1UL << 0)	/* Fragment List */
280#define	RXCTL_LFFORM	(1UL << 1)	/* Fragment List Format */
281#define	RXCTL_HEADER	(1UL << 2)	/* Header Copy */
282
283#define	TXCON_ETE	(1UL << 0)	/* Early Transmit Enable */
284#define	TXCON_LB_0	(0UL << 1)	/* Normal Operation */
285#define	TXCON_LB_1	(1UL << 1)	/* Internal Loopback */
286#define	TXCON_LB_2	(2UL << 1)	/* External Loopback */
287#define	TXCON_LB_3	(3UL << 1)	/* Full Duplex Mode */
288#define	TXCON_SLOT	3		/* Slot Time */
289
290#define	TXSTAT_PTX	(1UL << 0)	/* Packet Transmitted */
291#define	TXSTAT_ND	(1UL << 1)	/* Non-deferred Transmission */
292#define	TXSTAT_COLL	(1UL << 2)	/* Transmitted w/Collisions */
293#define	TXSTAT_CSL	(1UL << 3)	/* Carrier Sense Lost */
294#define	TXSTAT_UFLO	(1UL << 4)	/* TX Underrun */
295#define	TXSTAT_CDH	(1UL << 5)	/* Collision Detect Heartbeat */
296#define	TXSTAT_OWC	(1UL << 6)	/* Out of Window Collision */
297#define	TXSTAT_DEFER	(1UL << 7)	/* IGP Deferring */
298#define	TXSTAT_CCNT	8		/* Collision Count */
299#define	TXSTAT_CCNTMASK	0x1F		/* Collision Count Mask */
300#define	TXSTAT_EXCOLL	(1UL << 12)	/* Excessive Collisions */
301#define	TXSTAT_OWNER	(1UL << 15)	/* Descriptor Ownership Bit */
302
303#define	TXCTL_FRAGLIST	(1UL << 0)	/* Fragment List */
304#define	TXCTL_LFFORM	(1UL << 1)	/* Fragment List Format */
305#define	TXCTL_IAF	(1UL << 2)	/* Interrupt After Frame */
306#define	TXCTL_NOCRC	(1UL << 3)	/* Disable CRC Generation */
307#define	TXCTL_LASTDESCR	(1UL << 4)	/* Last Transmit Descriptor */
308
309/*
310 * Register access.
311 */
312#define	GETCSR(efep, reg) \
313	ddi_get32((efep)->efe_regs_acch, \
314	    (uint32_t *)((efep)->efe_regs + (reg)))
315
316#define	PUTCSR(efep, reg, val) \
317	ddi_put32((efep)->efe_regs_acch, \
318	    (uint32_t *)((efep)->efe_regs + (reg)), (val))
319
320#define	CLRBIT(efep, reg, bit) \
321	PUTCSR(efep, reg, (GETCSR(efep, reg) & ~(bit)))
322
323#define	SETBIT(efep, reg, bit) \
324	PUTCSR(efep, reg, (GETCSR(efep, reg) | (bit)))
325
326/*
327 * DMA access.
328 */
329#define	DESCSZ(x)		(sizeof (efe_desc_t) * (x))
330#define	BUFPSZ(x)		(sizeof (efe_buf_t *) * (x))
331
332#define	DESCADDR(rp, x)		((rp)->r_dmac.dmac_address + DESCSZ(x))
333#define	DESCLEN(rp)		((rp)->r_len)
334
335#define	BUFADDR(bp)		((bp)->b_dmac.dmac_address)
336#define	BUFLEN(bp)		((bp)->b_len)
337
338#define	NEXTDESC(rp, x)		(((x) + 1) % (rp)->r_len)
339#define	NEXTDESCADDR(rp, x)	DESCADDR(rp, NEXTDESC(rp, x))
340
341#define	GETDESC(rp, x) 		(&(rp)->r_descp[(x)])
342
343#define	GETDESC16(rp, addr) \
344	ddi_get16((rp)->r_acch, (addr))
345
346#define	PUTDESC16(rp, addr, val) \
347	ddi_put16((rp)->r_acch, (addr), (val))
348
349#define	GETDESC32(rp, addr) \
350	ddi_get32((rp)->r_acch, (addr))
351
352#define	PUTDESC32(rp, addr, val) \
353	ddi_put32((rp)->r_acch, (addr), (val))
354
355#define	SYNCDESC(rp, x, type) \
356	(void) ddi_dma_sync((rp)->r_dmah, DESCSZ(x), \
357	    sizeof (efe_desc_t), (type))
358
359#define	GETBUF(rp, x)		((rp)->r_bufpp[(x)])
360
361#define	SYNCBUF(bp, type) \
362	(void) ddi_dma_sync((bp)->b_dmah, 0, (bp)->b_len, (type))
363
364/*
365 * Soft state.
366 */
367typedef struct {
368	uint16_t		d_status;
369	uint16_t		d_len;
370	uint32_t		d_bufaddr;
371	uint16_t		d_buflen;
372	uint16_t		d_control;
373	uint32_t		d_next;
374} efe_desc_t;
375
376typedef struct {
377	ddi_dma_handle_t	b_dmah;
378	ddi_acc_handle_t	b_acch;
379	ddi_dma_cookie_t	b_dmac;
380	size_t			b_len;
381	caddr_t			b_kaddr;
382} efe_buf_t;
383
384typedef struct {
385	ddi_dma_handle_t	r_dmah;
386	ddi_acc_handle_t	r_acch;
387	ddi_dma_cookie_t	r_dmac;
388	size_t			r_len;
389	efe_desc_t		*r_descp;
390	efe_buf_t		**r_bufpp;
391} efe_ring_t;
392
393typedef struct {
394	dev_info_t		*efe_dip;
395
396	mii_handle_t		efe_miih;
397	mac_handle_t		efe_mh;
398
399	uint32_t		*efe_regs;
400	ddi_acc_handle_t	efe_regs_acch;
401
402	ddi_intr_handle_t	efe_intrh;
403
404	kmutex_t		efe_intrlock;
405	kmutex_t		efe_txlock;
406
407	int			efe_flags;
408	boolean_t		efe_promisc;
409
410	uint8_t			efe_macaddr[ETHERADDRL];
411
412	uint_t			efe_mccount[MCHASHL];
413	uint16_t		efe_mchash[MCHASHL / MCHASHSZ];
414
415	efe_ring_t		*efe_rx_ring;
416	uint_t			efe_rx_desc;
417
418	efe_ring_t		*efe_tx_ring;
419	uint_t			efe_tx_desc;
420	uint_t			efe_tx_sent;
421
422	/*
423	 * Driver statistics.
424	 */
425	uint64_t		efe_multircv;
426	uint64_t		efe_brdcstrcv;
427	uint64_t		efe_multixmt;
428	uint64_t		efe_brdcstxmt;
429	uint64_t		efe_norcvbuf;
430	uint64_t		efe_ierrors;
431	uint64_t		efe_noxmtbuf;
432	uint64_t		efe_oerrors;
433	uint64_t		efe_collisions;
434	uint64_t		efe_rbytes;
435	uint64_t		efe_ipackets;
436	uint64_t		efe_obytes;
437	uint64_t		efe_opackets;
438	uint64_t		efe_uflo;
439	uint64_t		efe_oflo;
440	uint64_t		efe_align_errors;
441	uint64_t		efe_fcs_errors;
442	uint64_t		efe_first_collisions;
443	uint64_t		efe_tx_late_collisions;
444	uint64_t		efe_defer_xmts;
445	uint64_t		efe_ex_collisions;
446	uint64_t		efe_macxmt_errors;
447	uint64_t		efe_carrier_errors;
448	uint64_t		efe_toolong_errors;
449	uint64_t		efe_macrcv_errors;
450	uint64_t		efe_runt_errors;
451	uint64_t		efe_jabber_errors;
452} efe_t;
453
454#ifdef	__cplusplus
455}
456#endif
457
458#endif	/* _EFE_H */