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/sys/dev/mvs/mvs_soc.c

https://github.com/freebsd/freebsd
C | 470 lines | 376 code | 45 blank | 49 comment | 53 complexity | 81ded45f13c5dec75eaabdb15e75ac67 MD5 | raw file
  1. /*-
  2. * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
  3. *
  4. * Copyright (c) 2010 Alexander Motin <mav@FreeBSD.org>
  5. * All rights reserved.
  6. *
  7. * Redistribution and use in source and binary forms, with or without
  8. * modification, are permitted provided that the following conditions
  9. * are met:
  10. * 1. Redistributions of source code must retain the above copyright
  11. * notice, this list of conditions and the following disclaimer,
  12. * without modification, immediately at the beginning of the file.
  13. * 2. Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. *
  17. * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  18. * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  19. * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  20. * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  21. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  22. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23. * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24. * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  26. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27. */
  28. #include <sys/cdefs.h>
  29. __FBSDID("$FreeBSD$");
  30. #include <sys/param.h>
  31. #include <sys/module.h>
  32. #include <sys/systm.h>
  33. #include <sys/kernel.h>
  34. #include <sys/bus.h>
  35. #include <sys/endian.h>
  36. #include <sys/malloc.h>
  37. #include <sys/lock.h>
  38. #include <sys/mutex.h>
  39. #include <vm/uma.h>
  40. #include <machine/stdarg.h>
  41. #include <machine/resource.h>
  42. #include <machine/bus.h>
  43. #include <sys/rman.h>
  44. #include <sys/sbuf.h>
  45. #include <arm/mv/mvreg.h>
  46. #include <arm/mv/mvvar.h>
  47. #include <dev/ofw/ofw_bus.h>
  48. #include <dev/ofw/ofw_bus_subr.h>
  49. #include "mvs.h"
  50. /* local prototypes */
  51. static int mvs_setup_interrupt(device_t dev);
  52. static void mvs_intr(void *data);
  53. static int mvs_suspend(device_t dev);
  54. static int mvs_resume(device_t dev);
  55. static int mvs_ctlr_setup(device_t dev);
  56. static struct {
  57. uint32_t id;
  58. uint8_t rev;
  59. const char *name;
  60. int ports;
  61. int quirks;
  62. } mvs_ids[] = {
  63. {MV_DEV_88F5182, 0x00, "Marvell 88F5182", 2, MVS_Q_GENIIE|MVS_Q_SOC},
  64. {MV_DEV_88F6281, 0x00, "Marvell 88F6281", 2, MVS_Q_GENIIE|MVS_Q_SOC},
  65. {MV_DEV_88F6282, 0x00, "Marvell 88F6282", 2, MVS_Q_GENIIE|MVS_Q_SOC},
  66. {MV_DEV_MV78100, 0x00, "Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC},
  67. {MV_DEV_MV78100_Z0, 0x00,"Marvell MV78100", 2, MVS_Q_GENIIE|MVS_Q_SOC},
  68. {MV_DEV_MV78260, 0x00, "Marvell MV78260", 2, MVS_Q_GENIIE|MVS_Q_SOC},
  69. {MV_DEV_MV78460, 0x00, "Marvell MV78460", 2, MVS_Q_GENIIE|MVS_Q_SOC},
  70. {0, 0x00, NULL, 0, 0}
  71. };
  72. static int
  73. mvs_probe(device_t dev)
  74. {
  75. char buf[64];
  76. int i;
  77. uint32_t devid, revid;
  78. if (!ofw_bus_status_okay(dev))
  79. return (ENXIO);
  80. if (!ofw_bus_is_compatible(dev, "mrvl,sata"))
  81. return (ENXIO);
  82. soc_id(&devid, &revid);
  83. for (i = 0; mvs_ids[i].id != 0; i++) {
  84. if (mvs_ids[i].id == devid &&
  85. mvs_ids[i].rev <= revid) {
  86. snprintf(buf, sizeof(buf), "%s SATA controller",
  87. mvs_ids[i].name);
  88. device_set_desc_copy(dev, buf);
  89. return (BUS_PROBE_DEFAULT);
  90. }
  91. }
  92. return (ENXIO);
  93. }
  94. static int
  95. mvs_attach(device_t dev)
  96. {
  97. struct mvs_controller *ctlr = device_get_softc(dev);
  98. device_t child;
  99. int error, unit, i;
  100. uint32_t devid, revid;
  101. soc_id(&devid, &revid);
  102. ctlr->dev = dev;
  103. i = 0;
  104. while (mvs_ids[i].id != 0 &&
  105. (mvs_ids[i].id != devid ||
  106. mvs_ids[i].rev > revid))
  107. i++;
  108. ctlr->channels = mvs_ids[i].ports;
  109. ctlr->quirks = mvs_ids[i].quirks;
  110. ctlr->ccc = 0;
  111. resource_int_value(device_get_name(dev),
  112. device_get_unit(dev), "ccc", &ctlr->ccc);
  113. ctlr->cccc = 8;
  114. resource_int_value(device_get_name(dev),
  115. device_get_unit(dev), "cccc", &ctlr->cccc);
  116. if (ctlr->ccc == 0 || ctlr->cccc == 0) {
  117. ctlr->ccc = 0;
  118. ctlr->cccc = 0;
  119. }
  120. if (ctlr->ccc > 100000)
  121. ctlr->ccc = 100000;
  122. device_printf(dev,
  123. "Gen-%s, %d %sGbps ports, Port Multiplier %s%s\n",
  124. ((ctlr->quirks & MVS_Q_GENI) ? "I" :
  125. ((ctlr->quirks & MVS_Q_GENII) ? "II" : "IIe")),
  126. ctlr->channels,
  127. ((ctlr->quirks & MVS_Q_GENI) ? "1.5" : "3"),
  128. ((ctlr->quirks & MVS_Q_GENI) ?
  129. "not supported" : "supported"),
  130. ((ctlr->quirks & MVS_Q_GENIIE) ?
  131. " with FBS" : ""));
  132. mtx_init(&ctlr->mtx, "MVS controller lock", NULL, MTX_DEF);
  133. /* We should have a memory BAR(0). */
  134. ctlr->r_rid = 0;
  135. if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
  136. &ctlr->r_rid, RF_ACTIVE)))
  137. return ENXIO;
  138. if (ATA_INL(ctlr->r_mem, PORT_BASE(0) + SATA_PHYCFG_OFS) != 0)
  139. ctlr->quirks |= MVS_Q_SOC65;
  140. /* Setup our own memory management for channels. */
  141. ctlr->sc_iomem.rm_start = rman_get_start(ctlr->r_mem);
  142. ctlr->sc_iomem.rm_end = rman_get_end(ctlr->r_mem);
  143. ctlr->sc_iomem.rm_type = RMAN_ARRAY;
  144. ctlr->sc_iomem.rm_descr = "I/O memory addresses";
  145. if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
  146. bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
  147. return (error);
  148. }
  149. if ((error = rman_manage_region(&ctlr->sc_iomem,
  150. rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
  151. bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
  152. rman_fini(&ctlr->sc_iomem);
  153. return (error);
  154. }
  155. mvs_ctlr_setup(dev);
  156. /* Setup interrupts. */
  157. if (mvs_setup_interrupt(dev)) {
  158. bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
  159. rman_fini(&ctlr->sc_iomem);
  160. return ENXIO;
  161. }
  162. /* Attach all channels on this controller */
  163. for (unit = 0; unit < ctlr->channels; unit++) {
  164. child = device_add_child(dev, "mvsch", -1);
  165. if (child == NULL)
  166. device_printf(dev, "failed to add channel device\n");
  167. else
  168. device_set_ivars(child, (void *)(intptr_t)unit);
  169. }
  170. bus_generic_attach(dev);
  171. return 0;
  172. }
  173. static int
  174. mvs_detach(device_t dev)
  175. {
  176. struct mvs_controller *ctlr = device_get_softc(dev);
  177. /* Detach & delete all children */
  178. device_delete_children(dev);
  179. /* Free interrupt. */
  180. if (ctlr->irq.r_irq) {
  181. bus_teardown_intr(dev, ctlr->irq.r_irq,
  182. ctlr->irq.handle);
  183. bus_release_resource(dev, SYS_RES_IRQ,
  184. ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
  185. }
  186. /* Free memory. */
  187. rman_fini(&ctlr->sc_iomem);
  188. if (ctlr->r_mem)
  189. bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
  190. mtx_destroy(&ctlr->mtx);
  191. return (0);
  192. }
  193. static int
  194. mvs_ctlr_setup(device_t dev)
  195. {
  196. struct mvs_controller *ctlr = device_get_softc(dev);
  197. int ccc = ctlr->ccc, cccc = ctlr->cccc, ccim = 0;
  198. /* Mask chip interrupts */
  199. ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000);
  200. /* Clear HC interrupts */
  201. ATA_OUTL(ctlr->r_mem, HC_IC, 0x00000000);
  202. /* Clear chip interrupts */
  203. ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIC, 0);
  204. /* Configure per-HC CCC */
  205. if (ccc && bootverbose) {
  206. device_printf(dev,
  207. "CCC with %dus/%dcmd enabled\n",
  208. ctlr->ccc, ctlr->cccc);
  209. }
  210. ccc *= 150;
  211. ATA_OUTL(ctlr->r_mem, HC_ICT, cccc);
  212. ATA_OUTL(ctlr->r_mem, HC_ITT, ccc);
  213. if (ccc)
  214. ccim |= IC_HC0_COAL_DONE;
  215. /* Enable chip interrupts */
  216. ctlr->gmim = ((ccc ? IC_HC0_COAL_DONE :
  217. (IC_DONE_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels))) |
  218. (IC_ERR_HC0 & CHIP_SOC_HC0_MASK(ctlr->channels)));
  219. ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim);
  220. return (0);
  221. }
  222. static void
  223. mvs_edma(device_t dev, device_t child, int mode)
  224. {
  225. struct mvs_controller *ctlr = device_get_softc(dev);
  226. int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
  227. int bit = IC_DONE_IRQ << (unit * 2);
  228. if (ctlr->ccc == 0)
  229. return;
  230. /* CCC is not working for non-EDMA mode. Unmask device interrupts. */
  231. mtx_lock(&ctlr->mtx);
  232. if (mode == MVS_EDMA_OFF)
  233. ctlr->pmim |= bit;
  234. else
  235. ctlr->pmim &= ~bit;
  236. ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, ctlr->gmim | ctlr->pmim);
  237. mtx_unlock(&ctlr->mtx);
  238. }
  239. static int
  240. mvs_suspend(device_t dev)
  241. {
  242. struct mvs_controller *ctlr = device_get_softc(dev);
  243. bus_generic_suspend(dev);
  244. /* Mask chip interrupts */
  245. ATA_OUTL(ctlr->r_mem, CHIP_SOC_MIM, 0x00000000);
  246. return 0;
  247. }
  248. static int
  249. mvs_resume(device_t dev)
  250. {
  251. mvs_ctlr_setup(dev);
  252. return (bus_generic_resume(dev));
  253. }
  254. static int
  255. mvs_setup_interrupt(device_t dev)
  256. {
  257. struct mvs_controller *ctlr = device_get_softc(dev);
  258. /* Allocate all IRQs. */
  259. ctlr->irq.r_irq_rid = 0;
  260. if (!(ctlr->irq.r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
  261. &ctlr->irq.r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
  262. device_printf(dev, "unable to map interrupt\n");
  263. return (ENXIO);
  264. }
  265. if ((bus_setup_intr(dev, ctlr->irq.r_irq, ATA_INTR_FLAGS, NULL,
  266. mvs_intr, ctlr, &ctlr->irq.handle))) {
  267. device_printf(dev, "unable to setup interrupt\n");
  268. bus_release_resource(dev, SYS_RES_IRQ,
  269. ctlr->irq.r_irq_rid, ctlr->irq.r_irq);
  270. ctlr->irq.r_irq = NULL;
  271. return (ENXIO);
  272. }
  273. return (0);
  274. }
  275. /*
  276. * Common case interrupt handler.
  277. */
  278. static void
  279. mvs_intr(void *data)
  280. {
  281. struct mvs_controller *ctlr = data;
  282. struct mvs_intr_arg arg;
  283. void (*function)(void *);
  284. int p, chan_num;
  285. u_int32_t ic, aic;
  286. ic = ATA_INL(ctlr->r_mem, CHIP_SOC_MIC);
  287. if ((ic & IC_HC0) == 0)
  288. return;
  289. /* Acknowledge interrupts of this HC. */
  290. aic = 0;
  291. /* Processing interrupts from each initialized channel */
  292. for (chan_num = 0; chan_num < ctlr->channels; chan_num++) {
  293. if (ic & (IC_DONE_IRQ << (chan_num * 2)))
  294. aic |= HC_IC_DONE(chan_num) | HC_IC_DEV(chan_num);
  295. }
  296. if (ic & IC_HC0_COAL_DONE)
  297. aic |= HC_IC_COAL;
  298. ATA_OUTL(ctlr->r_mem, HC_IC, ~aic);
  299. /* Call per-port interrupt handler. */
  300. for (p = 0; p < ctlr->channels; p++) {
  301. arg.cause = ic & (IC_ERR_IRQ|IC_DONE_IRQ);
  302. if ((arg.cause != 0) &&
  303. (function = ctlr->interrupt[p].function)) {
  304. arg.arg = ctlr->interrupt[p].argument;
  305. function(&arg);
  306. }
  307. ic >>= 2;
  308. }
  309. }
  310. static struct resource *
  311. mvs_alloc_resource(device_t dev, device_t child, int type, int *rid,
  312. rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
  313. {
  314. struct mvs_controller *ctlr = device_get_softc(dev);
  315. int unit = ((struct mvs_channel *)device_get_softc(child))->unit;
  316. struct resource *res = NULL;
  317. int offset = PORT_BASE(unit & 0x03);
  318. rman_res_t st;
  319. switch (type) {
  320. case SYS_RES_MEMORY:
  321. st = rman_get_start(ctlr->r_mem);
  322. res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
  323. st + offset + PORT_SIZE - 1, PORT_SIZE, RF_ACTIVE, child);
  324. if (res) {
  325. bus_space_handle_t bsh;
  326. bus_space_tag_t bst;
  327. bsh = rman_get_bushandle(ctlr->r_mem);
  328. bst = rman_get_bustag(ctlr->r_mem);
  329. bus_space_subregion(bst, bsh, offset, PORT_SIZE, &bsh);
  330. rman_set_bushandle(res, bsh);
  331. rman_set_bustag(res, bst);
  332. }
  333. break;
  334. case SYS_RES_IRQ:
  335. if (*rid == ATA_IRQ_RID)
  336. res = ctlr->irq.r_irq;
  337. break;
  338. }
  339. return (res);
  340. }
  341. static int
  342. mvs_release_resource(device_t dev, device_t child, int type, int rid,
  343. struct resource *r)
  344. {
  345. switch (type) {
  346. case SYS_RES_MEMORY:
  347. rman_release_resource(r);
  348. return (0);
  349. case SYS_RES_IRQ:
  350. if (rid != ATA_IRQ_RID)
  351. return ENOENT;
  352. return (0);
  353. }
  354. return (EINVAL);
  355. }
  356. static int
  357. mvs_setup_intr(device_t dev, device_t child, struct resource *irq,
  358. int flags, driver_filter_t *filter, driver_intr_t *function,
  359. void *argument, void **cookiep)
  360. {
  361. struct mvs_controller *ctlr = device_get_softc(dev);
  362. int unit = (intptr_t)device_get_ivars(child);
  363. if (filter != NULL) {
  364. printf("mvs.c: we cannot use a filter here\n");
  365. return (EINVAL);
  366. }
  367. ctlr->interrupt[unit].function = function;
  368. ctlr->interrupt[unit].argument = argument;
  369. return (0);
  370. }
  371. static int
  372. mvs_teardown_intr(device_t dev, device_t child, struct resource *irq,
  373. void *cookie)
  374. {
  375. struct mvs_controller *ctlr = device_get_softc(dev);
  376. int unit = (intptr_t)device_get_ivars(child);
  377. ctlr->interrupt[unit].function = NULL;
  378. ctlr->interrupt[unit].argument = NULL;
  379. return (0);
  380. }
  381. static int
  382. mvs_print_child(device_t dev, device_t child)
  383. {
  384. int retval;
  385. retval = bus_print_child_header(dev, child);
  386. retval += printf(" at channel %d",
  387. (int)(intptr_t)device_get_ivars(child));
  388. retval += bus_print_child_footer(dev, child);
  389. return (retval);
  390. }
  391. static int
  392. mvs_child_location(device_t dev, device_t child, struct sbuf *sb)
  393. {
  394. sbuf_printf(sb, "channel=%d", (int)(intptr_t)device_get_ivars(child));
  395. return (0);
  396. }
  397. static bus_dma_tag_t
  398. mvs_get_dma_tag(device_t bus, device_t child)
  399. {
  400. return (bus_get_dma_tag(bus));
  401. }
  402. static device_method_t mvs_methods[] = {
  403. DEVMETHOD(device_probe, mvs_probe),
  404. DEVMETHOD(device_attach, mvs_attach),
  405. DEVMETHOD(device_detach, mvs_detach),
  406. DEVMETHOD(device_suspend, mvs_suspend),
  407. DEVMETHOD(device_resume, mvs_resume),
  408. DEVMETHOD(bus_print_child, mvs_print_child),
  409. DEVMETHOD(bus_alloc_resource, mvs_alloc_resource),
  410. DEVMETHOD(bus_release_resource, mvs_release_resource),
  411. DEVMETHOD(bus_setup_intr, mvs_setup_intr),
  412. DEVMETHOD(bus_teardown_intr,mvs_teardown_intr),
  413. DEVMETHOD(bus_child_location, mvs_child_location),
  414. DEVMETHOD(bus_get_dma_tag, mvs_get_dma_tag),
  415. DEVMETHOD(mvs_edma, mvs_edma),
  416. { 0, 0 }
  417. };
  418. static driver_t mvs_driver = {
  419. "mvs",
  420. mvs_methods,
  421. sizeof(struct mvs_controller)
  422. };
  423. DRIVER_MODULE(mvs, simplebus, mvs_driver, mvs_devclass, 0, 0);
  424. MODULE_VERSION(mvs, 1);
  425. MODULE_DEPEND(mvs, cam, 1, 1, 1);