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/drivers/gpu/drm/i915/i915_gpu_error.c

https://bitbucket.org/alfredchen/linux-gc
C | 1684 lines | 1280 code | 297 blank | 107 comment | 232 complexity | 026f20757a695fced9b20e63cc878623 MD5 | raw file
Possible License(s): GPL-2.0, LGPL-2.0, AGPL-1.0
  1. /*
  2. * Copyright (c) 2008 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Eric Anholt <eric@anholt.net>
  25. * Keith Packard <keithp@keithp.com>
  26. * Mika Kuoppala <mika.kuoppala@intel.com>
  27. *
  28. */
  29. #include <generated/utsrelease.h>
  30. #include <linux/stop_machine.h>
  31. #include <linux/zlib.h>
  32. #include "i915_drv.h"
  33. static const char *engine_str(int engine)
  34. {
  35. switch (engine) {
  36. case RCS: return "render";
  37. case VCS: return "bsd";
  38. case BCS: return "blt";
  39. case VECS: return "vebox";
  40. case VCS2: return "bsd2";
  41. default: return "";
  42. }
  43. }
  44. static const char *tiling_flag(int tiling)
  45. {
  46. switch (tiling) {
  47. default:
  48. case I915_TILING_NONE: return "";
  49. case I915_TILING_X: return " X";
  50. case I915_TILING_Y: return " Y";
  51. }
  52. }
  53. static const char *dirty_flag(int dirty)
  54. {
  55. return dirty ? " dirty" : "";
  56. }
  57. static const char *purgeable_flag(int purgeable)
  58. {
  59. return purgeable ? " purgeable" : "";
  60. }
  61. static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
  62. {
  63. if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
  64. e->err = -ENOSPC;
  65. return false;
  66. }
  67. if (e->bytes == e->size - 1 || e->err)
  68. return false;
  69. return true;
  70. }
  71. static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
  72. unsigned len)
  73. {
  74. if (e->pos + len <= e->start) {
  75. e->pos += len;
  76. return false;
  77. }
  78. /* First vsnprintf needs to fit in its entirety for memmove */
  79. if (len >= e->size) {
  80. e->err = -EIO;
  81. return false;
  82. }
  83. return true;
  84. }
  85. static void __i915_error_advance(struct drm_i915_error_state_buf *e,
  86. unsigned len)
  87. {
  88. /* If this is first printf in this window, adjust it so that
  89. * start position matches start of the buffer
  90. */
  91. if (e->pos < e->start) {
  92. const size_t off = e->start - e->pos;
  93. /* Should not happen but be paranoid */
  94. if (off > len || e->bytes) {
  95. e->err = -EIO;
  96. return;
  97. }
  98. memmove(e->buf, e->buf + off, len - off);
  99. e->bytes = len - off;
  100. e->pos = e->start;
  101. return;
  102. }
  103. e->bytes += len;
  104. e->pos += len;
  105. }
  106. __printf(2, 0)
  107. static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
  108. const char *f, va_list args)
  109. {
  110. unsigned len;
  111. if (!__i915_error_ok(e))
  112. return;
  113. /* Seek the first printf which is hits start position */
  114. if (e->pos < e->start) {
  115. va_list tmp;
  116. va_copy(tmp, args);
  117. len = vsnprintf(NULL, 0, f, tmp);
  118. va_end(tmp);
  119. if (!__i915_error_seek(e, len))
  120. return;
  121. }
  122. len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
  123. if (len >= e->size - e->bytes)
  124. len = e->size - e->bytes - 1;
  125. __i915_error_advance(e, len);
  126. }
  127. static void i915_error_puts(struct drm_i915_error_state_buf *e,
  128. const char *str)
  129. {
  130. unsigned len;
  131. if (!__i915_error_ok(e))
  132. return;
  133. len = strlen(str);
  134. /* Seek the first printf which is hits start position */
  135. if (e->pos < e->start) {
  136. if (!__i915_error_seek(e, len))
  137. return;
  138. }
  139. if (len >= e->size - e->bytes)
  140. len = e->size - e->bytes - 1;
  141. memcpy(e->buf + e->bytes, str, len);
  142. __i915_error_advance(e, len);
  143. }
  144. #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
  145. #define err_puts(e, s) i915_error_puts(e, s)
  146. #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
  147. struct compress {
  148. struct z_stream_s zstream;
  149. void *tmp;
  150. };
  151. static bool compress_init(struct compress *c)
  152. {
  153. struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
  154. zstream->workspace =
  155. kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
  156. GFP_ATOMIC | __GFP_NOWARN);
  157. if (!zstream->workspace)
  158. return false;
  159. if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
  160. kfree(zstream->workspace);
  161. return false;
  162. }
  163. c->tmp = NULL;
  164. if (i915_has_memcpy_from_wc())
  165. c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
  166. return true;
  167. }
  168. static int compress_page(struct compress *c,
  169. void *src,
  170. struct drm_i915_error_object *dst)
  171. {
  172. struct z_stream_s *zstream = &c->zstream;
  173. zstream->next_in = src;
  174. if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
  175. zstream->next_in = c->tmp;
  176. zstream->avail_in = PAGE_SIZE;
  177. do {
  178. if (zstream->avail_out == 0) {
  179. unsigned long page;
  180. page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
  181. if (!page)
  182. return -ENOMEM;
  183. dst->pages[dst->page_count++] = (void *)page;
  184. zstream->next_out = (void *)page;
  185. zstream->avail_out = PAGE_SIZE;
  186. }
  187. if (zlib_deflate(zstream, Z_SYNC_FLUSH) != Z_OK)
  188. return -EIO;
  189. } while (zstream->avail_in);
  190. /* Fallback to uncompressed if we increase size? */
  191. if (0 && zstream->total_out > zstream->total_in)
  192. return -E2BIG;
  193. return 0;
  194. }
  195. static void compress_fini(struct compress *c,
  196. struct drm_i915_error_object *dst)
  197. {
  198. struct z_stream_s *zstream = &c->zstream;
  199. if (dst) {
  200. zlib_deflate(zstream, Z_FINISH);
  201. dst->unused = zstream->avail_out;
  202. }
  203. zlib_deflateEnd(zstream);
  204. kfree(zstream->workspace);
  205. if (c->tmp)
  206. free_page((unsigned long)c->tmp);
  207. }
  208. static void err_compression_marker(struct drm_i915_error_state_buf *m)
  209. {
  210. err_puts(m, ":");
  211. }
  212. #else
  213. struct compress {
  214. };
  215. static bool compress_init(struct compress *c)
  216. {
  217. return true;
  218. }
  219. static int compress_page(struct compress *c,
  220. void *src,
  221. struct drm_i915_error_object *dst)
  222. {
  223. unsigned long page;
  224. void *ptr;
  225. page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
  226. if (!page)
  227. return -ENOMEM;
  228. ptr = (void *)page;
  229. if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
  230. memcpy(ptr, src, PAGE_SIZE);
  231. dst->pages[dst->page_count++] = ptr;
  232. return 0;
  233. }
  234. static void compress_fini(struct compress *c,
  235. struct drm_i915_error_object *dst)
  236. {
  237. }
  238. static void err_compression_marker(struct drm_i915_error_state_buf *m)
  239. {
  240. err_puts(m, "~");
  241. }
  242. #endif
  243. static void print_error_buffers(struct drm_i915_error_state_buf *m,
  244. const char *name,
  245. struct drm_i915_error_buffer *err,
  246. int count)
  247. {
  248. int i;
  249. err_printf(m, "%s [%d]:\n", name, count);
  250. while (count--) {
  251. err_printf(m, " %08x_%08x %8u %02x %02x [ ",
  252. upper_32_bits(err->gtt_offset),
  253. lower_32_bits(err->gtt_offset),
  254. err->size,
  255. err->read_domains,
  256. err->write_domain);
  257. for (i = 0; i < I915_NUM_ENGINES; i++)
  258. err_printf(m, "%02x ", err->rseqno[i]);
  259. err_printf(m, "] %02x", err->wseqno);
  260. err_puts(m, tiling_flag(err->tiling));
  261. err_puts(m, dirty_flag(err->dirty));
  262. err_puts(m, purgeable_flag(err->purgeable));
  263. err_puts(m, err->userptr ? " userptr" : "");
  264. err_puts(m, err->engine != -1 ? " " : "");
  265. err_puts(m, engine_str(err->engine));
  266. err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
  267. if (err->name)
  268. err_printf(m, " (name: %d)", err->name);
  269. if (err->fence_reg != I915_FENCE_REG_NONE)
  270. err_printf(m, " (fence: %d)", err->fence_reg);
  271. err_puts(m, "\n");
  272. err++;
  273. }
  274. }
  275. static void error_print_instdone(struct drm_i915_error_state_buf *m,
  276. struct drm_i915_error_engine *ee)
  277. {
  278. int slice;
  279. int subslice;
  280. err_printf(m, " INSTDONE: 0x%08x\n",
  281. ee->instdone.instdone);
  282. if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
  283. return;
  284. err_printf(m, " SC_INSTDONE: 0x%08x\n",
  285. ee->instdone.slice_common);
  286. if (INTEL_GEN(m->i915) <= 6)
  287. return;
  288. for_each_instdone_slice_subslice(m->i915, slice, subslice)
  289. err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
  290. slice, subslice,
  291. ee->instdone.sampler[slice][subslice]);
  292. for_each_instdone_slice_subslice(m->i915, slice, subslice)
  293. err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
  294. slice, subslice,
  295. ee->instdone.row[slice][subslice]);
  296. }
  297. static void error_print_request(struct drm_i915_error_state_buf *m,
  298. const char *prefix,
  299. struct drm_i915_error_request *erq)
  300. {
  301. if (!erq->seqno)
  302. return;
  303. err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, emitted %dms ago, head %08x, tail %08x\n",
  304. prefix, erq->pid, erq->ban_score,
  305. erq->context, erq->seqno,
  306. jiffies_to_msecs(jiffies - erq->jiffies),
  307. erq->head, erq->tail);
  308. }
  309. static void error_print_engine(struct drm_i915_error_state_buf *m,
  310. struct drm_i915_error_engine *ee)
  311. {
  312. err_printf(m, "%s command stream:\n", engine_str(ee->engine_id));
  313. err_printf(m, " START: 0x%08x\n", ee->start);
  314. err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
  315. err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",
  316. ee->tail, ee->rq_post, ee->rq_tail);
  317. err_printf(m, " CTL: 0x%08x\n", ee->ctl);
  318. err_printf(m, " MODE: 0x%08x\n", ee->mode);
  319. err_printf(m, " HWS: 0x%08x\n", ee->hws);
  320. err_printf(m, " ACTHD: 0x%08x %08x\n",
  321. (u32)(ee->acthd>>32), (u32)ee->acthd);
  322. err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
  323. err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
  324. error_print_instdone(m, ee);
  325. if (ee->batchbuffer) {
  326. u64 start = ee->batchbuffer->gtt_offset;
  327. u64 end = start + ee->batchbuffer->gtt_size;
  328. err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",
  329. upper_32_bits(start), lower_32_bits(start),
  330. upper_32_bits(end), lower_32_bits(end));
  331. }
  332. if (INTEL_GEN(m->i915) >= 4) {
  333. err_printf(m, " BBADDR: 0x%08x_%08x\n",
  334. (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
  335. err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
  336. err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
  337. }
  338. err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
  339. err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
  340. lower_32_bits(ee->faddr));
  341. if (INTEL_GEN(m->i915) >= 6) {
  342. err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
  343. err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
  344. err_printf(m, " SYNC_0: 0x%08x\n",
  345. ee->semaphore_mboxes[0]);
  346. err_printf(m, " SYNC_1: 0x%08x\n",
  347. ee->semaphore_mboxes[1]);
  348. if (HAS_VEBOX(m->i915))
  349. err_printf(m, " SYNC_2: 0x%08x\n",
  350. ee->semaphore_mboxes[2]);
  351. }
  352. if (USES_PPGTT(m->i915)) {
  353. err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
  354. if (INTEL_GEN(m->i915) >= 8) {
  355. int i;
  356. for (i = 0; i < 4; i++)
  357. err_printf(m, " PDP%d: 0x%016llx\n",
  358. i, ee->vm_info.pdp[i]);
  359. } else {
  360. err_printf(m, " PP_DIR_BASE: 0x%08x\n",
  361. ee->vm_info.pp_dir_base);
  362. }
  363. }
  364. err_printf(m, " seqno: 0x%08x\n", ee->seqno);
  365. err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno);
  366. err_printf(m, " waiting: %s\n", yesno(ee->waiting));
  367. err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head);
  368. err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail);
  369. err_printf(m, " hangcheck stall: %s\n", yesno(ee->hangcheck_stalled));
  370. err_printf(m, " hangcheck action: %s\n",
  371. hangcheck_action_to_str(ee->hangcheck_action));
  372. err_printf(m, " hangcheck action timestamp: %lu, %u ms ago\n",
  373. ee->hangcheck_timestamp,
  374. jiffies_to_msecs(jiffies - ee->hangcheck_timestamp));
  375. error_print_request(m, " ELSP[0]: ", &ee->execlist[0]);
  376. error_print_request(m, " ELSP[1]: ", &ee->execlist[1]);
  377. }
  378. void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
  379. {
  380. va_list args;
  381. va_start(args, f);
  382. i915_error_vprintf(e, f, args);
  383. va_end(args);
  384. }
  385. static int
  386. ascii85_encode_len(int len)
  387. {
  388. return DIV_ROUND_UP(len, 4);
  389. }
  390. static bool
  391. ascii85_encode(u32 in, char *out)
  392. {
  393. int i;
  394. if (in == 0)
  395. return false;
  396. out[5] = '\0';
  397. for (i = 5; i--; ) {
  398. out[i] = '!' + in % 85;
  399. in /= 85;
  400. }
  401. return true;
  402. }
  403. static void print_error_obj(struct drm_i915_error_state_buf *m,
  404. struct intel_engine_cs *engine,
  405. const char *name,
  406. struct drm_i915_error_object *obj)
  407. {
  408. char out[6];
  409. int page;
  410. if (!obj)
  411. return;
  412. if (name) {
  413. err_printf(m, "%s --- %s = 0x%08x %08x\n",
  414. engine ? engine->name : "global", name,
  415. upper_32_bits(obj->gtt_offset),
  416. lower_32_bits(obj->gtt_offset));
  417. }
  418. err_compression_marker(m);
  419. for (page = 0; page < obj->page_count; page++) {
  420. int i, len;
  421. len = PAGE_SIZE;
  422. if (page == obj->page_count - 1)
  423. len -= obj->unused;
  424. len = ascii85_encode_len(len);
  425. for (i = 0; i < len; i++) {
  426. if (ascii85_encode(obj->pages[page][i], out))
  427. err_puts(m, out);
  428. else
  429. err_puts(m, "z");
  430. }
  431. }
  432. err_puts(m, "\n");
  433. }
  434. static void err_print_capabilities(struct drm_i915_error_state_buf *m,
  435. const struct intel_device_info *info)
  436. {
  437. #define PRINT_FLAG(x) err_printf(m, #x ": %s\n", yesno(info->x))
  438. DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  439. #undef PRINT_FLAG
  440. }
  441. int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
  442. const struct i915_error_state_file_priv *error_priv)
  443. {
  444. struct drm_i915_private *dev_priv = error_priv->i915;
  445. struct pci_dev *pdev = dev_priv->drm.pdev;
  446. struct drm_i915_error_state *error = error_priv->error;
  447. struct drm_i915_error_object *obj;
  448. int i, j;
  449. if (!error) {
  450. err_printf(m, "no error state collected\n");
  451. goto out;
  452. }
  453. err_printf(m, "%s\n", error->error_msg);
  454. err_printf(m, "Kernel: " UTS_RELEASE "\n");
  455. err_printf(m, "Time: %ld s %ld us\n",
  456. error->time.tv_sec, error->time.tv_usec);
  457. err_printf(m, "Boottime: %ld s %ld us\n",
  458. error->boottime.tv_sec, error->boottime.tv_usec);
  459. err_printf(m, "Uptime: %ld s %ld us\n",
  460. error->uptime.tv_sec, error->uptime.tv_usec);
  461. err_print_capabilities(m, &error->device_info);
  462. for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
  463. if (error->engine[i].hangcheck_stalled &&
  464. error->engine[i].pid != -1) {
  465. err_printf(m, "Active process (on ring %s): %s [%d], context bans %d\n",
  466. engine_str(i),
  467. error->engine[i].comm,
  468. error->engine[i].pid,
  469. error->engine[i].context_bans);
  470. }
  471. }
  472. err_printf(m, "Reset count: %u\n", error->reset_count);
  473. err_printf(m, "Suspend count: %u\n", error->suspend_count);
  474. err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
  475. err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
  476. err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
  477. err_printf(m, "PCI Subsystem: %04x:%04x\n",
  478. pdev->subsystem_vendor,
  479. pdev->subsystem_device);
  480. err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
  481. if (HAS_CSR(dev_priv)) {
  482. struct intel_csr *csr = &dev_priv->csr;
  483. err_printf(m, "DMC loaded: %s\n",
  484. yesno(csr->dmc_payload != NULL));
  485. err_printf(m, "DMC fw version: %d.%d\n",
  486. CSR_VERSION_MAJOR(csr->version),
  487. CSR_VERSION_MINOR(csr->version));
  488. }
  489. err_printf(m, "EIR: 0x%08x\n", error->eir);
  490. err_printf(m, "IER: 0x%08x\n", error->ier);
  491. if (INTEL_GEN(dev_priv) >= 8) {
  492. for (i = 0; i < 4; i++)
  493. err_printf(m, "GTIER gt %d: 0x%08x\n", i,
  494. error->gtier[i]);
  495. } else if (HAS_PCH_SPLIT(dev_priv) || IS_VALLEYVIEW(dev_priv))
  496. err_printf(m, "GTIER: 0x%08x\n", error->gtier[0]);
  497. err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
  498. err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
  499. err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
  500. err_printf(m, "CCID: 0x%08x\n", error->ccid);
  501. err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
  502. for (i = 0; i < dev_priv->num_fence_regs; i++)
  503. err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
  504. if (INTEL_GEN(dev_priv) >= 6) {
  505. err_printf(m, "ERROR: 0x%08x\n", error->error);
  506. if (INTEL_GEN(dev_priv) >= 8)
  507. err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
  508. error->fault_data1, error->fault_data0);
  509. err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
  510. }
  511. if (IS_GEN7(dev_priv))
  512. err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
  513. for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
  514. if (error->engine[i].engine_id != -1)
  515. error_print_engine(m, &error->engine[i]);
  516. }
  517. for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
  518. char buf[128];
  519. int len, first = 1;
  520. if (!error->active_vm[i])
  521. break;
  522. len = scnprintf(buf, sizeof(buf), "Active (");
  523. for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
  524. if (error->engine[j].vm != error->active_vm[i])
  525. continue;
  526. len += scnprintf(buf + len, sizeof(buf), "%s%s",
  527. first ? "" : ", ",
  528. dev_priv->engine[j]->name);
  529. first = 0;
  530. }
  531. scnprintf(buf + len, sizeof(buf), ")");
  532. print_error_buffers(m, buf,
  533. error->active_bo[i],
  534. error->active_bo_count[i]);
  535. }
  536. print_error_buffers(m, "Pinned (global)",
  537. error->pinned_bo,
  538. error->pinned_bo_count);
  539. for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
  540. struct drm_i915_error_engine *ee = &error->engine[i];
  541. obj = ee->batchbuffer;
  542. if (obj) {
  543. err_puts(m, dev_priv->engine[i]->name);
  544. if (ee->pid != -1)
  545. err_printf(m, " (submitted by %s [%d], bans %d)",
  546. ee->comm,
  547. ee->pid,
  548. ee->context_bans);
  549. err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
  550. upper_32_bits(obj->gtt_offset),
  551. lower_32_bits(obj->gtt_offset));
  552. print_error_obj(m, dev_priv->engine[i], NULL, obj);
  553. }
  554. if (ee->num_requests) {
  555. err_printf(m, "%s --- %d requests\n",
  556. dev_priv->engine[i]->name,
  557. ee->num_requests);
  558. for (j = 0; j < ee->num_requests; j++)
  559. error_print_request(m, " ", &ee->requests[j]);
  560. }
  561. if (IS_ERR(ee->waiters)) {
  562. err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
  563. dev_priv->engine[i]->name);
  564. } else if (ee->num_waiters) {
  565. err_printf(m, "%s --- %d waiters\n",
  566. dev_priv->engine[i]->name,
  567. ee->num_waiters);
  568. for (j = 0; j < ee->num_waiters; j++) {
  569. err_printf(m, " seqno 0x%08x for %s [%d]\n",
  570. ee->waiters[j].seqno,
  571. ee->waiters[j].comm,
  572. ee->waiters[j].pid);
  573. }
  574. }
  575. print_error_obj(m, dev_priv->engine[i],
  576. "ringbuffer", ee->ringbuffer);
  577. print_error_obj(m, dev_priv->engine[i],
  578. "HW Status", ee->hws_page);
  579. print_error_obj(m, dev_priv->engine[i],
  580. "HW context", ee->ctx);
  581. print_error_obj(m, dev_priv->engine[i],
  582. "WA context", ee->wa_ctx);
  583. print_error_obj(m, dev_priv->engine[i],
  584. "WA batchbuffer", ee->wa_batchbuffer);
  585. }
  586. print_error_obj(m, NULL, "Semaphores", error->semaphore);
  587. print_error_obj(m, NULL, "GuC log buffer", error->guc_log);
  588. if (error->overlay)
  589. intel_overlay_print_error_state(m, error->overlay);
  590. if (error->display)
  591. intel_display_print_error_state(m, dev_priv, error->display);
  592. out:
  593. if (m->bytes == 0 && m->err)
  594. return m->err;
  595. return 0;
  596. }
  597. int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
  598. struct drm_i915_private *i915,
  599. size_t count, loff_t pos)
  600. {
  601. memset(ebuf, 0, sizeof(*ebuf));
  602. ebuf->i915 = i915;
  603. /* We need to have enough room to store any i915_error_state printf
  604. * so that we can move it to start position.
  605. */
  606. ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
  607. ebuf->buf = kmalloc(ebuf->size,
  608. GFP_TEMPORARY | __GFP_NORETRY | __GFP_NOWARN);
  609. if (ebuf->buf == NULL) {
  610. ebuf->size = PAGE_SIZE;
  611. ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
  612. }
  613. if (ebuf->buf == NULL) {
  614. ebuf->size = 128;
  615. ebuf->buf = kmalloc(ebuf->size, GFP_TEMPORARY);
  616. }
  617. if (ebuf->buf == NULL)
  618. return -ENOMEM;
  619. ebuf->start = pos;
  620. return 0;
  621. }
  622. static void i915_error_object_free(struct drm_i915_error_object *obj)
  623. {
  624. int page;
  625. if (obj == NULL)
  626. return;
  627. for (page = 0; page < obj->page_count; page++)
  628. free_page((unsigned long)obj->pages[page]);
  629. kfree(obj);
  630. }
  631. static void i915_error_state_free(struct kref *error_ref)
  632. {
  633. struct drm_i915_error_state *error = container_of(error_ref,
  634. typeof(*error), ref);
  635. int i;
  636. for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
  637. struct drm_i915_error_engine *ee = &error->engine[i];
  638. i915_error_object_free(ee->batchbuffer);
  639. i915_error_object_free(ee->wa_batchbuffer);
  640. i915_error_object_free(ee->ringbuffer);
  641. i915_error_object_free(ee->hws_page);
  642. i915_error_object_free(ee->ctx);
  643. i915_error_object_free(ee->wa_ctx);
  644. kfree(ee->requests);
  645. if (!IS_ERR_OR_NULL(ee->waiters))
  646. kfree(ee->waiters);
  647. }
  648. i915_error_object_free(error->semaphore);
  649. i915_error_object_free(error->guc_log);
  650. for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
  651. kfree(error->active_bo[i]);
  652. kfree(error->pinned_bo);
  653. kfree(error->overlay);
  654. kfree(error->display);
  655. kfree(error);
  656. }
  657. static struct drm_i915_error_object *
  658. i915_error_object_create(struct drm_i915_private *i915,
  659. struct i915_vma *vma)
  660. {
  661. struct i915_ggtt *ggtt = &i915->ggtt;
  662. const u64 slot = ggtt->error_capture.start;
  663. struct drm_i915_error_object *dst;
  664. struct compress compress;
  665. unsigned long num_pages;
  666. struct sgt_iter iter;
  667. dma_addr_t dma;
  668. if (!vma)
  669. return NULL;
  670. num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
  671. num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
  672. dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
  673. GFP_ATOMIC | __GFP_NOWARN);
  674. if (!dst)
  675. return NULL;
  676. dst->gtt_offset = vma->node.start;
  677. dst->gtt_size = vma->node.size;
  678. dst->page_count = 0;
  679. dst->unused = 0;
  680. if (!compress_init(&compress)) {
  681. kfree(dst);
  682. return NULL;
  683. }
  684. for_each_sgt_dma(dma, iter, vma->pages) {
  685. void __iomem *s;
  686. int ret;
  687. ggtt->base.insert_page(&ggtt->base, dma, slot,
  688. I915_CACHE_NONE, 0);
  689. s = io_mapping_map_atomic_wc(&ggtt->mappable, slot);
  690. ret = compress_page(&compress, (void __force *)s, dst);
  691. io_mapping_unmap_atomic(s);
  692. if (ret)
  693. goto unwind;
  694. }
  695. goto out;
  696. unwind:
  697. while (dst->page_count--)
  698. free_page((unsigned long)dst->pages[dst->page_count]);
  699. kfree(dst);
  700. dst = NULL;
  701. out:
  702. compress_fini(&compress, dst);
  703. ggtt->base.clear_range(&ggtt->base, slot, PAGE_SIZE);
  704. return dst;
  705. }
  706. /* The error capture is special as tries to run underneath the normal
  707. * locking rules - so we use the raw version of the i915_gem_active lookup.
  708. */
  709. static inline uint32_t
  710. __active_get_seqno(struct i915_gem_active *active)
  711. {
  712. struct drm_i915_gem_request *request;
  713. request = __i915_gem_active_peek(active);
  714. return request ? request->global_seqno : 0;
  715. }
  716. static inline int
  717. __active_get_engine_id(struct i915_gem_active *active)
  718. {
  719. struct drm_i915_gem_request *request;
  720. request = __i915_gem_active_peek(active);
  721. return request ? request->engine->id : -1;
  722. }
  723. static void capture_bo(struct drm_i915_error_buffer *err,
  724. struct i915_vma *vma)
  725. {
  726. struct drm_i915_gem_object *obj = vma->obj;
  727. int i;
  728. err->size = obj->base.size;
  729. err->name = obj->base.name;
  730. for (i = 0; i < I915_NUM_ENGINES; i++)
  731. err->rseqno[i] = __active_get_seqno(&vma->last_read[i]);
  732. err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
  733. err->engine = __active_get_engine_id(&obj->frontbuffer_write);
  734. err->gtt_offset = vma->node.start;
  735. err->read_domains = obj->base.read_domains;
  736. err->write_domain = obj->base.write_domain;
  737. err->fence_reg = vma->fence ? vma->fence->id : -1;
  738. err->tiling = i915_gem_object_get_tiling(obj);
  739. err->dirty = obj->mm.dirty;
  740. err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
  741. err->userptr = obj->userptr.mm != NULL;
  742. err->cache_level = obj->cache_level;
  743. }
  744. static u32 capture_error_bo(struct drm_i915_error_buffer *err,
  745. int count, struct list_head *head,
  746. bool pinned_only)
  747. {
  748. struct i915_vma *vma;
  749. int i = 0;
  750. list_for_each_entry(vma, head, vm_link) {
  751. if (pinned_only && !i915_vma_is_pinned(vma))
  752. continue;
  753. capture_bo(err++, vma);
  754. if (++i == count)
  755. break;
  756. }
  757. return i;
  758. }
  759. /* Generate a semi-unique error code. The code is not meant to have meaning, The
  760. * code's only purpose is to try to prevent false duplicated bug reports by
  761. * grossly estimating a GPU error state.
  762. *
  763. * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
  764. * the hang if we could strip the GTT offset information from it.
  765. *
  766. * It's only a small step better than a random number in its current form.
  767. */
  768. static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
  769. struct drm_i915_error_state *error,
  770. int *engine_id)
  771. {
  772. uint32_t error_code = 0;
  773. int i;
  774. /* IPEHR would be an ideal way to detect errors, as it's the gross
  775. * measure of "the command that hung." However, has some very common
  776. * synchronization commands which almost always appear in the case
  777. * strictly a client bug. Use instdone to differentiate those some.
  778. */
  779. for (i = 0; i < I915_NUM_ENGINES; i++) {
  780. if (error->engine[i].hangcheck_stalled) {
  781. if (engine_id)
  782. *engine_id = i;
  783. return error->engine[i].ipehr ^
  784. error->engine[i].instdone.instdone;
  785. }
  786. }
  787. return error_code;
  788. }
  789. static void i915_gem_record_fences(struct drm_i915_private *dev_priv,
  790. struct drm_i915_error_state *error)
  791. {
  792. int i;
  793. if (IS_GEN3(dev_priv) || IS_GEN2(dev_priv)) {
  794. for (i = 0; i < dev_priv->num_fence_regs; i++)
  795. error->fence[i] = I915_READ(FENCE_REG(i));
  796. } else if (IS_GEN5(dev_priv) || IS_GEN4(dev_priv)) {
  797. for (i = 0; i < dev_priv->num_fence_regs; i++)
  798. error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
  799. } else if (INTEL_GEN(dev_priv) >= 6) {
  800. for (i = 0; i < dev_priv->num_fence_regs; i++)
  801. error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
  802. }
  803. }
  804. static inline u32
  805. gen8_engine_sync_index(struct intel_engine_cs *engine,
  806. struct intel_engine_cs *other)
  807. {
  808. int idx;
  809. /*
  810. * rcs -> 0 = vcs, 1 = bcs, 2 = vecs, 3 = vcs2;
  811. * vcs -> 0 = bcs, 1 = vecs, 2 = vcs2, 3 = rcs;
  812. * bcs -> 0 = vecs, 1 = vcs2. 2 = rcs, 3 = vcs;
  813. * vecs -> 0 = vcs2, 1 = rcs, 2 = vcs, 3 = bcs;
  814. * vcs2 -> 0 = rcs, 1 = vcs, 2 = bcs, 3 = vecs;
  815. */
  816. idx = (other - engine) - 1;
  817. if (idx < 0)
  818. idx += I915_NUM_ENGINES;
  819. return idx;
  820. }
  821. static void gen8_record_semaphore_state(struct drm_i915_error_state *error,
  822. struct intel_engine_cs *engine,
  823. struct drm_i915_error_engine *ee)
  824. {
  825. struct drm_i915_private *dev_priv = engine->i915;
  826. struct intel_engine_cs *to;
  827. enum intel_engine_id id;
  828. if (!error->semaphore)
  829. return;
  830. for_each_engine(to, dev_priv, id) {
  831. int idx;
  832. u16 signal_offset;
  833. u32 *tmp;
  834. if (engine == to)
  835. continue;
  836. signal_offset =
  837. (GEN8_SIGNAL_OFFSET(engine, id) & (PAGE_SIZE - 1)) / 4;
  838. tmp = error->semaphore->pages[0];
  839. idx = gen8_engine_sync_index(engine, to);
  840. ee->semaphore_mboxes[idx] = tmp[signal_offset];
  841. }
  842. }
  843. static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
  844. struct drm_i915_error_engine *ee)
  845. {
  846. struct drm_i915_private *dev_priv = engine->i915;
  847. ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
  848. ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
  849. if (HAS_VEBOX(dev_priv))
  850. ee->semaphore_mboxes[2] =
  851. I915_READ(RING_SYNC_2(engine->mmio_base));
  852. }
  853. static void error_record_engine_waiters(struct intel_engine_cs *engine,
  854. struct drm_i915_error_engine *ee)
  855. {
  856. struct intel_breadcrumbs *b = &engine->breadcrumbs;
  857. struct drm_i915_error_waiter *waiter;
  858. struct rb_node *rb;
  859. int count;
  860. ee->num_waiters = 0;
  861. ee->waiters = NULL;
  862. if (RB_EMPTY_ROOT(&b->waiters))
  863. return;
  864. if (!spin_trylock_irq(&b->lock)) {
  865. ee->waiters = ERR_PTR(-EDEADLK);
  866. return;
  867. }
  868. count = 0;
  869. for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
  870. count++;
  871. spin_unlock_irq(&b->lock);
  872. waiter = NULL;
  873. if (count)
  874. waiter = kmalloc_array(count,
  875. sizeof(struct drm_i915_error_waiter),
  876. GFP_ATOMIC);
  877. if (!waiter)
  878. return;
  879. if (!spin_trylock_irq(&b->lock)) {
  880. kfree(waiter);
  881. ee->waiters = ERR_PTR(-EDEADLK);
  882. return;
  883. }
  884. ee->waiters = waiter;
  885. for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
  886. struct intel_wait *w = container_of(rb, typeof(*w), node);
  887. strcpy(waiter->comm, w->tsk->comm);
  888. waiter->pid = w->tsk->pid;
  889. waiter->seqno = w->seqno;
  890. waiter++;
  891. if (++ee->num_waiters == count)
  892. break;
  893. }
  894. spin_unlock_irq(&b->lock);
  895. }
  896. static void error_record_engine_registers(struct drm_i915_error_state *error,
  897. struct intel_engine_cs *engine,
  898. struct drm_i915_error_engine *ee)
  899. {
  900. struct drm_i915_private *dev_priv = engine->i915;
  901. if (INTEL_GEN(dev_priv) >= 6) {
  902. ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
  903. ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
  904. if (INTEL_GEN(dev_priv) >= 8)
  905. gen8_record_semaphore_state(error, engine, ee);
  906. else
  907. gen6_record_semaphore_state(engine, ee);
  908. }
  909. if (INTEL_GEN(dev_priv) >= 4) {
  910. ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
  911. ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
  912. ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
  913. ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
  914. ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
  915. if (INTEL_GEN(dev_priv) >= 8) {
  916. ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
  917. ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
  918. }
  919. ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
  920. } else {
  921. ee->faddr = I915_READ(DMA_FADD_I8XX);
  922. ee->ipeir = I915_READ(IPEIR);
  923. ee->ipehr = I915_READ(IPEHR);
  924. }
  925. intel_engine_get_instdone(engine, &ee->instdone);
  926. ee->waiting = intel_engine_has_waiter(engine);
  927. ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
  928. ee->acthd = intel_engine_get_active_head(engine);
  929. ee->seqno = intel_engine_get_seqno(engine);
  930. ee->last_seqno = intel_engine_last_submit(engine);
  931. ee->start = I915_READ_START(engine);
  932. ee->head = I915_READ_HEAD(engine);
  933. ee->tail = I915_READ_TAIL(engine);
  934. ee->ctl = I915_READ_CTL(engine);
  935. if (INTEL_GEN(dev_priv) > 2)
  936. ee->mode = I915_READ_MODE(engine);
  937. if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
  938. i915_reg_t mmio;
  939. if (IS_GEN7(dev_priv)) {
  940. switch (engine->id) {
  941. default:
  942. case RCS:
  943. mmio = RENDER_HWS_PGA_GEN7;
  944. break;
  945. case BCS:
  946. mmio = BLT_HWS_PGA_GEN7;
  947. break;
  948. case VCS:
  949. mmio = BSD_HWS_PGA_GEN7;
  950. break;
  951. case VECS:
  952. mmio = VEBOX_HWS_PGA_GEN7;
  953. break;
  954. }
  955. } else if (IS_GEN6(engine->i915)) {
  956. mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
  957. } else {
  958. /* XXX: gen8 returns to sanity */
  959. mmio = RING_HWS_PGA(engine->mmio_base);
  960. }
  961. ee->hws = I915_READ(mmio);
  962. }
  963. ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
  964. ee->hangcheck_action = engine->hangcheck.action;
  965. ee->hangcheck_stalled = engine->hangcheck.stalled;
  966. if (USES_PPGTT(dev_priv)) {
  967. int i;
  968. ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
  969. if (IS_GEN6(dev_priv))
  970. ee->vm_info.pp_dir_base =
  971. I915_READ(RING_PP_DIR_BASE_READ(engine));
  972. else if (IS_GEN7(dev_priv))
  973. ee->vm_info.pp_dir_base =
  974. I915_READ(RING_PP_DIR_BASE(engine));
  975. else if (INTEL_GEN(dev_priv) >= 8)
  976. for (i = 0; i < 4; i++) {
  977. ee->vm_info.pdp[i] =
  978. I915_READ(GEN8_RING_PDP_UDW(engine, i));
  979. ee->vm_info.pdp[i] <<= 32;
  980. ee->vm_info.pdp[i] |=
  981. I915_READ(GEN8_RING_PDP_LDW(engine, i));
  982. }
  983. }
  984. }
  985. static void record_request(struct drm_i915_gem_request *request,
  986. struct drm_i915_error_request *erq)
  987. {
  988. erq->context = request->ctx->hw_id;
  989. erq->ban_score = request->ctx->ban_score;
  990. erq->seqno = request->global_seqno;
  991. erq->jiffies = request->emitted_jiffies;
  992. erq->head = request->head;
  993. erq->tail = request->tail;
  994. rcu_read_lock();
  995. erq->pid = request->ctx->pid ? pid_nr(request->ctx->pid) : 0;
  996. rcu_read_unlock();
  997. }
  998. static void engine_record_requests(struct intel_engine_cs *engine,
  999. struct drm_i915_gem_request *first,
  1000. struct drm_i915_error_engine *ee)
  1001. {
  1002. struct drm_i915_gem_request *request;
  1003. int count;
  1004. count = 0;
  1005. request = first;
  1006. list_for_each_entry_from(request, &engine->timeline->requests, link)
  1007. count++;
  1008. if (!count)
  1009. return;
  1010. ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
  1011. if (!ee->requests)
  1012. return;
  1013. ee->num_requests = count;
  1014. count = 0;
  1015. request = first;
  1016. list_for_each_entry_from(request, &engine->timeline->requests, link) {
  1017. if (count >= ee->num_requests) {
  1018. /*
  1019. * If the ring request list was changed in
  1020. * between the point where the error request
  1021. * list was created and dimensioned and this
  1022. * point then just exit early to avoid crashes.
  1023. *
  1024. * We don't need to communicate that the
  1025. * request list changed state during error
  1026. * state capture and that the error state is
  1027. * slightly incorrect as a consequence since we
  1028. * are typically only interested in the request
  1029. * list state at the point of error state
  1030. * capture, not in any changes happening during
  1031. * the capture.
  1032. */
  1033. break;
  1034. }
  1035. record_request(request, &ee->requests[count++]);
  1036. }
  1037. ee->num_requests = count;
  1038. }
  1039. static void error_record_engine_execlists(struct intel_engine_cs *engine,
  1040. struct drm_i915_error_engine *ee)
  1041. {
  1042. unsigned int n;
  1043. for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++)
  1044. if (engine->execlist_port[n].request)
  1045. record_request(engine->execlist_port[n].request,
  1046. &ee->execlist[n]);
  1047. }
  1048. static void i915_gem_record_rings(struct drm_i915_private *dev_priv,
  1049. struct drm_i915_error_state *error)
  1050. {
  1051. struct i915_ggtt *ggtt = &dev_priv->ggtt;
  1052. int i;
  1053. error->semaphore =
  1054. i915_error_object_create(dev_priv, dev_priv->semaphore);
  1055. for (i = 0; i < I915_NUM_ENGINES; i++) {
  1056. struct intel_engine_cs *engine = dev_priv->engine[i];
  1057. struct drm_i915_error_engine *ee = &error->engine[i];
  1058. struct drm_i915_gem_request *request;
  1059. ee->pid = -1;
  1060. ee->engine_id = -1;
  1061. if (!engine)
  1062. continue;
  1063. ee->engine_id = i;
  1064. error_record_engine_registers(error, engine, ee);
  1065. error_record_engine_waiters(engine, ee);
  1066. error_record_engine_execlists(engine, ee);
  1067. request = i915_gem_find_active_request(engine);
  1068. if (request) {
  1069. struct intel_ring *ring;
  1070. struct pid *pid;
  1071. ee->vm = request->ctx->ppgtt ?
  1072. &request->ctx->ppgtt->base : &ggtt->base;
  1073. /* We need to copy these to an anonymous buffer
  1074. * as the simplest method to avoid being overwritten
  1075. * by userspace.
  1076. */
  1077. ee->batchbuffer =
  1078. i915_error_object_create(dev_priv,
  1079. request->batch);
  1080. if (HAS_BROKEN_CS_TLB(dev_priv))
  1081. ee->wa_batchbuffer =
  1082. i915_error_object_create(dev_priv,
  1083. engine->scratch);
  1084. ee->ctx =
  1085. i915_error_object_create(dev_priv,
  1086. request->ctx->engine[i].state);
  1087. pid = request->ctx->pid;
  1088. if (pid) {
  1089. struct task_struct *task;
  1090. rcu_read_lock();
  1091. task = pid_task(pid, PIDTYPE_PID);
  1092. if (task) {
  1093. strcpy(ee->comm, task->comm);
  1094. ee->pid = task->pid;
  1095. }
  1096. rcu_read_unlock();
  1097. }
  1098. error->simulated |=
  1099. i915_gem_context_no_error_capture(request->ctx);
  1100. ee->rq_head = request->head;
  1101. ee->rq_post = request->postfix;
  1102. ee->rq_tail = request->tail;
  1103. ring = request->ring;
  1104. ee->cpu_ring_head = ring->head;
  1105. ee->cpu_ring_tail = ring->tail;
  1106. ee->ringbuffer =
  1107. i915_error_object_create(dev_priv, ring->vma);
  1108. engine_record_requests(engine, request, ee);
  1109. }
  1110. ee->hws_page =
  1111. i915_error_object_create(dev_priv,
  1112. engine->status_page.vma);
  1113. ee->wa_ctx =
  1114. i915_error_object_create(dev_priv, engine->wa_ctx.vma);
  1115. }
  1116. }
  1117. static void i915_gem_capture_vm(struct drm_i915_private *dev_priv,
  1118. struct drm_i915_error_state *error,
  1119. struct i915_address_space *vm,
  1120. int idx)
  1121. {
  1122. struct drm_i915_error_buffer *active_bo;
  1123. struct i915_vma *vma;
  1124. int count;
  1125. count = 0;
  1126. list_for_each_entry(vma, &vm->active_list, vm_link)
  1127. count++;
  1128. active_bo = NULL;
  1129. if (count)
  1130. active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
  1131. if (active_bo)
  1132. count = capture_error_bo(active_bo, count, &vm->active_list, false);
  1133. else
  1134. count = 0;
  1135. error->active_vm[idx] = vm;
  1136. error->active_bo[idx] = active_bo;
  1137. error->active_bo_count[idx] = count;
  1138. }
  1139. static void i915_capture_active_buffers(struct drm_i915_private *dev_priv,
  1140. struct drm_i915_error_state *error)
  1141. {
  1142. int cnt = 0, i, j;
  1143. BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
  1144. BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
  1145. BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
  1146. /* Scan each engine looking for unique active contexts/vm */
  1147. for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
  1148. struct drm_i915_error_engine *ee = &error->engine[i];
  1149. bool found;
  1150. if (!ee->vm)
  1151. continue;
  1152. found = false;
  1153. for (j = 0; j < i && !found; j++)
  1154. found = error->engine[j].vm == ee->vm;
  1155. if (!found)
  1156. i915_gem_capture_vm(dev_priv, error, ee->vm, cnt++);
  1157. }
  1158. }
  1159. static void i915_capture_pinned_buffers(struct drm_i915_private *dev_priv,
  1160. struct drm_i915_error_state *error)
  1161. {
  1162. struct i915_address_space *vm = &dev_priv->ggtt.base;
  1163. struct drm_i915_error_buffer *bo;
  1164. struct i915_vma *vma;
  1165. int count_inactive, count_active;
  1166. count_inactive = 0;
  1167. list_for_each_entry(vma, &vm->active_list, vm_link)
  1168. count_inactive++;
  1169. count_active = 0;
  1170. list_for_each_entry(vma, &vm->inactive_list, vm_link)
  1171. count_active++;
  1172. bo = NULL;
  1173. if (count_inactive + count_active)
  1174. bo = kcalloc(count_inactive + count_active,
  1175. sizeof(*bo), GFP_ATOMIC);
  1176. if (!bo)
  1177. return;
  1178. count_inactive = capture_error_bo(bo, count_inactive,
  1179. &vm->active_list, true);
  1180. count_active = capture_error_bo(bo + count_inactive, count_active,
  1181. &vm->inactive_list, true);
  1182. error->pinned_bo_count = count_inactive + count_active;
  1183. error->pinned_bo = bo;
  1184. }
  1185. static void i915_gem_capture_guc_log_buffer(struct drm_i915_private *dev_priv,
  1186. struct drm_i915_error_state *error)
  1187. {
  1188. /* Capturing log buf contents won't be useful if logging was disabled */
  1189. if (!dev_priv->guc.log.vma || (i915.guc_log_level < 0))
  1190. return;
  1191. error->guc_log = i915_error_object_create(dev_priv,
  1192. dev_priv->guc.log.vma);
  1193. }
  1194. /* Capture all registers which don't fit into another category. */
  1195. static void i915_capture_reg_state(struct drm_i915_private *dev_priv,
  1196. struct drm_i915_error_state *error)
  1197. {
  1198. int i;
  1199. /* General organization
  1200. * 1. Registers specific to a single generation
  1201. * 2. Registers which belong to multiple generations
  1202. * 3. Feature specific registers.
  1203. * 4. Everything else
  1204. * Please try to follow the order.
  1205. */
  1206. /* 1: Registers specific to a single generation */
  1207. if (IS_VALLEYVIEW(dev_priv)) {
  1208. error->gtier[0] = I915_READ(GTIER);
  1209. error->ier = I915_READ(VLV_IER);
  1210. error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
  1211. }
  1212. if (IS_GEN7(dev_priv))
  1213. error->err_int = I915_READ(GEN7_ERR_INT);
  1214. if (INTEL_GEN(dev_priv) >= 8) {
  1215. error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
  1216. error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
  1217. }
  1218. if (IS_GEN6(dev_priv)) {
  1219. error->forcewake = I915_READ_FW(FORCEWAKE);
  1220. error->gab_ctl = I915_READ(GAB_CTL);
  1221. error->gfx_mode = I915_READ(GFX_MODE);
  1222. }
  1223. /* 2: Registers which belong to multiple generations */
  1224. if (INTEL_GEN(dev_priv) >= 7)
  1225. error->forcewake = I915_READ_FW(FORCEWAKE_MT);
  1226. if (INTEL_GEN(dev_priv) >= 6) {
  1227. error->derrmr = I915_READ(DERRMR);
  1228. error->error = I915_READ(ERROR_GEN6);
  1229. error->done_reg = I915_READ(DONE_REG);
  1230. }
  1231. /* 3: Feature specific registers */
  1232. if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
  1233. error->gam_ecochk = I915_READ(GAM_ECOCHK);
  1234. error->gac_eco = I915_READ(GAC_ECO_BITS);
  1235. }
  1236. /* 4: Everything else */
  1237. if (HAS_HW_CONTEXTS(dev_priv))
  1238. error->ccid = I915_READ(CCID);
  1239. if (INTEL_GEN(dev_priv) >= 8) {
  1240. error->ier = I915_READ(GEN8_DE_MISC_IER);
  1241. for (i = 0; i < 4; i++)
  1242. error->gtier[i] = I915_READ(GEN8_GT_IER(i));
  1243. } else if (HAS_PCH_SPLIT(dev_priv)) {
  1244. error->ier = I915_READ(DEIER);
  1245. error->gtier[0] = I915_READ(GTIER);
  1246. } else if (IS_GEN2(dev_priv)) {
  1247. error->ier = I915_READ16(IER);
  1248. } else if (!IS_VALLEYVIEW(dev_priv)) {
  1249. error->ier = I915_READ(IER);
  1250. }
  1251. error->eir = I915_READ(EIR);
  1252. error->pgtbl_er = I915_READ(PGTBL_ER);
  1253. }
  1254. static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
  1255. struct drm_i915_error_state *error,
  1256. u32 engine_mask,
  1257. const char *error_msg)
  1258. {
  1259. u32 ecode;
  1260. int engine_id = -1, len;
  1261. ecode = i915_error_generate_code(dev_priv, error, &engine_id);
  1262. len = scnprintf(error->error_msg, sizeof(error->error_msg),
  1263. "GPU HANG: ecode %d:%d:0x%08x",
  1264. INTEL_GEN(dev_priv), engine_id, ecode);
  1265. if (engine_id != -1 && error->engine[engine_id].pid != -1)
  1266. len += scnprintf(error->error_msg + len,
  1267. sizeof(error->error_msg) - len,
  1268. ", in %s [%d]",
  1269. error->engine[engine_id].comm,
  1270. error->engine[engine_id].pid);
  1271. scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
  1272. ", reason: %s, action: %s",
  1273. error_msg,
  1274. engine_mask ? "reset" : "continue");
  1275. }
  1276. static void i915_capture_gen_state(struct drm_i915_private *dev_priv,
  1277. struct drm_i915_error_state *error)
  1278. {
  1279. error->iommu = -1;
  1280. #ifdef CONFIG_INTEL_IOMMU
  1281. error->iommu = intel_iommu_gfx_mapped;
  1282. #endif
  1283. error->reset_count = i915_reset_count(&dev_priv->gpu_error);
  1284. error->suspend_count = dev_priv->suspend_count;
  1285. memcpy(&error->device_info,
  1286. INTEL_INFO(dev_priv),
  1287. sizeof(error->device_info));
  1288. }
  1289. static int capture(void *data)
  1290. {
  1291. struct drm_i915_error_state *error = data;
  1292. i915_capture_gen_state(error->i915, error);
  1293. i915_capture_reg_state(error->i915, error);
  1294. i915_gem_record_fences(error->i915, error);
  1295. i915_gem_record_rings(error->i915, error);
  1296. i915_capture_active_buffers(error->i915, error);
  1297. i915_capture_pinned_buffers(error->i915, error);
  1298. i915_gem_capture_guc_log_buffer(error->i915, error);
  1299. do_gettimeofday(&error->time);
  1300. error->boottime = ktime_to_timeval(ktime_get_boottime());
  1301. error->uptime =
  1302. ktime_to_timeval(ktime_sub(ktime_get(),
  1303. error->i915->gt.last_init_time));
  1304. error->overlay = intel_overlay_capture_error_state(error->i915);
  1305. error->display = intel_display_capture_error_state(error->i915);
  1306. return 0;
  1307. }
  1308. #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
  1309. /**
  1310. * i915_capture_error_state - capture an error record for later analysis
  1311. * @dev: drm device
  1312. *
  1313. * Should be called when an error is detected (either a hang or an error
  1314. * interrupt) to capture error state from the time of the error. Fills
  1315. * out a structure which becomes available in debugfs for user level tools
  1316. * to pick up.
  1317. */
  1318. void i915_capture_error_state(struct drm_i915_private *dev_priv,
  1319. u32 engine_mask,
  1320. const char *error_msg)
  1321. {
  1322. static bool warned;
  1323. struct drm_i915_error_state *error;
  1324. unsigned long flags;
  1325. if (!i915.error_capture)
  1326. return;
  1327. if (READ_ONCE(dev_priv->gpu_error.first_error))
  1328. return;
  1329. /* Account for pipe specific data like PIPE*STAT */
  1330. error = kzalloc(sizeof(*error), GFP_ATOMIC);
  1331. if (!error) {
  1332. DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
  1333. return;
  1334. }
  1335. kref_init(&error->ref);
  1336. error->i915 = dev_priv;
  1337. stop_machine(capture, error, NULL);
  1338. i915_error_capture_msg(dev_priv, error, engine_mask, error_msg);
  1339. DRM_INFO("%s\n", error->error_msg);
  1340. if (!error->simulated) {
  1341. spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
  1342. if (!dev_priv->gpu_error.first_error) {
  1343. dev_priv->gpu_error.first_error = error;
  1344. error = NULL;
  1345. }
  1346. spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
  1347. }
  1348. if (error) {
  1349. i915_error_state_free(&error->ref);
  1350. return;
  1351. }
  1352. if (!warned &&
  1353. ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
  1354. DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
  1355. DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
  1356. DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
  1357. DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
  1358. DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
  1359. dev_priv->drm.primary->index);
  1360. warned = true;
  1361. }
  1362. }
  1363. void i915_error_state_get(struct drm_device *dev,
  1364. struct i915_error_state_file_priv *error_priv)
  1365. {
  1366. struct drm_i915_private *dev_priv = to_i915(dev);
  1367. spin_lock_irq(&dev_priv->gpu_error.lock);
  1368. error_priv->error = dev_priv->gpu_error.first_error;
  1369. if (error_priv->error)
  1370. kref_get(&error_priv->error->ref);
  1371. spin_unlock_irq(&dev_priv->gpu_error.lock);
  1372. }
  1373. void i915_error_state_put(struct i915_error_state_file_priv *error_priv)
  1374. {
  1375. if (error_priv->error)
  1376. kref_put(&error_priv->error->ref, i915_error_state_free);
  1377. }
  1378. void i915_destroy_error_state(struct drm_i915_private *dev_priv)
  1379. {
  1380. struct drm_i915_error_state *error;
  1381. spin_lock_irq(&dev_priv->gpu_error.lock);
  1382. error = dev_priv->gpu_error.first_error;
  1383. dev_priv->gpu_error.first_error = NULL;
  1384. spin_unlock_irq(&dev_priv->gpu_error.lock);
  1385. if (error)
  1386. kref_put(&error->ref, i915_error_state_free);
  1387. }