/dts/arm/st/g4/stm32g4.dtsi

https://github.com/methodpark/zephyr · Device Tree · 488 lines · 420 code · 60 blank · 8 comment · 0 complexity · 881cbbddc642c7b2ac05148cd7ff052a MD5 · raw file 

    

  1. /*
    2. 

  2.  * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
    3. 

  3.  *
    4. 

  4.  * SPDX-License-Identifier: Apache-2.0
    5. 

  5.  */
    6. 

  6. 

  7. 

  8. #include <arm/armv7-m.dtsi>
    9. 

  9. #include <dt-bindings/clock/stm32_clock.h>
    10. 

  10. #include <dt-bindings/i2c/i2c.h>
    11. 

  11. #include <dt-bindings/gpio/gpio.h>
    12. 

  12. 

  13. / {
    14. 

  14. 	chosen {
    15. 

  15. 		zephyr,entropy = &rng;
    16. 

  16. 		zephyr,flash-controller = &flash;
    17. 

  17. 	};
    18. 

  18. 

  19. 	cpus {
    20. 

  20. 		#address-cells = <1>;
    21. 

  21. 		#size-cells = <0>;
    22. 

  22. 

  23. 		cpu@0 {
    24. 

  24. 			device_type = "cpu";
    25. 

  25. 			compatible = "arm,cortex-m4f";
    26. 

  26. 			reg = <0>;
    27. 

  27. 		};
    28. 

  28. 	};
    29. 

  29. 

  30. 	sram0: memory@20000000 {
    31. 

  31. 		compatible = "mmio-sram";
    32. 

  32. 	};
    33. 

  33. 

  34. 	soc {
    35. 

  35. 		/*
    36. 

  36. 		 * Both adc instances cannot be used in parallel right now.
    37. 

  37. 		 */
    38. 

  38. 		adc1: adc@50000000 {
    39. 

  39. 			compatible = "st,stm32-adc";
    40. 

  40. 			reg = <0x50000000 0x100>;
    41. 

  41. 			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
    42. 

  42. 			interrupts = <18 0>;
    43. 

  43. 			status = "disabled";
    44. 

  44. 			label = "ADC_1";
    45. 

  45. 			#io-channel-cells = <1>;
    46. 

  46. 		};
    47. 

  47. 

  48. 		adc2: adc@50000100 {
    49. 

  49. 			compatible = "st,stm32-adc";
    50. 

  50. 			reg = <0x50000100 0x100>;
    51. 

  51. 			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00002000>;
    52. 

  52. 			interrupts = <18 0>;
    53. 

  53. 			status = "disabled";
    54. 

  54. 			label = "ADC_2";
    55. 

  55. 			#io-channel-cells = <1>;
    56. 

  56. 		};
    57. 

  57. 

  58. 		flash: flash-controller@40022000 {
    59. 

  59. 			compatible = "st,stm32-flash-controller", "st,stm32g4-flash-controller";
    60. 

  60. 			label = "FLASH_CTRL";
    61. 

  61. 			reg = <0x40022000 0x400>;
    62. 

  62. 			interrupts = <3 0>;
    63. 

  63. 

  64. 			#address-cells = <1>;
    65. 

  65. 			#size-cells = <1>;
    66. 

  66. 

  67. 			flash0: flash@8000000 {
    68. 

  68. 				compatible = "soc-nv-flash";
    69. 

  69. 				label = "FLASH_STM32";
    70. 

  70. 

  71. 				write-block-size = <8>;
    72. 

  72. 				erase-block-size = <2048>;
    73. 

  73. 			};
    74. 

  74. 		};
    75. 

  75. 

  76. 		rcc: rcc@40021000 {
    77. 

  77. 			compatible = "st,stm32-rcc";
    78. 

  78. 			#clock-cells = <2>;
    79. 

  79. 			reg = <0x40021000 0x400>;
    80. 

  80. 			label = "STM32_CLK_RCC";
    81. 

  81. 		};
    82. 

  82. 

  83. 		pinctrl: pin-controller@48000000 {
    84. 

  84. 			compatible = "st,stm32-pinmux";
    85. 

  85. 			#address-cells = <1>;
    86. 

  86. 			#size-cells = <1>;
    87. 

  87. 			reg = <0x48000000 0x2000>;
    88. 

  88. 

  89. 			gpioa: gpio@48000000 {
    90. 

  90. 				compatible = "st,stm32-gpio";
    91. 

  91. 				gpio-controller;
    92. 

  92. 				#gpio-cells = <2>;
    93. 

  93. 				reg = <0x48000000 0x400>;
    94. 

  94. 				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000001>;
    95. 

  95. 				label = "GPIOA";
    96. 

  96. 			};
    97. 

  97. 

  98. 			gpiob: gpio@48000400 {
    99. 

  99. 				compatible = "st,stm32-gpio";
    100. 

  100. 				gpio-controller;
    101. 

  101. 				#gpio-cells = <2>;
    102. 

  102. 				reg = <0x48000400 0x400>;
    103. 

  103. 				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000002>;
    104. 

  104. 				label = "GPIOB";
    105. 

  105. 			};
    106. 

  106. 

  107. 			gpioc: gpio@48000800 {
    108. 

  108. 				compatible = "st,stm32-gpio";
    109. 

  109. 				gpio-controller;
    110. 

  110. 				#gpio-cells = <2>;
    111. 

  111. 				reg = <0x48000800 0x400>;
    112. 

  112. 				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000004>;
    113. 

  113. 				label = "GPIOC";
    114. 

  114. 			};
    115. 

  115. 

  116. 			gpiod: gpio@48000c00 {
    117. 

  117. 				compatible = "st,stm32-gpio";
    118. 

  118. 				gpio-controller;
    119. 

  119. 				#gpio-cells = <2>;
    120. 

  120. 				reg = <0x48000c00 0x400>;
    121. 

  121. 				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000008>;
    122. 

  122. 				label = "GPIOD";
    123. 

  123. 			};
    124. 

  124. 

  125. 			gpioe: gpio@48001000 {
    126. 

  126. 				compatible = "st,stm32-gpio";
    127. 

  127. 				gpio-controller;
    128. 

  128. 				#gpio-cells = <2>;
    129. 

  129. 				reg = <0x48001000 0x400>;
    130. 

  130. 				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
    131. 

  131. 				label = "GPIOE";
    132. 

  132. 			};
    133. 

  133. 

  134. 			gpiof: gpio@48001400 {
    135. 

  135. 				compatible = "st,stm32-gpio";
    136. 

  136. 				gpio-controller;
    137. 

  137. 				#gpio-cells = <2>;
    138. 

  138. 				reg = <0x48001400 0x400>;
    139. 

  139. 				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000020>;
    140. 

  140. 				label = "GPIOF";
    141. 

  141. 			};
    142. 

  142. 

  143. 			gpiog: gpio@48001800 {
    144. 

  144. 				compatible = "st,stm32-gpio";
    145. 

  145. 				gpio-controller;
    146. 

  146. 				#gpio-cells = <2>;
    147. 

  147. 				reg = <0x48001800 0x400>;
    148. 

  148. 				clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
    149. 

  149. 				label = "GPIOG";
    150. 

  150. 			};
    151. 

  151. 		};
    152. 

  152. 

  153. 		usart1: serial@40013800 {
    154. 

  154. 			compatible = "st,stm32-usart", "st,stm32-uart";
    155. 

  155. 			reg = <0x40013800 0x400>;
    156. 

  156. 			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
    157. 

  157. 			interrupts = <37 0>;
    158. 

  158. 			status = "disabled";
    159. 

  159. 			label = "UART_1";
    160. 

  160. 		};
    161. 

  161. 

  162. 		usart2: serial@40004400 {
    163. 

  163. 			compatible = "st,stm32-usart", "st,stm32-uart";
    164. 

  164. 			reg = <0x40004400 0x400>;
    165. 

  165. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
    166. 

  166. 			interrupts = <38 0>;
    167. 

  167. 			status = "disabled";
    168. 

  168. 			label = "UART_2";
    169. 

  169. 		};
    170. 

  170. 

  171. 		usart3: serial@40004800 {
    172. 

  172. 			compatible = "st,stm32-usart", "st,stm32-uart";
    173. 

  173. 			reg = <0x40004800 0x400>;
    174. 

  174. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
    175. 

  175. 			interrupts = <39 0>;
    176. 

  176. 			status = "disabled";
    177. 

  177. 			label = "UART_3";
    178. 

  178. 		};
    179. 

  179. 

  180. 		uart4: serial@40004c00 {
    181. 

  181. 			compatible = "st,stm32-uart";
    182. 

  182. 			reg = <0x40004c00 0x400>;
    183. 

  183. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
    184. 

  184. 			interrupts = <52 0>;
    185. 

  185. 			status = "disabled";
    186. 

  186. 			label = "UART_4";
    187. 

  187. 		};
    188. 

  188. 

  189. 		lpuart1: serial@40008000 {
    190. 

  190. 			compatible = "st,stm32-lpuart", "st,stm32-uart";
    191. 

  191. 			reg = <0x40008000 0x400>;
    192. 

  192. 			clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000001>;
    193. 

  193. 			interrupts = <91 0>;
    194. 

  194. 			status = "disabled";
    195. 

  195. 			label = "LPUART_1";
    196. 

  196. 		};
    197. 

  197. 

  198. 		iwdg: watchdog@40003000 {
    199. 

  199. 			compatible = "st,stm32-watchdog";
    200. 

  200. 			reg = <0x40003000 0x400>;
    201. 

  201. 			label = "IWDG";
    202. 

  202. 			status = "disabled";
    203. 

  203. 		};
    204. 

  204. 

  205. 		wwdg: watchdog@40002c00 {
    206. 

  206. 			compatible = "st,stm32-window-watchdog";
    207. 

  207. 			reg = <0x40002C00 0x400>;
    208. 

  208. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
    209. 

  209. 			label = "WWDG";
    210. 

  210. 			interrupts = <0 7>;
    211. 

  211. 			status = "disabled";
    212. 

  212. 		};
    213. 

  213. 

  214. 		i2c1: i2c@40005400 {
    215. 

  215. 			compatible = "st,stm32-i2c-v2";
    216. 

  216. 			clock-frequency = <I2C_BITRATE_STANDARD>;
    217. 

  217. 			#address-cells = <1>;
    218. 

  218. 			#size-cells = <0>;
    219. 

  219. 			reg = <0x40005400 0x400>;
    220. 

  220. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
    221. 

  221. 			interrupts = <31 0>, <32 0>;
    222. 

  222. 			interrupt-names = "event", "error";
    223. 

  223. 			status = "disabled";
    224. 

  224. 			label= "I2C_1";
    225. 

  225. 		};
    226. 

  226. 

  227. 		i2c2: i2c@40005800 {
    228. 

  228. 			compatible = "st,stm32-i2c-v2";
    229. 

  229. 			clock-frequency = <I2C_BITRATE_STANDARD>;
    230. 

  230. 			#address-cells = <1>;
    231. 

  231. 			#size-cells = <0>;
    232. 

  232. 			reg = <0x40005800 0x400>;
    233. 

  233. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
    234. 

  234. 			interrupts = <33 0>, <34 0>;
    235. 

  235. 			interrupt-names = "event", "error";
    236. 

  236. 			status = "disabled";
    237. 

  237. 			label= "I2C_2";
    238. 

  238. 		};
    239. 

  239. 

  240. 		i2c3: i2c@40007800 {
    241. 

  241. 			compatible = "st,stm32-i2c-v2";
    242. 

  242. 			clock-frequency = <I2C_BITRATE_STANDARD>;
    243. 

  243. 			#address-cells = <1>;
    244. 

  244. 			#size-cells = <0>;
    245. 

  245. 			reg = <0x40007800 0x400>;
    246. 

  246. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
    247. 

  247. 			interrupts = <92 0>, <93 0>;
    248. 

  248. 			interrupt-names = "event", "error";
    249. 

  249. 			status = "disabled";
    250. 

  250. 			label= "I2C_3";
    251. 

  251. 		};
    252. 

  252. 

  253. 		spi1: spi@40013000 {
    254. 

  254. 			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
    255. 

  255. 			#address-cells = <1>;
    256. 

  256. 			#size-cells = <0>;
    257. 

  257. 			reg = <0x40013000 0x400>;
    258. 

  258. 			interrupts = <35 5>;
    259. 

  259. 			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
    260. 

  260. 			status = "disabled";
    261. 

  261. 			label = "SPI_1";
    262. 

  262. 		};
    263. 

  263. 

  264. 		spi2: spi@40003800 {
    265. 

  265. 			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
    266. 

  266. 			#address-cells = <1>;
    267. 

  267. 			#size-cells = <0>;
    268. 

  268. 			reg = <0x40003800 0x400>;
    269. 

  269. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
    270. 

  270. 			interrupts = <36 5>;
    271. 

  271. 			status = "disabled";
    272. 

  272. 			label = "SPI_2";
    273. 

  273. 		};
    274. 

  274. 

  275. 		spi3: spi@40003c00 {
    276. 

  276. 			compatible = "st,stm32-spi-fifo", "st,stm32-spi";
    277. 

  277. 			#address-cells = <1>;
    278. 

  278. 			#size-cells = <0>;
    279. 

  279. 			reg = <0x40003c00 0x400>;
    280. 

  280. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
    281. 

  281. 			interrupts = <51 5>;
    282. 

  282. 			status = "disabled";
    283. 

  283. 			label = "SPI_3";
    284. 

  284. 		};
    285. 

  285. 

  286. 		timers1: timers@40012c00 {
    287. 

  287. 			compatible = "st,stm32-timers";
    288. 

  288. 			reg = <0x40012c00 0x400>;
    289. 

  289. 			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
    290. 

  290. 			status = "disabled";
    291. 

  291. 			label = "TIMERS_1";
    292. 

  292. 

  293. 			pwm {
    294. 

  294. 				compatible = "st,stm32-pwm";
    295. 

  295. 				status = "disabled";
    296. 

  296. 				st,prescaler = <10000>;
    297. 

  297. 				label = "PWM_1";
    298. 

  298. 				#pwm-cells = <2>;
    299. 

  299. 			};
    300. 

  300. 		};
    301. 

  301. 

  302. 		timers2: timers@40000000 {
    303. 

  303. 			compatible = "st,stm32-timers";
    304. 

  304. 			reg = <0x40000000 0x400>;
    305. 

  305. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
    306. 

  306. 			status = "disabled";
    307. 

  307. 			label = "TIMERS_2";
    308. 

  308. 

  309. 			pwm {
    310. 

  310. 				compatible = "st,stm32-pwm";
    311. 

  311. 				status = "disabled";
    312. 

  312. 				st,prescaler = <0>;
    313. 

  313. 				label = "PWM_2";
    314. 

  314. 				#pwm-cells = <2>;
    315. 

  315. 			};
    316. 

  316. 		};
    317. 

  317. 

  318. 		timers3: timers@40000400 {
    319. 

  319. 			compatible = "st,stm32-timers";
    320. 

  320. 			reg = <0x40000400 0x400>;
    321. 

  321. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
    322. 

  322. 			status = "disabled";
    323. 

  323. 			label = "TIMERS_3";
    324. 

  324. 

  325. 			pwm {
    326. 

  326. 				compatible = "st,stm32-pwm";
    327. 

  327. 				status = "disabled";
    328. 

  328. 				st,prescaler = <10000>;
    329. 

  329. 				label = "PWM_3";
    330. 

  330. 				#pwm-cells = <2>;
    331. 

  331. 			};
    332. 

  332. 		};
    333. 

  333. 

  334. 		timers4: timers@40000800 {
    335. 

  335. 			compatible = "st,stm32-timers";
    336. 

  336. 			reg = <0x40000800 0x400>;
    337. 

  337. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
    338. 

  338. 			status = "disabled";
    339. 

  339. 			label = "TIMERS_4";
    340. 

  340. 

  341. 			pwm {
    342. 

  342. 				compatible = "st,stm32-pwm";
    343. 

  343. 				status = "disabled";
    344. 

  344. 				st,prescaler = <10000>;
    345. 

  345. 				label = "PWM_4";
    346. 

  346. 				#pwm-cells = <2>;
    347. 

  347. 			};
    348. 

  348. 		};
    349. 

  349. 

  350. 		timers6: timers@40001000 {
    351. 

  351. 			compatible = "st,stm32-timers";
    352. 

  352. 			reg = <0x40001000 0x400>;
    353. 

  353. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
    354. 

  354. 			status = "disabled";
    355. 

  355. 			label = "TIMERS_6";
    356. 

  356. 

  357. 			pwm {
    358. 

  358. 				compatible = "st,stm32-pwm";
    359. 

  359. 				status = "disabled";
    360. 

  360. 				st,prescaler = <10000>;
    361. 

  361. 				label = "PWM_6";
    362. 

  362. 				#pwm-cells = <2>;
    363. 

  363. 			};
    364. 

  364. 		};
    365. 

  365. 

  366. 		timers7: timers@40001400 {
    367. 

  367. 			compatible = "st,stm32-timers";
    368. 

  368. 			reg = <0x40001400 0x400>;
    369. 

  369. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
    370. 

  370. 			status = "disabled";
    371. 

  371. 			label = "TIMERS_7";
    372. 

  372. 

  373. 			pwm {
    374. 

  374. 				compatible = "st,stm32-pwm";
    375. 

  375. 				status = "disabled";
    376. 

  376. 				st,prescaler = <10000>;
    377. 

  377. 				label = "PWM_7";
    378. 

  378. 				#pwm-cells = <2>;
    379. 

  379. 			};
    380. 

  380. 		};
    381. 

  381. 

  382. 		timers8: timers@40013400 {
    383. 

  383. 			compatible = "st,stm32-timers";
    384. 

  384. 			reg = <0x40013400 0x400>;
    385. 

  385. 			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
    386. 

  386. 			status = "disabled";
    387. 

  387. 			label = "TIMERS_8";
    388. 

  388. 

  389. 			pwm {
    390. 

  390. 				compatible = "st,stm32-pwm";
    391. 

  391. 				status = "disabled";
    392. 

  392. 				st,prescaler = <10000>;
    393. 

  393. 				label = "PWM_8";
    394. 

  394. 				#pwm-cells = <2>;
    395. 

  395. 			};
    396. 

  396. 		};
    397. 

  397. 

  398. 		timers15: timers@40014000 {
    399. 

  399. 			compatible = "st,stm32-timers";
    400. 

  400. 			reg = <0x40014000 0x400>;
    401. 

  401. 			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
    402. 

  402. 			status = "disabled";
    403. 

  403. 			label = "TIMERS_15";
    404. 

  404. 

  405. 			pwm {
    406. 

  406. 				compatible = "st,stm32-pwm";
    407. 

  407. 				status = "disabled";
    408. 

  408. 				st,prescaler = <10000>;
    409. 

  409. 				label = "PWM_15";
    410. 

  410. 				#pwm-cells = <2>;
    411. 

  411. 			};
    412. 

  412. 		};
    413. 

  413. 

  414. 		timers16: timers@40014400 {
    415. 

  415. 			compatible = "st,stm32-timers";
    416. 

  416. 			reg = <0x40014400 0x400>;
    417. 

  417. 			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
    418. 

  418. 			status = "disabled";
    419. 

  419. 			label = "TIMERS_16";
    420. 

  420. 

  421. 			pwm {
    422. 

  422. 				compatible = "st,stm32-pwm";
    423. 

  423. 				status = "disabled";
    424. 

  424. 				st,prescaler = <10000>;
    425. 

  425. 				label = "PWM_16";
    426. 

  426. 				#pwm-cells = <2>;
    427. 

  427. 			};
    428. 

  428. 		};
    429. 

  429. 

  430. 		timers17: timers@40014800 {
    431. 

  431. 			compatible = "st,stm32-timers";
    432. 

  432. 			reg = <0x40014800 0x400>;
    433. 

  433. 			clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
    434. 

  434. 			status = "disabled";
    435. 

  435. 			label = "TIMERS_17";
    436. 

  436. 

  437. 			pwm {
    438. 

  438. 				compatible = "st,stm32-pwm";
    439. 

  439. 				status = "disabled";
    440. 

  440. 				st,prescaler = <10000>;
    441. 

  441. 				label = "PWM_17";
    442. 

  442. 				#pwm-cells = <2>;
    443. 

  443. 			};
    444. 

  444. 		};
    445. 

  445. 

  446. 		rtc: rtc@40002800 {
    447. 

  447. 			compatible = "st,stm32-rtc";
    448. 

  448. 			reg = <0x40002800 0x400>;
    449. 

  449. 			interrupts = <41 0>;
    450. 

  450. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
    451. 

  451. 			prescaler = <32768>;
    452. 

  452. 			status = "disabled";
    453. 

  453. 			label = "RTC_0";
    454. 

  454. 		};
    455. 

  455. 

  456. 		rng: rng@50060800 {
    457. 

  457. 			compatible = "st,stm32-rng";
    458. 

  458. 			reg = <0x50060800 0x400>;
    459. 

  459. 			clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x04000000>;
    460. 

  460. 			status = "disabled";
    461. 

  461. 			label = "RNG";
    462. 

  462. 		};
    463. 

  463. 

  464. 		usb: usb@40005c00 {
    465. 

  465. 			compatible = "st,stm32-usb";
    466. 

  466. 			reg = <0x40005c00 0x400>;
    467. 

  467. 			interrupts = <20 0>, <19 0>;
    468. 

  468. 			interrupt-names = "usb", "usbhp";
    469. 

  469. 			num-bidir-endpoints = <8>;
    470. 

  470. 			ram-size = <1024>;
    471. 

  471. 			phys = <&usb_fs_phy>;
    472. 

  472. 			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
    473. 

  473. 			status = "disabled";
    474. 

  474. 			label= "USB";
    475. 

  475. 		};
    476. 

  476. 

  477. 	};
    478. 

  478. 

  479. 	usb_fs_phy: usbphy {
    480. 

  480. 		compatible = "usb-nop-xceiv";
    481. 

  481. 		#phy-cells = <0>;
    482. 

  482. 		label = "USB_FS_PHY";
    483. 

  483. 	};
    484. 

  484. };
    485. 

  485. 

  486. &nvic {
    487. 

  487. 	arm,num-irq-priority-bits = <4>;
    488. 

  488. };
    489.