/grlib-gpl-1.1.0-b4113/lib/micron/ddr/ddr3.v
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- /****************************************************************************************
- *
- * File Name: ddr3.v
- * Version: 1.60
- * Model: BUS Functional
- *
- * Dependencies: ddr3_model_parameters.vh
- *
- * Description: Micron SDRAM DDR3 (Double Data Rate 3)
- *
- * Limitation: - doesn't check for average refresh timings
- * - positive ck and ck_n edges are used to form internal clock
- * - positive dqs and dqs_n edges are used to latch data
- * - test mode is not modeled
- * - Duty Cycle Corrector is not modeled
- * - Temperature Compensated Self Refresh is not modeled
- * - DLL off mode is not modeled.
- *
- * Note: - Set simulator resolution to "ps" accuracy
- * - Set DEBUG = 0 to disable $display messages
- *
- * Disclaimer This software code and all associated documentation, comments or other
- * of Warranty: information (collectively "Software") is provided "AS IS" without
- * warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
- * DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
- * TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
- * OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
- * WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
- * OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
- * FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
- * THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
- * ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
- * OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
- * ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
- * WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
- * OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
- * THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGES. Because some jurisdictions prohibit the exclusion or
- * limitation of liability for consequential or incidental damages, the
- * above limitation may not apply to you.
- *
- * Copyright 2003 Micron Technology, Inc. All rights reserved.
- *
- * Rev Author Date Changes
- * ---------------------------------------------------------------------------------------
- * 0.41 JMK 05/12/06 Removed auto-precharge to power down error check.
- * 0.42 JMK 08/25/06 Created internal clock using ck and ck_n.
- * TDQS can only be enabled in EMR for x8 configurations.
- * CAS latency is checked vs frequency when DLL locks.
- * Improved checking of DQS during writes.
- * Added true BL4 operation.
- * 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers.
- * Added ODTS Readout.
- * Replaced tZQCL with tZQinit and tZQoper
- * Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS.
- * Added tRFC checking for Refresh to Power-Down Re-Entry.
- * Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry
- * Added Clock Frequency Change during Precharge Power-Down.
- * Added -125x speed grades.
- * Fixed tRCD checking during Write.
- * 1.00 JMK 05/11/07 Initial release
- * 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF
- * Removed temp sensor readout from MPR
- * Updated initialization sequence
- * Updated timing parameters
- * 1.20 JMK 09/05/07 Updated clock frequency change
- * Added ddr3_dimm module
- * 1.30 JMK 01/23/08 Updated timing parameters
- * 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133
- * renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support.
- * Added multi-chip package model support in ddr3_mcp.v
- * 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades.
- * 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes
- *****************************************************************************************/
- // DO NOT CHANGE THE TIMESCALE
- // MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
- `timescale 1ps / 1ps
- // model flags
- // `define MODEL_PASR
- module ddr3 (
- rst_n,
- ck,
- ck_n,
- cke,
- cs_n,
- ras_n,
- cas_n,
- we_n,
- dm_tdqs,
- ba,
- addr,
- dq,
- dqs,
- dqs_n,
- tdqs_n,
- odt
- );
- `define x1Gb
- `define sg187E
- `define x16
- /* `include "ddr3_model_parameters.vh" */
- /****************************************************************************************
- *
- * Disclaimer This software code and all associated documentation, comments or other
- * of Warranty: information (collectively "Software") is provided "AS IS" without
- * warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
- * DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
- * TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
- * OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
- * WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
- * OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
- * FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
- * THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
- * ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
- * OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
- * ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
- * INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
- * WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
- * OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
- * THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
- * DAMAGES. Because some jurisdictions prohibit the exclusion or
- * limitation of liability for consequential or incidental damages, the
- * above limitation may not apply to you.
- *
- * Copyright 2003 Micron Technology, Inc. All rights reserved.
- *
- ****************************************************************************************/
- // Parameters current with 1Gb and 2Gb datasheet rev D
- // Timing parameters based on Speed Grade
- // SYMBOL UNITS DESCRIPTION
- // ------ ----- -----------
- `ifdef x1Gb // 1Gb parameters
- `ifdef sg094E // sg094E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin
- parameter TCK_MIN = 937.5; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 50; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 73; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 85; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 98; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 117; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 275; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 455; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 35; // tIS ps Input Setup Time
- parameter TIH = 75; // tIH ps Input Hold Time
- parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 12187; // tRCD ps Active to Read/Write command time
- parameter TRP = 12187; // tRP ps Precharge command period
- parameter TXP = 6000; // tXP ps Exit power down to a valid command
- parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 122; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 122; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 7500; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 12187; // TAA ps Internal READ command to first data
- parameter CL_TIME = 12187; // CL ps Minimum CAS Latency
- `else `ifdef sg094 // sg094 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin
- parameter TCK_MIN = 937.5; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 50; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 73; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 85; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 98; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 117; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 275; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 455; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 35; // tIS ps Input Setup Time
- parameter TIH = 75; // tIH ps Input Hold Time
- parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
- parameter TRP = 13125; // tRP ps Precharge command period
- parameter TXP = 6000; // tXP ps Exit power down to a valid command
- parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 122; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 122; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 7500; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
- parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
- `else `ifdef sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin
- parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 60; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 50; // tIS ps Input Setup Time
- parameter TIH = 100; // tIH ps Input Hold Time
- parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 12857; // tRCD ps Active to Read/Write command time
- parameter TRP = 12857; // tRP ps Precharge command period
- parameter TXP = 6000; // tXP ps Exit power down to a valid command
- parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 140; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 140; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 7500; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 12857; // TAA ps Internal READ command to first data
- parameter CL_TIME = 12857; // CL ps Minimum CAS Latency
- `else `ifdef sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin
- parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 60; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 50; // tIS ps Input Setup Time
- parameter TIH = 100; // tIH ps Input Hold Time
- parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 13928; // tRCD ps Active to Read/Write command time
- parameter TRP = 13928; // tRP ps Precharge command period
- parameter TXP = 6000; // tXP ps Exit power down to a valid command
- parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 140; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 140; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 7500; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 13928; // TAA ps Internal READ command to first data
- parameter CL_TIME = 13928; // CL ps Minimum CAS Latency
- `else `ifdef sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (14-14-14) speed bin
- parameter TCK_MIN = 15e3/14; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 60; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 103; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 140; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 300; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 505; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 50; // tIS ps Input Setup Time
- parameter TIH = 100; // tIH ps Input Hold Time
- parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
- parameter TRP = 15000; // tRP ps Precharge command period
- parameter TXP = 6000; // tXP ps Exit power down to a valid command
- parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 140; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 140; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 7500; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
- parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
- `else `ifdef sg125F // sg125F is equivalent to the JEDEC DDR3-1600 (9-9-9) speed bin
- parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 70; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 170; // tIS ps Input Setup Time
- parameter TIH = 120; // tIH ps Input Hold Time
- parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 46250; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 11250; // tRCD ps Active to Read/Write command time
- parameter TRP = 11250; // tRP ps Precharge command period
- parameter TXP = 6000; // tXP ps Exit power down to a valid command
- parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 165; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 165; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 7500; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 11250; // TAA ps Internal READ command to first data
- parameter CL_TIME = 11250; // CL ps Minimum CAS Latency
- `else `ifdef sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin
- parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 70; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 170; // tIS ps Input Setup Time
- parameter TIH = 120; // tIH ps Input Hold Time
- parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 12500; // tRCD ps Active to Read/Write command time
- parameter TRP = 12500; // tRP ps Precharge command period
- parameter TXP = 6000; // tXP ps Exit power down to a valid command
- parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 165; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 165; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 7500; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
- parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
- `else `ifdef sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin
- parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 70; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 170; // tIS ps Input Setup Time
- parameter TIH = 120; // tIH ps Input Hold Time
- parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
- parameter TRP = 13125; // tRP ps Precharge command period
- parameter TXP = 6000; // tXP ps Exit power down to a valid command
- parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 165; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 165; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 7500; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
- parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
- `else `ifdef sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin
- parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 190; // tIS ps Input Setup Time
- parameter TIH = 140; // tIH ps Input Hold Time
- parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
- parameter TRP = 13125; // tRP ps Precharge command period
- parameter TXP = 6000; // tXP ps Exit power down to a valid command
- parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 9000; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
- parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
- `else `ifdef sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin
- parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 80; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 190; // tIS ps Input Setup Time
- parameter TIH = 140; // tIH ps Input Hold Time
- parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 15000; // tRCD ps Active to Read/Write command time
- parameter TRP = 15000; // tRP ps Precharge command period
- parameter TXP = 6000; // tXP ps Exit power down to a valid command
- parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 195; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 195; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 9000; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data
- parameter CL_TIME = 15000; // CL ps Minimum CAS Latency
- `else `ifdef sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin
- parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle)
- parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle)
- parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle)
- parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle)
- parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle)
- parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle)
- parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle)
- parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle)
- parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle)
- parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle)
- parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle)
- parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS
- parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS
- parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access
- parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition
- parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time)
- parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time)
- parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK#
- parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width
- parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width
- parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width
- parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width
- parameter TIS = 275; // tIS ps Input Setup Time
- parameter TIH = 200; // tIH ps Input Hold Time
- parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time
- parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time
- parameter TRCD = 13125; // tRCD ps Active to Read/Write command time
- parameter TRP = 13125; // tRP ps Precharge command period
- parameter TXP = 7500; // tXP ps Exit power down to a valid command
- parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width
- parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference
- parameter TWLS = 245; // tWLS ps Setup time for tDQS flop
- parameter TWLH = 245; // tWLH ps Hold time of tDQS flop
- parameter TWLO = 9000; // tWLO ps Write levelization output delay
- parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data
- parameter CL_TIME = 13125; // CL ps Minimum CAS Latency
- `else `ifdef sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin
- parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time
- parameter TJIT_PER = 90; // tJIT(per) ps Period JItter
- parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter
- parameter TERR_2PER …
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