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/grlib-gpl-1.1.0-b4113/lib/micron/ddr/ddr3.v

https://github.com/shmele/leon3
Verilog | 4136 lines | 3641 code | 172 blank | 323 comment | 846 complexity | 45b3fdda80adcde112979602458017ef MD5 | raw file

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  1/****************************************************************************************
  2*
  3*    File Name:  ddr3.v
  4*      Version:  1.60
  5*        Model:  BUS Functional
  6*
  7* Dependencies:  ddr3_model_parameters.vh
  8*
  9*  Description:  Micron SDRAM DDR3 (Double Data Rate 3)
 10*
 11*   Limitation:  - doesn't check for average refresh timings
 12*                - positive ck and ck_n edges are used to form internal clock
 13*                - positive dqs and dqs_n edges are used to latch data
 14*                - test mode is not modeled
 15*                - Duty Cycle Corrector is not modeled
 16*                - Temperature Compensated Self Refresh is not modeled
 17*                - DLL off mode is not modeled.
 18*
 19*         Note:  - Set simulator resolution to "ps" accuracy
 20*                - Set DEBUG = 0 to disable $display messages
 21*
 22*   Disclaimer   This software code and all associated documentation, comments or other 
 23*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
 24*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
 25*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
 26*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
 27*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
 28*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
 29*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
 30*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
 31*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
 32*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
 33*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
 34*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
 35*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
 36*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
 37*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
 38*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
 39*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
 40*                limitation of liability for consequential or incidental damages, the 
 41*                above limitation may not apply to you.
 42*
 43*                Copyright 2003 Micron Technology, Inc. All rights reserved.
 44*
 45* Rev   Author   Date        Changes
 46* ---------------------------------------------------------------------------------------
 47* 0.41  JMK      05/12/06    Removed auto-precharge to power down error check.
 48* 0.42  JMK      08/25/06    Created internal clock using ck and ck_n.
 49*                            TDQS can only be enabled in EMR for x8 configurations.
 50*                            CAS latency is checked vs frequency when DLL locks.
 51*                            Improved checking of DQS during writes.
 52*                            Added true BL4 operation.
 53* 0.43  JMK      08/14/06    Added checking for setting reserved bits in Mode Registers.
 54*                            Added ODTS Readout.
 55*                            Replaced tZQCL with tZQinit and tZQoper
 56*                            Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS.
 57*                            Added tRFC checking for Refresh to Power-Down Re-Entry.
 58*                            Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry
 59*                            Added Clock Frequency Change during Precharge Power-Down.
 60*                            Added -125x speed grades.
 61*                            Fixed tRCD checking during Write.
 62* 1.00  JMK      05/11/07    Initial release
 63* 1.10  JMK      06/26/07    Fixed ODTH8 check during BLOTF
 64*                            Removed temp sensor readout from MPR
 65*                            Updated initialization sequence
 66*                            Updated timing parameters
 67* 1.20  JMK      09/05/07    Updated clock frequency change
 68*                            Added ddr3_dimm module
 69* 1.30  JMK      01/23/08    Updated timing parameters
 70* 1.40  JMK      12/02/08    Added support for DDR3-1866 and DDR3-2133
 71*                            renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support.
 72*                            Added multi-chip package model support in ddr3_mcp.v
 73* 1.50  JMK      05/04/08    Added 1866 and 2133 speed grades.
 74* 1.60  MYY      07/10/09    Merging of 1.50 version and pre-1.0 version changes
 75*****************************************************************************************/
 76// DO NOT CHANGE THE TIMESCALE
 77// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
 78`timescale 1ps / 1ps
 79
 80// model flags
 81// `define MODEL_PASR
 82
 83module ddr3 (
 84    rst_n,
 85    ck,
 86    ck_n,
 87    cke,
 88    cs_n,
 89    ras_n,
 90    cas_n,
 91    we_n,
 92    dm_tdqs,
 93    ba,
 94    addr,
 95    dq,
 96    dqs,
 97    dqs_n,
 98    tdqs_n,
 99    odt
100);
101
102`define x1Gb
103`define sg187E
104`define x16
105
106/*    `include "ddr3_model_parameters.vh" */
107
108
109/****************************************************************************************
110*
111*   Disclaimer   This software code and all associated documentation, comments or other
112*  of Warranty:  information (collectively "Software") is provided "AS IS" without
113*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY
114*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED
115*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES
116*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT
117*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE
118*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE.
119*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR
120*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS,
121*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE
122*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI,
123*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT,
124*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING,
125*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION,
126*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE
127*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH
128*                DAMAGES. Because some jurisdictions prohibit the exclusion or
129*                limitation of liability for consequential or incidental damages, the
130*                above limitation may not apply to you.
131*
132*                Copyright 2003 Micron Technology, Inc. All rights reserved.
133*
134****************************************************************************************/
135
136    // Parameters current with 1Gb and 2Gb datasheet rev D
137
138    // Timing parameters based on Speed Grade
139
140                                            // SYMBOL     UNITS DESCRIPTION
141                                            // ------     ----- -----------
142`ifdef x1Gb  // 1Gb parameters
143
144  `ifdef sg094E                             // sg094E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin
145      parameter TCK_MIN          =   937.5; // tCK        ps    Minimum Clock Cycle Time
146      parameter TJIT_PER         =      50; // tJIT(per)  ps    Period JItter
147      parameter TJIT_CC          =     100; // tJIT(cc)   ps    Cycle to Cycle jitter
148      parameter TERR_2PER        =      73; // tERR(2per) ps    Accumulated Error (2-cycle)
149      parameter TERR_3PER        =      85; // tERR(3per) ps    Accumulated Error (3-cycle)
150      parameter TERR_4PER        =      98; // tERR(4per) ps    Accumulated Error (4-cycle)
151      parameter TERR_5PER        =     105; // tERR(5per) ps    Accumulated Error (5-cycle)
152      parameter TERR_6PER        =     111; // tERR(6per) ps    Accumulated Error (6-cycle)
153      parameter TERR_7PER        =     117; // tERR(7per) ps    Accumulated Error (7-cycle)
154      parameter TERR_8PER        =     121; // tERR(8per) ps    Accumulated Error (8-cycle)
155      parameter TERR_9PER        =     125; // tERR(9per) ps    Accumulated Error (9-cycle)
156      parameter TERR_10PER       =     128; // tERR(10per)ps    Accumulated Error (10-cycle)
157      parameter TERR_11PER       =     132; // tERR(11per)ps    Accumulated Error (11-cycle)
158      parameter TERR_12PER       =     134; // tERR(12per)ps    Accumulated Error (12-cycle)
159      parameter TDS              =       5; // tDS        ps    DQ and DM input setup time relative to DQS
160      parameter TDH              =      20; // tDH        ps    DQ and DM input hold time relative to DQS
161      parameter TDQSQ            =      70; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
162      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
163      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
164      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
165      parameter TDQSCK           =     175; // tDQSCK     ps    DQS output access time from CK/CK#
166      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
167      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
168      parameter TDIPW            =     275; // tDIPW      ps    DQ and DM input Pulse Width
169      parameter TIPW             =     455; // tIPW       ps    Control and Address input Pulse Width
170      parameter TIS              =      35; // tIS        ps    Input Setup Time
171      parameter TIH              =      75; // tIH        ps    Input Hold Time
172      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
173      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
174      parameter TRCD             =   12187; // tRCD       ps    Active to Read/Write command time
175      parameter TRP              =   12187; // tRP        ps    Precharge command period
176      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
177      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
178      parameter TAON             =     180; // tAON       ps    RTT turn-on from ODTLon reference
179      parameter TWLS             =     122; // tWLS       ps    Setup time for tDQS flop
180      parameter TWLH             =     122; // tWLH       ps    Hold time of tDQS flop
181      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
182      parameter TAA_MIN          =   12187; // TAA        ps    Internal READ command to first data
183      parameter CL_TIME          =   12187; // CL         ps    Minimum CAS Latency
184  `else `ifdef sg094                        // sg094  is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin
185      parameter TCK_MIN          =   937.5; // tCK        ps    Minimum Clock Cycle Time
186      parameter TJIT_PER         =      50; // tJIT(per)  ps    Period JItter
187      parameter TJIT_CC          =     100; // tJIT(cc)   ps    Cycle to Cycle jitter
188      parameter TERR_2PER        =      73; // tERR(2per) ps    Accumulated Error (2-cycle)
189      parameter TERR_3PER        =      85; // tERR(3per) ps    Accumulated Error (3-cycle)
190      parameter TERR_4PER        =      98; // tERR(4per) ps    Accumulated Error (4-cycle)
191      parameter TERR_5PER        =     105; // tERR(5per) ps    Accumulated Error (5-cycle)
192      parameter TERR_6PER        =     111; // tERR(6per) ps    Accumulated Error (6-cycle)
193      parameter TERR_7PER        =     117; // tERR(7per) ps    Accumulated Error (7-cycle)
194      parameter TERR_8PER        =     121; // tERR(8per) ps    Accumulated Error (8-cycle)
195      parameter TERR_9PER        =     125; // tERR(9per) ps    Accumulated Error (9-cycle)
196      parameter TERR_10PER       =     128; // tERR(10per)ps    Accumulated Error (10-cycle)
197      parameter TERR_11PER       =     132; // tERR(11per)ps    Accumulated Error (11-cycle)
198      parameter TERR_12PER       =     134; // tERR(12per)ps    Accumulated Error (12-cycle)
199      parameter TDS              =       5; // tDS        ps    DQ and DM input setup time relative to DQS
200      parameter TDH              =      20; // tDH        ps    DQ and DM input hold time relative to DQS
201      parameter TDQSQ            =      70; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
202      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
203      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
204      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
205      parameter TDQSCK           =     175; // tDQSCK     ps    DQS output access time from CK/CK#
206      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
207      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
208      parameter TDIPW            =     275; // tDIPW      ps    DQ and DM input Pulse Width
209      parameter TIPW             =     455; // tIPW       ps    Control and Address input Pulse Width
210      parameter TIS              =      35; // tIS        ps    Input Setup Time
211      parameter TIH              =      75; // tIH        ps    Input Hold Time
212      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
213      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
214      parameter TRCD             =   13125; // tRCD       ps    Active to Read/Write command time
215      parameter TRP              =   13125; // tRP        ps    Precharge command period
216      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
217      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
218      parameter TAON             =     180; // tAON       ps    RTT turn-on from ODTLon reference
219      parameter TWLS             =     122; // tWLS       ps    Setup time for tDQS flop
220      parameter TWLH             =     122; // tWLH       ps    Hold time of tDQS flop
221      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
222      parameter TAA_MIN          =   13125; // TAA        ps    Internal READ command to first data
223      parameter CL_TIME          =   13125; // CL         ps    Minimum CAS Latency
224  `else `ifdef sg107F                       // sg107F is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin
225      parameter TCK_MIN          = 15e3/14; // tCK        ps    Minimum Clock Cycle Time
226      parameter TJIT_PER         =      60; // tJIT(per)  ps    Period JItter
227      parameter TJIT_CC          =     120; // tJIT(cc)   ps    Cycle to Cycle jitter
228      parameter TERR_2PER        =      88; // tERR(2per) ps    Accumulated Error (2-cycle)
229      parameter TERR_3PER        =     103; // tERR(3per) ps    Accumulated Error (3-cycle)
230      parameter TERR_4PER        =     117; // tERR(4per) ps    Accumulated Error (4-cycle)
231      parameter TERR_5PER        =     126; // tERR(5per) ps    Accumulated Error (5-cycle)
232      parameter TERR_6PER        =     133; // tERR(6per) ps    Accumulated Error (6-cycle)
233      parameter TERR_7PER        =     140; // tERR(7per) ps    Accumulated Error (7-cycle)
234      parameter TERR_8PER        =     145; // tERR(8per) ps    Accumulated Error (8-cycle)
235      parameter TERR_9PER        =     150; // tERR(9per) ps    Accumulated Error (9-cycle)
236      parameter TERR_10PER       =     154; // tERR(10per)ps    Accumulated Error (10-cycle)
237      parameter TERR_11PER       =     158; // tERR(11per)ps    Accumulated Error (11-cycle)
238      parameter TERR_12PER       =     161; // tERR(12per)ps    Accumulated Error (12-cycle)
239      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
240      parameter TDH              =      20; // tDH        ps    DQ and DM input hold time relative to DQS
241      parameter TDQSQ            =      80; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
242      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
243      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
244      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
245      parameter TDQSCK           =     200; // tDQSCK     ps    DQS output access time from CK/CK#
246      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
247      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
248      parameter TDIPW            =     300; // tDIPW      ps    DQ and DM input Pulse Width
249      parameter TIPW             =     505; // tIPW       ps    Control and Address input Pulse Width
250      parameter TIS              =      50; // tIS        ps    Input Setup Time
251      parameter TIH              =     100; // tIH        ps    Input Hold Time
252      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
253      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
254      parameter TRCD             =   12857; // tRCD       ps    Active to Read/Write command time
255      parameter TRP              =   12857; // tRP        ps    Precharge command period
256      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
257      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
258      parameter TAON             =     200; // tAON       ps    RTT turn-on from ODTLon reference
259      parameter TWLS             =     140; // tWLS       ps    Setup time for tDQS flop
260      parameter TWLH             =     140; // tWLH       ps    Hold time of tDQS flop
261      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
262      parameter TAA_MIN          =   12857; // TAA        ps    Internal READ command to first data
263      parameter CL_TIME          =   12857; // CL         ps    Minimum CAS Latency
264  `else `ifdef sg107E                       // sg107E is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin
265      parameter TCK_MIN          = 15e3/14; // tCK        ps    Minimum Clock Cycle Time
266      parameter TJIT_PER         =      60; // tJIT(per)  ps    Period JItter
267      parameter TJIT_CC          =     120; // tJIT(cc)   ps    Cycle to Cycle jitter
268      parameter TERR_2PER        =      88; // tERR(2per) ps    Accumulated Error (2-cycle)
269      parameter TERR_3PER        =     103; // tERR(3per) ps    Accumulated Error (3-cycle)
270      parameter TERR_4PER        =     117; // tERR(4per) ps    Accumulated Error (4-cycle)
271      parameter TERR_5PER        =     126; // tERR(5per) ps    Accumulated Error (5-cycle)
272      parameter TERR_6PER        =     133; // tERR(6per) ps    Accumulated Error (6-cycle)
273      parameter TERR_7PER        =     140; // tERR(7per) ps    Accumulated Error (7-cycle)
274      parameter TERR_8PER        =     145; // tERR(8per) ps    Accumulated Error (8-cycle)
275      parameter TERR_9PER        =     150; // tERR(9per) ps    Accumulated Error (9-cycle)
276      parameter TERR_10PER       =     154; // tERR(10per)ps    Accumulated Error (10-cycle)
277      parameter TERR_11PER       =     158; // tERR(11per)ps    Accumulated Error (11-cycle)
278      parameter TERR_12PER       =     161; // tERR(12per)ps    Accumulated Error (12-cycle)
279      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
280      parameter TDH              =      20; // tDH        ps    DQ and DM input hold time relative to DQS
281      parameter TDQSQ            =      80; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
282      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
283      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
284      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
285      parameter TDQSCK           =     200; // tDQSCK     ps    DQS output access time from CK/CK#
286      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
287      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
288      parameter TDIPW            =     300; // tDIPW      ps    DQ and DM input Pulse Width
289      parameter TIPW             =     505; // tIPW       ps    Control and Address input Pulse Width
290      parameter TIS              =      50; // tIS        ps    Input Setup Time
291      parameter TIH              =     100; // tIH        ps    Input Hold Time
292      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
293      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
294      parameter TRCD             =   13928; // tRCD       ps    Active to Read/Write command time
295      parameter TRP              =   13928; // tRP        ps    Precharge command period
296      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
297      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
298      parameter TAON             =     200; // tAON       ps    RTT turn-on from ODTLon reference
299      parameter TWLS             =     140; // tWLS       ps    Setup time for tDQS flop
300      parameter TWLH             =     140; // tWLH       ps    Hold time of tDQS flop
301      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
302      parameter TAA_MIN          =   13928; // TAA        ps    Internal READ command to first data
303      parameter CL_TIME          =   13928; // CL         ps    Minimum CAS Latency
304  `else `ifdef sg107                        // sg107  is equivalent to the JEDEC DDR3-1866 (14-14-14) speed bin
305      parameter TCK_MIN          = 15e3/14; // tCK        ps    Minimum Clock Cycle Time
306      parameter TJIT_PER         =      60; // tJIT(per)  ps    Period JItter
307      parameter TJIT_CC          =     120; // tJIT(cc)   ps    Cycle to Cycle jitter
308      parameter TERR_2PER        =      88; // tERR(2per) ps    Accumulated Error (2-cycle)
309      parameter TERR_3PER        =     103; // tERR(3per) ps    Accumulated Error (3-cycle)
310      parameter TERR_4PER        =     117; // tERR(4per) ps    Accumulated Error (4-cycle)
311      parameter TERR_5PER        =     126; // tERR(5per) ps    Accumulated Error (5-cycle)
312      parameter TERR_6PER        =     133; // tERR(6per) ps    Accumulated Error (6-cycle)
313      parameter TERR_7PER        =     140; // tERR(7per) ps    Accumulated Error (7-cycle)
314      parameter TERR_8PER        =     145; // tERR(8per) ps    Accumulated Error (8-cycle)
315      parameter TERR_9PER        =     150; // tERR(9per) ps    Accumulated Error (9-cycle)
316      parameter TERR_10PER       =     154; // tERR(10per)ps    Accumulated Error (10-cycle)
317      parameter TERR_11PER       =     158; // tERR(11per)ps    Accumulated Error (11-cycle)
318      parameter TERR_12PER       =     161; // tERR(12per)ps    Accumulated Error (12-cycle)
319      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
320      parameter TDH              =      20; // tDH        ps    DQ and DM input hold time relative to DQS
321      parameter TDQSQ            =      80; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
322      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
323      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
324      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
325      parameter TDQSCK           =     200; // tDQSCK     ps    DQS output access time from CK/CK#
326      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
327      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
328      parameter TDIPW            =     300; // tDIPW      ps    DQ and DM input Pulse Width
329      parameter TIPW             =     505; // tIPW       ps    Control and Address input Pulse Width
330      parameter TIS              =      50; // tIS        ps    Input Setup Time
331      parameter TIH              =     100; // tIH        ps    Input Hold Time
332      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
333      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
334      parameter TRCD             =   15000; // tRCD       ps    Active to Read/Write command time
335      parameter TRP              =   15000; // tRP        ps    Precharge command period
336      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
337      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
338      parameter TAON             =     200; // tAON       ps    RTT turn-on from ODTLon reference
339      parameter TWLS             =     140; // tWLS       ps    Setup time for tDQS flop
340      parameter TWLH             =     140; // tWLH       ps    Hold time of tDQS flop
341      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
342      parameter TAA_MIN          =   15000; // TAA        ps    Internal READ command to first data
343      parameter CL_TIME          =   15000; // CL         ps    Minimum CAS Latency
344  `else `ifdef sg125F                       // sg125F is equivalent to the JEDEC DDR3-1600 (9-9-9) speed bin
345      parameter TCK_MIN          =    1250; // tCK        ps    Minimum Clock Cycle Time
346      parameter TJIT_PER         =      70; // tJIT(per)  ps    Period JItter
347      parameter TJIT_CC          =     140; // tJIT(cc)   ps    Cycle to Cycle jitter
348      parameter TERR_2PER        =     103; // tERR(2per) ps    Accumulated Error (2-cycle)
349      parameter TERR_3PER        =     122; // tERR(3per) ps    Accumulated Error (3-cycle)
350      parameter TERR_4PER        =     136; // tERR(4per) ps    Accumulated Error (4-cycle)
351      parameter TERR_5PER        =     147; // tERR(5per) ps    Accumulated Error (5-cycle)
352      parameter TERR_6PER        =     155; // tERR(6per) ps    Accumulated Error (6-cycle)
353      parameter TERR_7PER        =     163; // tERR(7per) ps    Accumulated Error (7-cycle)
354      parameter TERR_8PER        =     169; // tERR(8per) ps    Accumulated Error (8-cycle)
355      parameter TERR_9PER        =     175; // tERR(9per) ps    Accumulated Error (9-cycle)
356      parameter TERR_10PER       =     180; // tERR(10per)ps    Accumulated Error (10-cycle)
357      parameter TERR_11PER       =     184; // tERR(11per)ps    Accumulated Error (11-cycle)
358      parameter TERR_12PER       =     188; // tERR(12per)ps    Accumulated Error (12-cycle)
359      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
360      parameter TDH              =      45; // tDH        ps    DQ and DM input hold time relative to DQS
361      parameter TDQSQ            =     100; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
362      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
363      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
364      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
365      parameter TDQSCK           =     225; // tDQSCK     ps    DQS output access time from CK/CK#
366      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
367      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
368      parameter TDIPW            =     360; // tDIPW      ps    DQ and DM input Pulse Width
369      parameter TIPW             =     560; // tIPW       ps    Control and Address input Pulse Width
370      parameter TIS              =     170; // tIS        ps    Input Setup Time
371      parameter TIH              =     120; // tIH        ps    Input Hold Time
372      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
373      parameter TRC              =   46250; // tRC        ps    Active to Active/Auto Refresh command time
374      parameter TRCD             =   11250; // tRCD       ps    Active to Read/Write command time
375      parameter TRP              =   11250; // tRP        ps    Precharge command period
376      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
377      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
378      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
379      parameter TWLS             =     165; // tWLS       ps    Setup time for tDQS flop
380      parameter TWLH             =     165; // tWLH       ps    Hold time of tDQS flop
381      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
382      parameter TAA_MIN          =   11250; // TAA        ps    Internal READ command to first data
383      parameter CL_TIME          =   11250; // CL         ps    Minimum CAS Latency
384  `else `ifdef sg125E                       // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin
385      parameter TCK_MIN          =    1250; // tCK        ps    Minimum Clock Cycle Time
386      parameter TJIT_PER         =      70; // tJIT(per)  ps    Period JItter
387      parameter TJIT_CC          =     140; // tJIT(cc)   ps    Cycle to Cycle jitter
388      parameter TERR_2PER        =     103; // tERR(2per) ps    Accumulated Error (2-cycle)
389      parameter TERR_3PER        =     122; // tERR(3per) ps    Accumulated Error (3-cycle)
390      parameter TERR_4PER        =     136; // tERR(4per) ps    Accumulated Error (4-cycle)
391      parameter TERR_5PER        =     147; // tERR(5per) ps    Accumulated Error (5-cycle)
392      parameter TERR_6PER        =     155; // tERR(6per) ps    Accumulated Error (6-cycle)
393      parameter TERR_7PER        =     163; // tERR(7per) ps    Accumulated Error (7-cycle)
394      parameter TERR_8PER        =     169; // tERR(8per) ps    Accumulated Error (8-cycle)
395      parameter TERR_9PER        =     175; // tERR(9per) ps    Accumulated Error (9-cycle)
396      parameter TERR_10PER       =     180; // tERR(10per)ps    Accumulated Error (10-cycle)
397      parameter TERR_11PER       =     184; // tERR(11per)ps    Accumulated Error (11-cycle)
398      parameter TERR_12PER       =     188; // tERR(12per)ps    Accumulated Error (12-cycle)
399      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
400      parameter TDH              =      45; // tDH        ps    DQ and DM input hold time relative to DQS
401      parameter TDQSQ            =     100; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
402      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
403      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
404      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
405      parameter TDQSCK           =     225; // tDQSCK     ps    DQS output access time from CK/CK#
406      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
407      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
408      parameter TDIPW            =     360; // tDIPW      ps    DQ and DM input Pulse Width
409      parameter TIPW             =     560; // tIPW       ps    Control and Address input Pulse Width
410      parameter TIS              =     170; // tIS        ps    Input Setup Time
411      parameter TIH              =     120; // tIH        ps    Input Hold Time
412      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
413      parameter TRC              =   47500; // tRC        ps    Active to Active/Auto Refresh command time
414      parameter TRCD             =   12500; // tRCD       ps    Active to Read/Write command time
415      parameter TRP              =   12500; // tRP        ps    Precharge command period
416      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
417      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
418      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
419      parameter TWLS             =     165; // tWLS       ps    Setup time for tDQS flop
420      parameter TWLH             =     165; // tWLH       ps    Hold time of tDQS flop
421      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
422      parameter TAA_MIN          =   12500; // TAA        ps    Internal READ command to first data
423      parameter CL_TIME          =   12500; // CL         ps    Minimum CAS Latency
424  `else `ifdef sg125                        // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin
425      parameter TCK_MIN          =    1250; // tCK        ps    Minimum Clock Cycle Time
426      parameter TJIT_PER         =      70; // tJIT(per)  ps    Period JItter
427      parameter TJIT_CC          =     140; // tJIT(cc)   ps    Cycle to Cycle jitter
428      parameter TERR_2PER        =     103; // tERR(2per) ps    Accumulated Error (2-cycle)
429      parameter TERR_3PER        =     122; // tERR(3per) ps    Accumulated Error (3-cycle)
430      parameter TERR_4PER        =     136; // tERR(4per) ps    Accumulated Error (4-cycle)
431      parameter TERR_5PER        =     147; // tERR(5per) ps    Accumulated Error (5-cycle)
432      parameter TERR_6PER        =     155; // tERR(6per) ps    Accumulated Error (6-cycle)
433      parameter TERR_7PER        =     163; // tERR(7per) ps    Accumulated Error (7-cycle)
434      parameter TERR_8PER        =     169; // tERR(8per) ps    Accumulated Error (8-cycle)
435      parameter TERR_9PER        =     175; // tERR(9per) ps    Accumulated Error (9-cycle)
436      parameter TERR_10PER       =     180; // tERR(10per)ps    Accumulated Error (10-cycle)
437      parameter TERR_11PER       =     184; // tERR(11per)ps    Accumulated Error (11-cycle)
438      parameter TERR_12PER       =     188; // tERR(12per)ps    Accumulated Error (12-cycle)
439      parameter TDS              =      10; // tDS        ps    DQ and DM input setup time relative to DQS
440      parameter TDH              =      45; // tDH        ps    DQ and DM input hold time relative to DQS
441      parameter TDQSQ            =     100; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
442      parameter TDQSS            =    0.27; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
443      parameter TDSS             =    0.18; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
444      parameter TDSH             =    0.18; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
445      parameter TDQSCK           =     225; // tDQSCK     ps    DQS output access time from CK/CK#
446      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
447      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
448      parameter TDIPW            =     360; // tDIPW      ps    DQ and DM input Pulse Width
449      parameter TIPW             =     560; // tIPW       ps    Control and Address input Pulse Width
450      parameter TIS              =     170; // tIS        ps    Input Setup Time
451      parameter TIH              =     120; // tIH        ps    Input Hold Time
452      parameter TRAS_MIN         =   35000; // tRAS       ps    Minimum Active to Precharge command time
453      parameter TRC              =   48750; // tRC        ps    Active to Active/Auto Refresh command time
454      parameter TRCD             =   13125; // tRCD       ps    Active to Read/Write command time
455      parameter TRP              =   13125; // tRP        ps    Precharge command period
456      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
457      parameter TCKE             =    5000; // tCKE       ps    CKE minimum high or low pulse width
458      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
459      parameter TWLS             =     165; // tWLS       ps    Setup time for tDQS flop
460      parameter TWLH             =     165; // tWLH       ps    Hold time of tDQS flop
461      parameter TWLO             =    7500; // tWLO       ps    Write levelization output delay
462      parameter TAA_MIN          =   13125; // TAA        ps    Internal READ command to first data
463      parameter CL_TIME          =   13125; // CL         ps    Minimum CAS Latency
464  `else `ifdef sg15E                        // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin
465      parameter TCK_MIN          =    1500; // tCK        ps    Minimum Clock Cycle Time
466      parameter TJIT_PER         =      80; // tJIT(per)  ps    Period JItter
467      parameter TJIT_CC          =     160; // tJIT(cc)   ps    Cycle to Cycle jitter
468      parameter TERR_2PER        =     118; // tERR(2per) ps    Accumulated Error (2-cycle)
469      parameter TERR_3PER        =     140; // tERR(3per) ps    Accumulated Error (3-cycle)
470      parameter TERR_4PER        =     155; // tERR(4per) ps    Accumulated Error (4-cycle)
471      parameter TERR_5PER        =     168; // tERR(5per) ps    Accumulated Error (5-cycle)
472      parameter TERR_6PER        =     177; // tERR(6per) ps    Accumulated Error (6-cycle)
473      parameter TERR_7PER        =     186; // tERR(7per) ps    Accumulated Error (7-cycle)
474      parameter TERR_8PER        =     193; // tERR(8per) ps    Accumulated Error (8-cycle)
475      parameter TERR_9PER        =     200; // tERR(9per) ps    Accumulated Error (9-cycle)
476      parameter TERR_10PER       =     205; // tERR(10per)ps    Accumulated Error (10-cycle)
477      parameter TERR_11PER       =     210; // tERR(11per)ps    Accumulated Error (11-cycle)
478      parameter TERR_12PER       =     215; // tERR(12per)ps    Accumulated Error (12-cycle)
479      parameter TDS              =      30; // tDS        ps    DQ and DM input setup time relative to DQS
480      parameter TDH              =      65; // tDH        ps    DQ and DM input hold time relative to DQS
481      parameter TDQSQ            =     125; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
482      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
483      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
484      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
485      parameter TDQSCK           =     255; // tDQSCK     ps    DQS output access time from CK/CK#
486      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
487      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
488      parameter TDIPW            =     400; // tDIPW      ps    DQ and DM input Pulse Width
489      parameter TIPW             =     620; // tIPW       ps    Control and Address input Pulse Width
490      parameter TIS              =     190; // tIS        ps    Input Setup Time
491      parameter TIH              =     140; // tIH        ps    Input Hold Time
492      parameter TRAS_MIN         =   36000; // tRAS       ps    Minimum Active to Precharge command time
493      parameter TRC              =   49500; // tRC        ps    Active to Active/Auto Refresh command time
494      parameter TRCD             =   13125; // tRCD       ps    Active to Read/Write command time
495      parameter TRP              =   13125; // tRP        ps    Precharge command period
496      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
497      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
498      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
499      parameter TWLS             =     195; // tWLS       ps    Setup time for tDQS flop
500      parameter TWLH             =     195; // tWLH       ps    Hold time of tDQS flop
501      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
502      parameter TAA_MIN          =   13125; // TAA        ps    Internal READ command to first data
503      parameter CL_TIME          =   13125; // CL         ps    Minimum CAS Latency
504  `else `ifdef sg15                         // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin
505      parameter TCK_MIN          =    1500; // tCK        ps    Minimum Clock Cycle Time
506      parameter TJIT_PER         =      80; // tJIT(per)  ps    Period JItter
507      parameter TJIT_CC          =     160; // tJIT(cc)   ps    Cycle to Cycle jitter
508      parameter TERR_2PER        =     118; // tERR(2per) ps    Accumulated Error (2-cycle)
509      parameter TERR_3PER        =     140; // tERR(3per) ps    Accumulated Error (3-cycle)
510      parameter TERR_4PER        =     155; // tERR(4per) ps    Accumulated Error (4-cycle)
511      parameter TERR_5PER        =     168; // tERR(5per) ps    Accumulated Error (5-cycle)
512      parameter TERR_6PER        =     177; // tERR(6per) ps    Accumulated Error (6-cycle)
513      parameter TERR_7PER        =     186; // tERR(7per) ps    Accumulated Error (7-cycle)
514      parameter TERR_8PER        =     193; // tERR(8per) ps    Accumulated Error (8-cycle)
515      parameter TERR_9PER        =     200; // tERR(9per) ps    Accumulated Error (9-cycle)
516      parameter TERR_10PER       =     205; // tERR(10per)ps    Accumulated Error (10-cycle)
517      parameter TERR_11PER       =     210; // tERR(11per)ps    Accumulated Error (11-cycle)
518      parameter TERR_12PER       =     215; // tERR(12per)ps    Accumulated Error (12-cycle)
519      parameter TDS              =      30; // tDS        ps    DQ and DM input setup time relative to DQS
520      parameter TDH              =      65; // tDH        ps    DQ and DM input hold time relative to DQS
521      parameter TDQSQ            =     125; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
522      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
523      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
524      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
525      parameter TDQSCK           =     255; // tDQSCK     ps    DQS output access time from CK/CK#
526      parameter TQSH             =    0.40; // tQSH       tCK   DQS Output High Pulse Width
527      parameter TQSL             =    0.40; // tQSL       tCK   DQS Output Low Pulse Width
528      parameter TDIPW            =     400; // tDIPW      ps    DQ and DM input Pulse Width
529      parameter TIPW             =     620; // tIPW       ps    Control and Address input Pulse Width
530      parameter TIS              =     190; // tIS        ps    Input Setup Time
531      parameter TIH              =     140; // tIH        ps    Input Hold Time
532      parameter TRAS_MIN         =   36000; // tRAS       ps    Minimum Active to Precharge command time
533      parameter TRC              =   51000; // tRC        ps    Active to Active/Auto Refresh command time
534      parameter TRCD             =   15000; // tRCD       ps    Active to Read/Write command time
535      parameter TRP              =   15000; // tRP        ps    Precharge command period
536      parameter TXP              =    6000; // tXP        ps    Exit power down to a valid command
537      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
538      parameter TAON             =     250; // tAON       ps    RTT turn-on from ODTLon reference
539      parameter TWLS             =     195; // tWLS       ps    Setup time for tDQS flop
540      parameter TWLH             =     195; // tWLH       ps    Hold time of tDQS flop
541      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
542      parameter TAA_MIN          =   15000; // TAA        ps    Internal READ command to first data
543      parameter CL_TIME          =   15000; // CL         ps    Minimum CAS Latency
544  `else `ifdef sg187E                       // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin
545      parameter TCK_MIN          =    1875; // tCK        ps    Minimum Clock Cycle Time
546      parameter TJIT_PER         =      90; // tJIT(per)  ps    Period JItter
547      parameter TJIT_CC          =     180; // tJIT(cc)   ps    Cycle to Cycle jitter
548      parameter TERR_2PER        =     132; // tERR(2per) ps    Accumulated Error (2-cycle)
549      parameter TERR_3PER        =     157; // tERR(3per) ps    Accumulated Error (3-cycle)
550      parameter TERR_4PER        =     175; // tERR(4per) ps    Accumulated Error (4-cycle)
551      parameter TERR_5PER        =     188; // tERR(5per) ps    Accumulated Error (5-cycle)
552      parameter TERR_6PER        =     200; // tERR(6per) ps    Accumulated Error (6-cycle)
553      parameter TERR_7PER        =     209; // tERR(7per) ps    Accumulated Error (7-cycle)
554      parameter TERR_8PER        =     217; // tERR(8per) ps    Accumulated Error (8-cycle)
555      parameter TERR_9PER        =     224; // tERR(9per) ps    Accumulated Error (9-cycle)
556      parameter TERR_10PER       =     231; // tERR(10per)ps    Accumulated Error (10-cycle)
557      parameter TERR_11PER       =     237; // tERR(11per)ps    Accumulated Error (11-cycle)
558      parameter TERR_12PER       =     242; // tERR(12per)ps    Accumulated Error (12-cycle)
559      parameter TDS              =      75; // tDS        ps    DQ and DM input setup time relative to DQS
560      parameter TDH              =     100; // tDH        ps    DQ and DM input hold time relative to DQS
561      parameter TDQSQ            =     150; // tDQSQ      ps    DQS-DQ skew, DQS to last DQ valid, per group, per access
562      parameter TDQSS            =    0.25; // tDQSS      tCK   Rising clock edge to DQS/DQS# latching transition
563      parameter TDSS             =    0.20; // tDSS       tCK   DQS falling edge to CLK rising (setup time)
564      parameter TDSH             =    0.20; // tDSH       tCK   DQS falling edge from CLK rising (hold time)
565      parameter TDQSCK           =     300; // tDQSCK     ps    DQS output access time from CK/CK#
566      parameter TQSH             =    0.38; // tQSH       tCK   DQS Output High Pulse Width
567      parameter TQSL             =    0.38; // tQSL       tCK   DQS Output Low Pulse Width
568      parameter TDIPW            =     490; // tDIPW      ps    DQ and DM input Pulse Width
569      parameter TIPW             =     780; // tIPW       ps    Control and Address input Pulse Width
570      parameter TIS              =     275; // tIS        ps    Input Setup Time
571      parameter TIH              =     200; // tIH        ps    Input Hold Time
572      parameter TRAS_MIN         =   37500; // tRAS       ps    Minimum Active to Precharge command time
573      parameter TRC              =   50625; // tRC        ps    Active to Active/Auto Refresh command time
574      parameter TRCD             =   13125; // tRCD       ps    Active to Read/Write command time
575      parameter TRP              =   13125; // tRP        ps    Precharge command period
576      parameter TXP              =    7500; // tXP        ps    Exit power down to a valid command
577      parameter TCKE             =    5625; // tCKE       ps    CKE minimum high or low pulse width
578      parameter TAON             =     300; // tAON       ps    RTT turn-on from ODTLon reference
579      parameter TWLS             =     245; // tWLS       ps    Setup time for tDQS flop
580      parameter TWLH             =     245; // tWLH       ps    Hold time of tDQS flop
581      parameter TWLO             =    9000; // tWLO       ps    Write levelization output delay
582      parameter TAA_MIN          =   13125; // TAA        ps    Internal READ command to first data
583      parameter CL_TIME          =   13125; // CL         ps    Minimum CAS Latency
584  `else `ifdef sg187                        // sg187  is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin
585      parameter TCK_MIN          =    1875; // tCK        ps    Minimum Clock Cycle Time
586      parameter TJIT_PER         =      90; // tJIT(per)  ps    Period JItter
587      parameter TJIT_CC          =     180; // tJIT(cc)   ps    Cycle to Cycle jitter
588      parameter TERR_2PER  

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