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/drivers/gpu/drm/radeon/cypress_dpm.c

http://github.com/mirrors/linux
C | 2166 lines | 1737 code | 401 blank | 28 comment | 288 complexity | 4216a584fb9f137b9c6f00a1ccb9cc55 MD5 | raw file
Possible License(s): AGPL-1.0, GPL-2.0, LGPL-2.0

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  1. /*
  2. * Copyright 2011 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. */
  24. #include <linux/pci.h>
  25. #include "atom.h"
  26. #include "cypress_dpm.h"
  27. #include "evergreend.h"
  28. #include "r600_dpm.h"
  29. #include "radeon.h"
  30. #include "radeon_asic.h"
  31. #define SMC_RAM_END 0x8000
  32. #define MC_CG_ARB_FREQ_F0 0x0a
  33. #define MC_CG_ARB_FREQ_F1 0x0b
  34. #define MC_CG_ARB_FREQ_F2 0x0c
  35. #define MC_CG_ARB_FREQ_F3 0x0d
  36. #define MC_CG_SEQ_DRAMCONF_S0 0x05
  37. #define MC_CG_SEQ_DRAMCONF_S1 0x06
  38. #define MC_CG_SEQ_YCLK_SUSPEND 0x04
  39. #define MC_CG_SEQ_YCLK_RESUME 0x0a
  40. struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps);
  41. struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
  42. struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
  43. static void cypress_enable_bif_dynamic_pcie_gen2(struct radeon_device *rdev,
  44. bool enable)
  45. {
  46. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  47. u32 tmp, bif;
  48. tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  49. if (enable) {
  50. if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
  51. (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
  52. if (!pi->boot_in_gen2) {
  53. bif = RREG32(CG_BIF_REQ_AND_RSP) & ~CG_CLIENT_REQ_MASK;
  54. bif |= CG_CLIENT_REQ(0xd);
  55. WREG32(CG_BIF_REQ_AND_RSP, bif);
  56. tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
  57. tmp |= LC_HW_VOLTAGE_IF_CONTROL(1);
  58. tmp |= LC_GEN2_EN_STRAP;
  59. tmp |= LC_CLR_FAILED_SPD_CHANGE_CNT;
  60. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  61. udelay(10);
  62. tmp &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
  63. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  64. }
  65. }
  66. } else {
  67. if (!pi->boot_in_gen2) {
  68. tmp &= ~LC_HW_VOLTAGE_IF_CONTROL_MASK;
  69. tmp &= ~LC_GEN2_EN_STRAP;
  70. }
  71. if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
  72. (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
  73. WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, tmp);
  74. }
  75. }
  76. static void cypress_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
  77. bool enable)
  78. {
  79. cypress_enable_bif_dynamic_pcie_gen2(rdev, enable);
  80. if (enable)
  81. WREG32_P(GENERAL_PWRMGT, ENABLE_GEN2PCIE, ~ENABLE_GEN2PCIE);
  82. else
  83. WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
  84. }
  85. #if 0
  86. static int cypress_enter_ulp_state(struct radeon_device *rdev)
  87. {
  88. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  89. if (pi->gfx_clock_gating) {
  90. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
  91. WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
  92. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
  93. RREG32(GB_ADDR_CONFIG);
  94. }
  95. WREG32_P(SMC_MSG, HOST_SMC_MSG(PPSMC_MSG_SwitchToMinimumPower),
  96. ~HOST_SMC_MSG_MASK);
  97. udelay(7000);
  98. return 0;
  99. }
  100. #endif
  101. static void cypress_gfx_clock_gating_enable(struct radeon_device *rdev,
  102. bool enable)
  103. {
  104. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  105. if (enable) {
  106. if (eg_pi->light_sleep) {
  107. WREG32(GRBM_GFX_INDEX, 0xC0000000);
  108. WREG32_CG(CG_CGLS_TILE_0, 0xFFFFFFFF);
  109. WREG32_CG(CG_CGLS_TILE_1, 0xFFFFFFFF);
  110. WREG32_CG(CG_CGLS_TILE_2, 0xFFFFFFFF);
  111. WREG32_CG(CG_CGLS_TILE_3, 0xFFFFFFFF);
  112. WREG32_CG(CG_CGLS_TILE_4, 0xFFFFFFFF);
  113. WREG32_CG(CG_CGLS_TILE_5, 0xFFFFFFFF);
  114. WREG32_CG(CG_CGLS_TILE_6, 0xFFFFFFFF);
  115. WREG32_CG(CG_CGLS_TILE_7, 0xFFFFFFFF);
  116. WREG32_CG(CG_CGLS_TILE_8, 0xFFFFFFFF);
  117. WREG32_CG(CG_CGLS_TILE_9, 0xFFFFFFFF);
  118. WREG32_CG(CG_CGLS_TILE_10, 0xFFFFFFFF);
  119. WREG32_CG(CG_CGLS_TILE_11, 0xFFFFFFFF);
  120. WREG32_P(SCLK_PWRMGT_CNTL, DYN_LIGHT_SLEEP_EN, ~DYN_LIGHT_SLEEP_EN);
  121. }
  122. WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
  123. } else {
  124. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
  125. WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
  126. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
  127. RREG32(GB_ADDR_CONFIG);
  128. if (eg_pi->light_sleep) {
  129. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_LIGHT_SLEEP_EN);
  130. WREG32(GRBM_GFX_INDEX, 0xC0000000);
  131. WREG32_CG(CG_CGLS_TILE_0, 0);
  132. WREG32_CG(CG_CGLS_TILE_1, 0);
  133. WREG32_CG(CG_CGLS_TILE_2, 0);
  134. WREG32_CG(CG_CGLS_TILE_3, 0);
  135. WREG32_CG(CG_CGLS_TILE_4, 0);
  136. WREG32_CG(CG_CGLS_TILE_5, 0);
  137. WREG32_CG(CG_CGLS_TILE_6, 0);
  138. WREG32_CG(CG_CGLS_TILE_7, 0);
  139. WREG32_CG(CG_CGLS_TILE_8, 0);
  140. WREG32_CG(CG_CGLS_TILE_9, 0);
  141. WREG32_CG(CG_CGLS_TILE_10, 0);
  142. WREG32_CG(CG_CGLS_TILE_11, 0);
  143. }
  144. }
  145. }
  146. static void cypress_mg_clock_gating_enable(struct radeon_device *rdev,
  147. bool enable)
  148. {
  149. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  150. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  151. if (enable) {
  152. u32 cgts_sm_ctrl_reg;
  153. if (rdev->family == CHIP_CEDAR)
  154. cgts_sm_ctrl_reg = CEDAR_MGCGCGTSSMCTRL_DFLT;
  155. else if (rdev->family == CHIP_REDWOOD)
  156. cgts_sm_ctrl_reg = REDWOOD_MGCGCGTSSMCTRL_DFLT;
  157. else
  158. cgts_sm_ctrl_reg = CYPRESS_MGCGCGTSSMCTRL_DFLT;
  159. WREG32(GRBM_GFX_INDEX, 0xC0000000);
  160. WREG32_CG(CG_CGTT_LOCAL_0, CYPRESS_MGCGTTLOCAL0_DFLT);
  161. WREG32_CG(CG_CGTT_LOCAL_1, CYPRESS_MGCGTTLOCAL1_DFLT & 0xFFFFCFFF);
  162. WREG32_CG(CG_CGTT_LOCAL_2, CYPRESS_MGCGTTLOCAL2_DFLT);
  163. WREG32_CG(CG_CGTT_LOCAL_3, CYPRESS_MGCGTTLOCAL3_DFLT);
  164. if (pi->mgcgtssm)
  165. WREG32(CGTS_SM_CTRL_REG, cgts_sm_ctrl_reg);
  166. if (eg_pi->mcls) {
  167. WREG32_P(MC_CITF_MISC_RD_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
  168. WREG32_P(MC_CITF_MISC_WR_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
  169. WREG32_P(MC_CITF_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
  170. WREG32_P(MC_HUB_MISC_HUB_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
  171. WREG32_P(MC_HUB_MISC_VM_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
  172. WREG32_P(MC_HUB_MISC_SIP_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
  173. WREG32_P(MC_XPB_CLK_GAT, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
  174. WREG32_P(VM_L2_CG, MEM_LS_ENABLE, ~MEM_LS_ENABLE);
  175. }
  176. } else {
  177. WREG32(GRBM_GFX_INDEX, 0xC0000000);
  178. WREG32_CG(CG_CGTT_LOCAL_0, 0xFFFFFFFF);
  179. WREG32_CG(CG_CGTT_LOCAL_1, 0xFFFFFFFF);
  180. WREG32_CG(CG_CGTT_LOCAL_2, 0xFFFFFFFF);
  181. WREG32_CG(CG_CGTT_LOCAL_3, 0xFFFFFFFF);
  182. if (pi->mgcgtssm)
  183. WREG32(CGTS_SM_CTRL_REG, 0x81f44bc0);
  184. }
  185. }
  186. void cypress_enable_spread_spectrum(struct radeon_device *rdev,
  187. bool enable)
  188. {
  189. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  190. if (enable) {
  191. if (pi->sclk_ss)
  192. WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
  193. if (pi->mclk_ss)
  194. WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN);
  195. } else {
  196. WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
  197. WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
  198. WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN);
  199. WREG32_P(MPLL_CNTL_MODE, 0, ~SS_DSMODE_EN);
  200. }
  201. }
  202. void cypress_start_dpm(struct radeon_device *rdev)
  203. {
  204. WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
  205. }
  206. void cypress_enable_sclk_control(struct radeon_device *rdev,
  207. bool enable)
  208. {
  209. if (enable)
  210. WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
  211. else
  212. WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
  213. }
  214. void cypress_enable_mclk_control(struct radeon_device *rdev,
  215. bool enable)
  216. {
  217. if (enable)
  218. WREG32_P(MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF);
  219. else
  220. WREG32_P(MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF);
  221. }
  222. int cypress_notify_smc_display_change(struct radeon_device *rdev,
  223. bool has_display)
  224. {
  225. PPSMC_Msg msg = has_display ?
  226. (PPSMC_Msg)PPSMC_MSG_HasDisplay : (PPSMC_Msg)PPSMC_MSG_NoDisplay;
  227. if (rv770_send_msg_to_smc(rdev, msg) != PPSMC_Result_OK)
  228. return -EINVAL;
  229. return 0;
  230. }
  231. void cypress_program_response_times(struct radeon_device *rdev)
  232. {
  233. u32 reference_clock;
  234. u32 mclk_switch_limit;
  235. reference_clock = radeon_get_xclk(rdev);
  236. mclk_switch_limit = (460 * reference_clock) / 100;
  237. rv770_write_smc_soft_register(rdev,
  238. RV770_SMC_SOFT_REGISTER_mclk_switch_lim,
  239. mclk_switch_limit);
  240. rv770_write_smc_soft_register(rdev,
  241. RV770_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
  242. rv770_write_smc_soft_register(rdev,
  243. RV770_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
  244. rv770_program_response_times(rdev);
  245. if (ASIC_IS_LOMBOK(rdev))
  246. rv770_write_smc_soft_register(rdev,
  247. RV770_SMC_SOFT_REGISTER_is_asic_lombok, 1);
  248. }
  249. static int cypress_pcie_performance_request(struct radeon_device *rdev,
  250. u8 perf_req, bool advertise)
  251. {
  252. #if defined(CONFIG_ACPI)
  253. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  254. #endif
  255. u32 tmp;
  256. udelay(10);
  257. tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  258. if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) && (tmp & LC_CURRENT_DATA_RATE))
  259. return 0;
  260. #if defined(CONFIG_ACPI)
  261. if ((perf_req == PCIE_PERF_REQ_PECI_GEN1) ||
  262. (perf_req == PCIE_PERF_REQ_PECI_GEN2)) {
  263. eg_pi->pcie_performance_request_registered = true;
  264. return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
  265. } else if ((perf_req == PCIE_PERF_REQ_REMOVE_REGISTRY) &&
  266. eg_pi->pcie_performance_request_registered) {
  267. eg_pi->pcie_performance_request_registered = false;
  268. return radeon_acpi_pcie_performance_request(rdev, perf_req, advertise);
  269. }
  270. #endif
  271. return 0;
  272. }
  273. void cypress_advertise_gen2_capability(struct radeon_device *rdev)
  274. {
  275. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  276. u32 tmp;
  277. #if defined(CONFIG_ACPI)
  278. radeon_acpi_pcie_notify_device_ready(rdev);
  279. #endif
  280. tmp = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
  281. if ((tmp & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
  282. (tmp & LC_OTHER_SIDE_SUPPORTS_GEN2))
  283. pi->pcie_gen2 = true;
  284. else
  285. pi->pcie_gen2 = false;
  286. if (!pi->pcie_gen2)
  287. cypress_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, true);
  288. }
  289. static enum radeon_pcie_gen cypress_get_maximum_link_speed(struct radeon_ps *radeon_state)
  290. {
  291. struct rv7xx_ps *state = rv770_get_ps(radeon_state);
  292. if (state->high.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
  293. return 1;
  294. return 0;
  295. }
  296. void cypress_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
  297. struct radeon_ps *radeon_new_state,
  298. struct radeon_ps *radeon_current_state)
  299. {
  300. enum radeon_pcie_gen pcie_link_speed_target =
  301. cypress_get_maximum_link_speed(radeon_new_state);
  302. enum radeon_pcie_gen pcie_link_speed_current =
  303. cypress_get_maximum_link_speed(radeon_current_state);
  304. u8 request;
  305. if (pcie_link_speed_target < pcie_link_speed_current) {
  306. if (pcie_link_speed_target == RADEON_PCIE_GEN1)
  307. request = PCIE_PERF_REQ_PECI_GEN1;
  308. else if (pcie_link_speed_target == RADEON_PCIE_GEN2)
  309. request = PCIE_PERF_REQ_PECI_GEN2;
  310. else
  311. request = PCIE_PERF_REQ_PECI_GEN3;
  312. cypress_pcie_performance_request(rdev, request, false);
  313. }
  314. }
  315. void cypress_notify_link_speed_change_before_state_change(struct radeon_device *rdev,
  316. struct radeon_ps *radeon_new_state,
  317. struct radeon_ps *radeon_current_state)
  318. {
  319. enum radeon_pcie_gen pcie_link_speed_target =
  320. cypress_get_maximum_link_speed(radeon_new_state);
  321. enum radeon_pcie_gen pcie_link_speed_current =
  322. cypress_get_maximum_link_speed(radeon_current_state);
  323. u8 request;
  324. if (pcie_link_speed_target > pcie_link_speed_current) {
  325. if (pcie_link_speed_target == RADEON_PCIE_GEN1)
  326. request = PCIE_PERF_REQ_PECI_GEN1;
  327. else if (pcie_link_speed_target == RADEON_PCIE_GEN2)
  328. request = PCIE_PERF_REQ_PECI_GEN2;
  329. else
  330. request = PCIE_PERF_REQ_PECI_GEN3;
  331. cypress_pcie_performance_request(rdev, request, false);
  332. }
  333. }
  334. static int cypress_populate_voltage_value(struct radeon_device *rdev,
  335. struct atom_voltage_table *table,
  336. u16 value, RV770_SMC_VOLTAGE_VALUE *voltage)
  337. {
  338. unsigned int i;
  339. for (i = 0; i < table->count; i++) {
  340. if (value <= table->entries[i].value) {
  341. voltage->index = (u8)i;
  342. voltage->value = cpu_to_be16(table->entries[i].value);
  343. break;
  344. }
  345. }
  346. if (i == table->count)
  347. return -EINVAL;
  348. return 0;
  349. }
  350. u8 cypress_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
  351. {
  352. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  353. u8 result = 0;
  354. bool strobe_mode = false;
  355. if (pi->mem_gddr5) {
  356. if (mclk <= pi->mclk_strobe_mode_threshold)
  357. strobe_mode = true;
  358. result = cypress_get_mclk_frequency_ratio(rdev, mclk, strobe_mode);
  359. if (strobe_mode)
  360. result |= SMC_STROBE_ENABLE;
  361. }
  362. return result;
  363. }
  364. u32 cypress_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf)
  365. {
  366. u32 ref_clk = rdev->clock.mpll.reference_freq;
  367. u32 vco = clkf * ref_clk;
  368. /* 100 Mhz ref clk */
  369. if (ref_clk == 10000) {
  370. if (vco > 500000)
  371. return 0xC6;
  372. if (vco > 400000)
  373. return 0x9D;
  374. if (vco > 330000)
  375. return 0x6C;
  376. if (vco > 250000)
  377. return 0x2B;
  378. if (vco > 160000)
  379. return 0x5B;
  380. if (vco > 120000)
  381. return 0x0A;
  382. return 0x4B;
  383. }
  384. /* 27 Mhz ref clk */
  385. if (vco > 250000)
  386. return 0x8B;
  387. if (vco > 200000)
  388. return 0xCC;
  389. if (vco > 150000)
  390. return 0x9B;
  391. return 0x6B;
  392. }
  393. static int cypress_populate_mclk_value(struct radeon_device *rdev,
  394. u32 engine_clock, u32 memory_clock,
  395. RV7XX_SMC_MCLK_VALUE *mclk,
  396. bool strobe_mode, bool dll_state_on)
  397. {
  398. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  399. u32 mpll_ad_func_cntl =
  400. pi->clk_regs.rv770.mpll_ad_func_cntl;
  401. u32 mpll_ad_func_cntl_2 =
  402. pi->clk_regs.rv770.mpll_ad_func_cntl_2;
  403. u32 mpll_dq_func_cntl =
  404. pi->clk_regs.rv770.mpll_dq_func_cntl;
  405. u32 mpll_dq_func_cntl_2 =
  406. pi->clk_regs.rv770.mpll_dq_func_cntl_2;
  407. u32 mclk_pwrmgt_cntl =
  408. pi->clk_regs.rv770.mclk_pwrmgt_cntl;
  409. u32 dll_cntl =
  410. pi->clk_regs.rv770.dll_cntl;
  411. u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1;
  412. u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2;
  413. struct atom_clock_dividers dividers;
  414. u32 ibias;
  415. u32 dll_speed;
  416. int ret;
  417. u32 mc_seq_misc7;
  418. ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM,
  419. memory_clock, strobe_mode, &dividers);
  420. if (ret)
  421. return ret;
  422. if (!strobe_mode) {
  423. mc_seq_misc7 = RREG32(MC_SEQ_MISC7);
  424. if(mc_seq_misc7 & 0x8000000)
  425. dividers.post_div = 1;
  426. }
  427. ibias = cypress_map_clkf_to_ibias(rdev, dividers.whole_fb_div);
  428. mpll_ad_func_cntl &= ~(CLKR_MASK |
  429. YCLK_POST_DIV_MASK |
  430. CLKF_MASK |
  431. CLKFRAC_MASK |
  432. IBIAS_MASK);
  433. mpll_ad_func_cntl |= CLKR(dividers.ref_div);
  434. mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div);
  435. mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div);
  436. mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div);
  437. mpll_ad_func_cntl |= IBIAS(ibias);
  438. if (dividers.vco_mode)
  439. mpll_ad_func_cntl_2 |= VCO_MODE;
  440. else
  441. mpll_ad_func_cntl_2 &= ~VCO_MODE;
  442. if (pi->mem_gddr5) {
  443. mpll_dq_func_cntl &= ~(CLKR_MASK |
  444. YCLK_POST_DIV_MASK |
  445. CLKF_MASK |
  446. CLKFRAC_MASK |
  447. IBIAS_MASK);
  448. mpll_dq_func_cntl |= CLKR(dividers.ref_div);
  449. mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div);
  450. mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div);
  451. mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div);
  452. mpll_dq_func_cntl |= IBIAS(ibias);
  453. if (strobe_mode)
  454. mpll_dq_func_cntl &= ~PDNB;
  455. else
  456. mpll_dq_func_cntl |= PDNB;
  457. if (dividers.vco_mode)
  458. mpll_dq_func_cntl_2 |= VCO_MODE;
  459. else
  460. mpll_dq_func_cntl_2 &= ~VCO_MODE;
  461. }
  462. if (pi->mclk_ss) {
  463. struct radeon_atom_ss ss;
  464. u32 vco_freq = memory_clock * dividers.post_div;
  465. if (radeon_atombios_get_asic_ss_info(rdev, &ss,
  466. ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
  467. u32 reference_clock = rdev->clock.mpll.reference_freq;
  468. u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
  469. u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
  470. u32 clk_v = ss.percentage *
  471. (0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
  472. mpll_ss1 &= ~CLKV_MASK;
  473. mpll_ss1 |= CLKV(clk_v);
  474. mpll_ss2 &= ~CLKS_MASK;
  475. mpll_ss2 |= CLKS(clk_s);
  476. }
  477. }
  478. dll_speed = rv740_get_dll_speed(pi->mem_gddr5,
  479. memory_clock);
  480. mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
  481. mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed);
  482. if (dll_state_on)
  483. mclk_pwrmgt_cntl |= (MRDCKA0_PDNB |
  484. MRDCKA1_PDNB |
  485. MRDCKB0_PDNB |
  486. MRDCKB1_PDNB |
  487. MRDCKC0_PDNB |
  488. MRDCKC1_PDNB |
  489. MRDCKD0_PDNB |
  490. MRDCKD1_PDNB);
  491. else
  492. mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
  493. MRDCKA1_PDNB |
  494. MRDCKB0_PDNB |
  495. MRDCKB1_PDNB |
  496. MRDCKC0_PDNB |
  497. MRDCKC1_PDNB |
  498. MRDCKD0_PDNB |
  499. MRDCKD1_PDNB);
  500. mclk->mclk770.mclk_value = cpu_to_be32(memory_clock);
  501. mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
  502. mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2);
  503. mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
  504. mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2);
  505. mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
  506. mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
  507. mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1);
  508. mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
  509. return 0;
  510. }
  511. u8 cypress_get_mclk_frequency_ratio(struct radeon_device *rdev,
  512. u32 memory_clock, bool strobe_mode)
  513. {
  514. u8 mc_para_index;
  515. if (rdev->family >= CHIP_BARTS) {
  516. if (strobe_mode) {
  517. if (memory_clock < 10000)
  518. mc_para_index = 0x00;
  519. else if (memory_clock > 47500)
  520. mc_para_index = 0x0f;
  521. else
  522. mc_para_index = (u8)((memory_clock - 10000) / 2500);
  523. } else {
  524. if (memory_clock < 65000)
  525. mc_para_index = 0x00;
  526. else if (memory_clock > 135000)
  527. mc_para_index = 0x0f;
  528. else
  529. mc_para_index = (u8)((memory_clock - 60000) / 5000);
  530. }
  531. } else {
  532. if (strobe_mode) {
  533. if (memory_clock < 10000)
  534. mc_para_index = 0x00;
  535. else if (memory_clock > 47500)
  536. mc_para_index = 0x0f;
  537. else
  538. mc_para_index = (u8)((memory_clock - 10000) / 2500);
  539. } else {
  540. if (memory_clock < 40000)
  541. mc_para_index = 0x00;
  542. else if (memory_clock > 115000)
  543. mc_para_index = 0x0f;
  544. else
  545. mc_para_index = (u8)((memory_clock - 40000) / 5000);
  546. }
  547. }
  548. return mc_para_index;
  549. }
  550. static int cypress_populate_mvdd_value(struct radeon_device *rdev,
  551. u32 mclk,
  552. RV770_SMC_VOLTAGE_VALUE *voltage)
  553. {
  554. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  555. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  556. if (!pi->mvdd_control) {
  557. voltage->index = eg_pi->mvdd_high_index;
  558. voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
  559. return 0;
  560. }
  561. if (mclk <= pi->mvdd_split_frequency) {
  562. voltage->index = eg_pi->mvdd_low_index;
  563. voltage->value = cpu_to_be16(MVDD_LOW_VALUE);
  564. } else {
  565. voltage->index = eg_pi->mvdd_high_index;
  566. voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
  567. }
  568. return 0;
  569. }
  570. int cypress_convert_power_level_to_smc(struct radeon_device *rdev,
  571. struct rv7xx_pl *pl,
  572. RV770_SMC_HW_PERFORMANCE_LEVEL *level,
  573. u8 watermark_level)
  574. {
  575. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  576. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  577. int ret;
  578. bool dll_state_on;
  579. level->gen2PCIE = pi->pcie_gen2 ?
  580. ((pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0) : 0;
  581. level->gen2XSP = (pl->flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) ? 1 : 0;
  582. level->backbias = (pl->flags & ATOM_PPLIB_R600_FLAGS_BACKBIASENABLE) ? 1 : 0;
  583. level->displayWatermark = watermark_level;
  584. ret = rv740_populate_sclk_value(rdev, pl->sclk, &level->sclk);
  585. if (ret)
  586. return ret;
  587. level->mcFlags = 0;
  588. if (pi->mclk_stutter_mode_threshold &&
  589. (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
  590. !eg_pi->uvd_enabled) {
  591. level->mcFlags |= SMC_MC_STUTTER_EN;
  592. if (eg_pi->sclk_deep_sleep)
  593. level->stateFlags |= PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
  594. else
  595. level->stateFlags &= ~PPSMC_STATEFLAG_AUTO_PULSE_SKIP;
  596. }
  597. if (pi->mem_gddr5) {
  598. if (pl->mclk > pi->mclk_edc_enable_threshold)
  599. level->mcFlags |= SMC_MC_EDC_RD_FLAG;
  600. if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
  601. level->mcFlags |= SMC_MC_EDC_WR_FLAG;
  602. level->strobeMode = cypress_get_strobe_mode_settings(rdev, pl->mclk);
  603. if (level->strobeMode & SMC_STROBE_ENABLE) {
  604. if (cypress_get_mclk_frequency_ratio(rdev, pl->mclk, true) >=
  605. ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
  606. dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
  607. else
  608. dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
  609. } else
  610. dll_state_on = eg_pi->dll_default_on;
  611. ret = cypress_populate_mclk_value(rdev,
  612. pl->sclk,
  613. pl->mclk,
  614. &level->mclk,
  615. (level->strobeMode & SMC_STROBE_ENABLE) != 0,
  616. dll_state_on);
  617. } else {
  618. ret = cypress_populate_mclk_value(rdev,
  619. pl->sclk,
  620. pl->mclk,
  621. &level->mclk,
  622. true,
  623. true);
  624. }
  625. if (ret)
  626. return ret;
  627. ret = cypress_populate_voltage_value(rdev,
  628. &eg_pi->vddc_voltage_table,
  629. pl->vddc,
  630. &level->vddc);
  631. if (ret)
  632. return ret;
  633. if (eg_pi->vddci_control) {
  634. ret = cypress_populate_voltage_value(rdev,
  635. &eg_pi->vddci_voltage_table,
  636. pl->vddci,
  637. &level->vddci);
  638. if (ret)
  639. return ret;
  640. }
  641. ret = cypress_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
  642. return ret;
  643. }
  644. static int cypress_convert_power_state_to_smc(struct radeon_device *rdev,
  645. struct radeon_ps *radeon_state,
  646. RV770_SMC_SWSTATE *smc_state)
  647. {
  648. struct rv7xx_ps *state = rv770_get_ps(radeon_state);
  649. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  650. int ret;
  651. if (!(radeon_state->caps & ATOM_PPLIB_DISALLOW_ON_DC))
  652. smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
  653. ret = cypress_convert_power_level_to_smc(rdev,
  654. &state->low,
  655. &smc_state->levels[0],
  656. PPSMC_DISPLAY_WATERMARK_LOW);
  657. if (ret)
  658. return ret;
  659. ret = cypress_convert_power_level_to_smc(rdev,
  660. &state->medium,
  661. &smc_state->levels[1],
  662. PPSMC_DISPLAY_WATERMARK_LOW);
  663. if (ret)
  664. return ret;
  665. ret = cypress_convert_power_level_to_smc(rdev,
  666. &state->high,
  667. &smc_state->levels[2],
  668. PPSMC_DISPLAY_WATERMARK_HIGH);
  669. if (ret)
  670. return ret;
  671. smc_state->levels[0].arbValue = MC_CG_ARB_FREQ_F1;
  672. smc_state->levels[1].arbValue = MC_CG_ARB_FREQ_F2;
  673. smc_state->levels[2].arbValue = MC_CG_ARB_FREQ_F3;
  674. if (eg_pi->dynamic_ac_timing) {
  675. smc_state->levels[0].ACIndex = 2;
  676. smc_state->levels[1].ACIndex = 3;
  677. smc_state->levels[2].ACIndex = 4;
  678. } else {
  679. smc_state->levels[0].ACIndex = 0;
  680. smc_state->levels[1].ACIndex = 0;
  681. smc_state->levels[2].ACIndex = 0;
  682. }
  683. rv770_populate_smc_sp(rdev, radeon_state, smc_state);
  684. return rv770_populate_smc_t(rdev, radeon_state, smc_state);
  685. }
  686. static void cypress_convert_mc_registers(struct evergreen_mc_reg_entry *entry,
  687. SMC_Evergreen_MCRegisterSet *data,
  688. u32 num_entries, u32 valid_flag)
  689. {
  690. u32 i, j;
  691. for (i = 0, j = 0; j < num_entries; j++) {
  692. if (valid_flag & (1 << j)) {
  693. data->value[i] = cpu_to_be32(entry->mc_data[j]);
  694. i++;
  695. }
  696. }
  697. }
  698. static void cypress_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
  699. struct rv7xx_pl *pl,
  700. SMC_Evergreen_MCRegisterSet *mc_reg_table_data)
  701. {
  702. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  703. u32 i = 0;
  704. for (i = 0; i < eg_pi->mc_reg_table.num_entries; i++) {
  705. if (pl->mclk <=
  706. eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
  707. break;
  708. }
  709. if ((i == eg_pi->mc_reg_table.num_entries) && (i > 0))
  710. --i;
  711. cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[i],
  712. mc_reg_table_data,
  713. eg_pi->mc_reg_table.last,
  714. eg_pi->mc_reg_table.valid_flag);
  715. }
  716. static void cypress_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
  717. struct radeon_ps *radeon_state,
  718. SMC_Evergreen_MCRegisters *mc_reg_table)
  719. {
  720. struct rv7xx_ps *state = rv770_get_ps(radeon_state);
  721. cypress_convert_mc_reg_table_entry_to_smc(rdev,
  722. &state->low,
  723. &mc_reg_table->data[2]);
  724. cypress_convert_mc_reg_table_entry_to_smc(rdev,
  725. &state->medium,
  726. &mc_reg_table->data[3]);
  727. cypress_convert_mc_reg_table_entry_to_smc(rdev,
  728. &state->high,
  729. &mc_reg_table->data[4]);
  730. }
  731. int cypress_upload_sw_state(struct radeon_device *rdev,
  732. struct radeon_ps *radeon_new_state)
  733. {
  734. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  735. u16 address = pi->state_table_start +
  736. offsetof(RV770_SMC_STATETABLE, driverState);
  737. RV770_SMC_SWSTATE state = { 0 };
  738. int ret;
  739. ret = cypress_convert_power_state_to_smc(rdev, radeon_new_state, &state);
  740. if (ret)
  741. return ret;
  742. return rv770_copy_bytes_to_smc(rdev, address, (u8 *)&state,
  743. sizeof(RV770_SMC_SWSTATE),
  744. pi->sram_end);
  745. }
  746. int cypress_upload_mc_reg_table(struct radeon_device *rdev,
  747. struct radeon_ps *radeon_new_state)
  748. {
  749. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  750. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  751. SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
  752. u16 address;
  753. cypress_convert_mc_reg_table_to_smc(rdev, radeon_new_state, &mc_reg_table);
  754. address = eg_pi->mc_reg_table_start +
  755. (u16)offsetof(SMC_Evergreen_MCRegisters, data[2]);
  756. return rv770_copy_bytes_to_smc(rdev, address,
  757. (u8 *)&mc_reg_table.data[2],
  758. sizeof(SMC_Evergreen_MCRegisterSet) * 3,
  759. pi->sram_end);
  760. }
  761. u32 cypress_calculate_burst_time(struct radeon_device *rdev,
  762. u32 engine_clock, u32 memory_clock)
  763. {
  764. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  765. u32 multiplier = pi->mem_gddr5 ? 1 : 2;
  766. u32 result = (4 * multiplier * engine_clock) / (memory_clock / 2);
  767. u32 burst_time;
  768. if (result <= 4)
  769. burst_time = 0;
  770. else if (result < 8)
  771. burst_time = result - 4;
  772. else {
  773. burst_time = result / 2 ;
  774. if (burst_time > 18)
  775. burst_time = 18;
  776. }
  777. return burst_time;
  778. }
  779. void cypress_program_memory_timing_parameters(struct radeon_device *rdev,
  780. struct radeon_ps *radeon_new_state)
  781. {
  782. struct rv7xx_ps *new_state = rv770_get_ps(radeon_new_state);
  783. u32 mc_arb_burst_time = RREG32(MC_ARB_BURST_TIME);
  784. mc_arb_burst_time &= ~(STATE1_MASK | STATE2_MASK | STATE3_MASK);
  785. mc_arb_burst_time |= STATE1(cypress_calculate_burst_time(rdev,
  786. new_state->low.sclk,
  787. new_state->low.mclk));
  788. mc_arb_burst_time |= STATE2(cypress_calculate_burst_time(rdev,
  789. new_state->medium.sclk,
  790. new_state->medium.mclk));
  791. mc_arb_burst_time |= STATE3(cypress_calculate_burst_time(rdev,
  792. new_state->high.sclk,
  793. new_state->high.mclk));
  794. rv730_program_memory_timing_parameters(rdev, radeon_new_state);
  795. WREG32(MC_ARB_BURST_TIME, mc_arb_burst_time);
  796. }
  797. static void cypress_populate_mc_reg_addresses(struct radeon_device *rdev,
  798. SMC_Evergreen_MCRegisters *mc_reg_table)
  799. {
  800. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  801. u32 i, j;
  802. for (i = 0, j = 0; j < eg_pi->mc_reg_table.last; j++) {
  803. if (eg_pi->mc_reg_table.valid_flag & (1 << j)) {
  804. mc_reg_table->address[i].s0 =
  805. cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s0);
  806. mc_reg_table->address[i].s1 =
  807. cpu_to_be16(eg_pi->mc_reg_table.mc_reg_address[j].s1);
  808. i++;
  809. }
  810. }
  811. mc_reg_table->last = (u8)i;
  812. }
  813. static void cypress_set_mc_reg_address_table(struct radeon_device *rdev)
  814. {
  815. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  816. u32 i = 0;
  817. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RAS_TIMING_LP >> 2;
  818. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RAS_TIMING >> 2;
  819. i++;
  820. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_CAS_TIMING_LP >> 2;
  821. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_CAS_TIMING >> 2;
  822. i++;
  823. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING_LP >> 2;
  824. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2;
  825. i++;
  826. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC_TIMING2_LP >> 2;
  827. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING2 >> 2;
  828. i++;
  829. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D0_LP >> 2;
  830. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D0 >> 2;
  831. i++;
  832. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RD_CTL_D1_LP >> 2;
  833. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RD_CTL_D1 >> 2;
  834. i++;
  835. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D0_LP >> 2;
  836. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D0 >> 2;
  837. i++;
  838. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_WR_CTL_D1_LP >> 2;
  839. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2;
  840. i++;
  841. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
  842. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_EMRS >> 2;
  843. i++;
  844. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
  845. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS >> 2;
  846. i++;
  847. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
  848. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_PMG_CMD_MRS1 >> 2;
  849. i++;
  850. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC1 >> 2;
  851. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC1 >> 2;
  852. i++;
  853. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_RESERVE_M >> 2;
  854. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_RESERVE_M >> 2;
  855. i++;
  856. eg_pi->mc_reg_table.mc_reg_address[i].s0 = MC_SEQ_MISC3 >> 2;
  857. eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC3 >> 2;
  858. i++;
  859. eg_pi->mc_reg_table.last = (u8)i;
  860. }
  861. static void cypress_retrieve_ac_timing_for_one_entry(struct radeon_device *rdev,
  862. struct evergreen_mc_reg_entry *entry)
  863. {
  864. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  865. u32 i;
  866. for (i = 0; i < eg_pi->mc_reg_table.last; i++)
  867. entry->mc_data[i] =
  868. RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
  869. }
  870. static void cypress_retrieve_ac_timing_for_all_ranges(struct radeon_device *rdev,
  871. struct atom_memory_clock_range_table *range_table)
  872. {
  873. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  874. u32 i, j;
  875. for (i = 0; i < range_table->num_entries; i++) {
  876. eg_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max =
  877. range_table->mclk[i];
  878. radeon_atom_set_ac_timing(rdev, range_table->mclk[i]);
  879. cypress_retrieve_ac_timing_for_one_entry(rdev,
  880. &eg_pi->mc_reg_table.mc_reg_table_entry[i]);
  881. }
  882. eg_pi->mc_reg_table.num_entries = range_table->num_entries;
  883. eg_pi->mc_reg_table.valid_flag = 0;
  884. for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
  885. for (j = 1; j < range_table->num_entries; j++) {
  886. if (eg_pi->mc_reg_table.mc_reg_table_entry[j-1].mc_data[i] !=
  887. eg_pi->mc_reg_table.mc_reg_table_entry[j].mc_data[i]) {
  888. eg_pi->mc_reg_table.valid_flag |= (1 << i);
  889. break;
  890. }
  891. }
  892. }
  893. }
  894. static int cypress_initialize_mc_reg_table(struct radeon_device *rdev)
  895. {
  896. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  897. u8 module_index = rv770_get_memory_module_index(rdev);
  898. struct atom_memory_clock_range_table range_table = { 0 };
  899. int ret;
  900. ret = radeon_atom_get_mclk_range_table(rdev,
  901. pi->mem_gddr5,
  902. module_index, &range_table);
  903. if (ret)
  904. return ret;
  905. cypress_retrieve_ac_timing_for_all_ranges(rdev, &range_table);
  906. return 0;
  907. }
  908. static void cypress_wait_for_mc_sequencer(struct radeon_device *rdev, u8 value)
  909. {
  910. u32 i, j;
  911. u32 channels = 2;
  912. if ((rdev->family == CHIP_CYPRESS) ||
  913. (rdev->family == CHIP_HEMLOCK))
  914. channels = 4;
  915. else if (rdev->family == CHIP_CEDAR)
  916. channels = 1;
  917. for (i = 0; i < channels; i++) {
  918. if ((rdev->family == CHIP_CYPRESS) ||
  919. (rdev->family == CHIP_HEMLOCK)) {
  920. WREG32_P(MC_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
  921. WREG32_P(MC_CG_CONFIG_MCD, MC_RD_ENABLE_MCD(i), ~MC_RD_ENABLE_MCD_MASK);
  922. } else {
  923. WREG32_P(MC_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
  924. WREG32_P(MC_CG_CONFIG, MC_RD_ENABLE(i), ~MC_RD_ENABLE_MASK);
  925. }
  926. for (j = 0; j < rdev->usec_timeout; j++) {
  927. if (((RREG32(MC_SEQ_CG) & CG_SEQ_RESP_MASK) >> CG_SEQ_RESP_SHIFT) == value)
  928. break;
  929. udelay(1);
  930. }
  931. }
  932. }
  933. static void cypress_force_mc_use_s1(struct radeon_device *rdev,
  934. struct radeon_ps *radeon_boot_state)
  935. {
  936. struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
  937. u32 strobe_mode;
  938. u32 mc_seq_cg;
  939. int i;
  940. if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
  941. return;
  942. radeon_atom_set_ac_timing(rdev, boot_state->low.mclk);
  943. radeon_mc_wait_for_idle(rdev);
  944. if ((rdev->family == CHIP_CYPRESS) ||
  945. (rdev->family == CHIP_HEMLOCK)) {
  946. WREG32(MC_CONFIG_MCD, 0xf);
  947. WREG32(MC_CG_CONFIG_MCD, 0xf);
  948. } else {
  949. WREG32(MC_CONFIG, 0xf);
  950. WREG32(MC_CG_CONFIG, 0xf);
  951. }
  952. for (i = 0; i < rdev->num_crtc; i++)
  953. radeon_wait_for_vblank(rdev, i);
  954. WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
  955. cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
  956. strobe_mode = cypress_get_strobe_mode_settings(rdev,
  957. boot_state->low.mclk);
  958. mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S1);
  959. mc_seq_cg |= SEQ_CG_RESP(strobe_mode);
  960. WREG32(MC_SEQ_CG, mc_seq_cg);
  961. for (i = 0; i < rdev->usec_timeout; i++) {
  962. if (RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE)
  963. break;
  964. udelay(1);
  965. }
  966. mc_seq_cg &= ~CG_SEQ_REQ_MASK;
  967. mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
  968. WREG32(MC_SEQ_CG, mc_seq_cg);
  969. cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
  970. }
  971. static void cypress_copy_ac_timing_from_s1_to_s0(struct radeon_device *rdev)
  972. {
  973. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  974. u32 value;
  975. u32 i;
  976. for (i = 0; i < eg_pi->mc_reg_table.last; i++) {
  977. value = RREG32(eg_pi->mc_reg_table.mc_reg_address[i].s1 << 2);
  978. WREG32(eg_pi->mc_reg_table.mc_reg_address[i].s0 << 2, value);
  979. }
  980. }
  981. static void cypress_force_mc_use_s0(struct radeon_device *rdev,
  982. struct radeon_ps *radeon_boot_state)
  983. {
  984. struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
  985. u32 strobe_mode;
  986. u32 mc_seq_cg;
  987. int i;
  988. cypress_copy_ac_timing_from_s1_to_s0(rdev);
  989. radeon_mc_wait_for_idle(rdev);
  990. if ((rdev->family == CHIP_CYPRESS) ||
  991. (rdev->family == CHIP_HEMLOCK)) {
  992. WREG32(MC_CONFIG_MCD, 0xf);
  993. WREG32(MC_CG_CONFIG_MCD, 0xf);
  994. } else {
  995. WREG32(MC_CONFIG, 0xf);
  996. WREG32(MC_CG_CONFIG, 0xf);
  997. }
  998. for (i = 0; i < rdev->num_crtc; i++)
  999. radeon_wait_for_vblank(rdev, i);
  1000. WREG32(MC_SEQ_CG, MC_CG_SEQ_YCLK_SUSPEND);
  1001. cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_SUSPEND);
  1002. strobe_mode = cypress_get_strobe_mode_settings(rdev,
  1003. boot_state->low.mclk);
  1004. mc_seq_cg = CG_SEQ_REQ(MC_CG_SEQ_DRAMCONF_S0);
  1005. mc_seq_cg |= SEQ_CG_RESP(strobe_mode);
  1006. WREG32(MC_SEQ_CG, mc_seq_cg);
  1007. for (i = 0; i < rdev->usec_timeout; i++) {
  1008. if (!(RREG32(MC_SEQ_STATUS_M) & PMG_PWRSTATE))
  1009. break;
  1010. udelay(1);
  1011. }
  1012. mc_seq_cg &= ~CG_SEQ_REQ_MASK;
  1013. mc_seq_cg |= CG_SEQ_REQ(MC_CG_SEQ_YCLK_RESUME);
  1014. WREG32(MC_SEQ_CG, mc_seq_cg);
  1015. cypress_wait_for_mc_sequencer(rdev, MC_CG_SEQ_YCLK_RESUME);
  1016. }
  1017. static int cypress_populate_initial_mvdd_value(struct radeon_device *rdev,
  1018. RV770_SMC_VOLTAGE_VALUE *voltage)
  1019. {
  1020. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  1021. voltage->index = eg_pi->mvdd_high_index;
  1022. voltage->value = cpu_to_be16(MVDD_HIGH_VALUE);
  1023. return 0;
  1024. }
  1025. int cypress_populate_smc_initial_state(struct radeon_device *rdev,
  1026. struct radeon_ps *radeon_initial_state,
  1027. RV770_SMC_STATETABLE *table)
  1028. {
  1029. struct rv7xx_ps *initial_state = rv770_get_ps(radeon_initial_state);
  1030. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  1031. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  1032. u32 a_t;
  1033. table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
  1034. cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl);
  1035. table->initialState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
  1036. cpu_to_be32(pi->clk_regs.rv770.mpll_ad_func_cntl_2);
  1037. table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
  1038. cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl);
  1039. table->initialState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
  1040. cpu_to_be32(pi->clk_regs.rv770.mpll_dq_func_cntl_2);
  1041. table->initialState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
  1042. cpu_to_be32(pi->clk_regs.rv770.mclk_pwrmgt_cntl);
  1043. table->initialState.levels[0].mclk.mclk770.vDLL_CNTL =
  1044. cpu_to_be32(pi->clk_regs.rv770.dll_cntl);
  1045. table->initialState.levels[0].mclk.mclk770.vMPLL_SS =
  1046. cpu_to_be32(pi->clk_regs.rv770.mpll_ss1);
  1047. table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
  1048. cpu_to_be32(pi->clk_regs.rv770.mpll_ss2);
  1049. table->initialState.levels[0].mclk.mclk770.mclk_value =
  1050. cpu_to_be32(initial_state->low.mclk);
  1051. table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
  1052. cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl);
  1053. table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
  1054. cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_2);
  1055. table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
  1056. cpu_to_be32(pi->clk_regs.rv770.cg_spll_func_cntl_3);
  1057. table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
  1058. cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum);
  1059. table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
  1060. cpu_to_be32(pi->clk_regs.rv770.cg_spll_spread_spectrum_2);
  1061. table->initialState.levels[0].sclk.sclk_value =
  1062. cpu_to_be32(initial_state->low.sclk);
  1063. table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0;
  1064. table->initialState.levels[0].ACIndex = 0;
  1065. cypress_populate_voltage_value(rdev,
  1066. &eg_pi->vddc_voltage_table,
  1067. initial_state->low.vddc,
  1068. &table->initialState.levels[0].vddc);
  1069. if (eg_pi->vddci_control)
  1070. cypress_populate_voltage_value(rdev,
  1071. &eg_pi->vddci_voltage_table,
  1072. initial_state->low.vddci,
  1073. &table->initialState.levels[0].vddci);
  1074. cypress_populate_initial_mvdd_value(rdev,
  1075. &table->initialState.levels[0].mvdd);
  1076. a_t = CG_R(0xffff) | CG_L(0);
  1077. table->initialState.levels[0].aT = cpu_to_be32(a_t);
  1078. table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
  1079. if (pi->boot_in_gen2)
  1080. table->initialState.levels[0].gen2PCIE = 1;
  1081. else
  1082. table->initialState.levels[0].gen2PCIE = 0;
  1083. if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2)
  1084. table->initialState.levels[0].gen2XSP = 1;
  1085. else
  1086. table->initialState.levels[0].gen2XSP = 0;
  1087. if (pi->mem_gddr5) {
  1088. table->initialState.levels[0].strobeMode =
  1089. cypress_get_strobe_mode_settings(rdev,
  1090. initial_state->low.mclk);
  1091. if (initial_state->low.mclk > pi->mclk_edc_enable_threshold)
  1092. table->initialState.levels[0].mcFlags = SMC_MC_EDC_RD_FLAG | SMC_MC_EDC_WR_FLAG;
  1093. else
  1094. table->initialState.levels[0].mcFlags = 0;
  1095. }
  1096. table->initialState.levels[1] = table->initialState.levels[0];
  1097. table->initialState.levels[2] = table->initialState.levels[0];
  1098. table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
  1099. return 0;
  1100. }
  1101. int cypress_populate_smc_acpi_state(struct radeon_device *rdev,
  1102. RV770_SMC_STATETABLE *table)
  1103. {
  1104. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  1105. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  1106. u32 mpll_ad_func_cntl =
  1107. pi->clk_regs.rv770.mpll_ad_func_cntl;
  1108. u32 mpll_ad_func_cntl_2 =
  1109. pi->clk_regs.rv770.mpll_ad_func_cntl_2;
  1110. u32 mpll_dq_func_cntl =
  1111. pi->clk_regs.rv770.mpll_dq_func_cntl;
  1112. u32 mpll_dq_func_cntl_2 =
  1113. pi->clk_regs.rv770.mpll_dq_func_cntl_2;
  1114. u32 spll_func_cntl =
  1115. pi->clk_regs.rv770.cg_spll_func_cntl;
  1116. u32 spll_func_cntl_2 =
  1117. pi->clk_regs.rv770.cg_spll_func_cntl_2;
  1118. u32 spll_func_cntl_3 =
  1119. pi->clk_regs.rv770.cg_spll_func_cntl_3;
  1120. u32 mclk_pwrmgt_cntl =
  1121. pi->clk_regs.rv770.mclk_pwrmgt_cntl;
  1122. u32 dll_cntl =
  1123. pi->clk_regs.rv770.dll_cntl;
  1124. table->ACPIState = table->initialState;
  1125. table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
  1126. if (pi->acpi_vddc) {
  1127. cypress_populate_voltage_value(rdev,
  1128. &eg_pi->vddc_voltage_table,
  1129. pi->acpi_vddc,
  1130. &table->ACPIState.levels[0].vddc);
  1131. if (pi->pcie_gen2) {
  1132. if (pi->acpi_pcie_gen2)
  1133. table->ACPIState.levels[0].gen2PCIE = 1;
  1134. else
  1135. table->ACPIState.levels[0].gen2PCIE = 0;
  1136. } else
  1137. table->ACPIState.levels[0].gen2PCIE = 0;
  1138. if (pi->acpi_pcie_gen2)
  1139. table->ACPIState.levels[0].gen2XSP = 1;
  1140. else
  1141. table->ACPIState.levels[0].gen2XSP = 0;
  1142. } else {
  1143. cypress_populate_voltage_value(rdev,
  1144. &eg_pi->vddc_voltage_table,
  1145. pi->min_vddc_in_table,
  1146. &table->ACPIState.levels[0].vddc);
  1147. table->ACPIState.levels[0].gen2PCIE = 0;
  1148. }
  1149. if (eg_pi->acpi_vddci) {
  1150. if (eg_pi->vddci_control) {
  1151. cypress_populate_voltage_value(rdev,
  1152. &eg_pi->vddci_voltage_table,
  1153. eg_pi->acpi_vddci,
  1154. &table->ACPIState.levels[0].vddci);
  1155. }
  1156. }
  1157. mpll_ad_func_cntl &= ~PDNB;
  1158. mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN;
  1159. if (pi->mem_gddr5)
  1160. mpll_dq_func_cntl &= ~PDNB;
  1161. mpll_dq_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN | BYPASS;
  1162. mclk_pwrmgt_cntl |= (MRDCKA0_RESET |
  1163. MRDCKA1_RESET |
  1164. MRDCKB0_RESET |
  1165. MRDCKB1_RESET |
  1166. MRDCKC0_RESET |
  1167. MRDCKC1_RESET |
  1168. MRDCKD0_RESET |
  1169. MRDCKD1_RESET);
  1170. mclk_pwrmgt_cntl &= ~(MRDCKA0_PDNB |
  1171. MRDCKA1_PDNB |
  1172. MRDCKB0_PDNB |
  1173. MRDCKB1_PDNB |
  1174. MRDCKC0_PDNB |
  1175. MRDCKC1_PDNB |
  1176. MRDCKD0_PDNB |
  1177. MRDCKD1_PDNB);
  1178. dll_cntl |= (MRDCKA0_BYPASS |
  1179. MRDCKA1_BYPASS |
  1180. MRDCKB0_BYPASS |
  1181. MRDCKB1_BYPASS |
  1182. MRDCKC0_BYPASS |
  1183. MRDCKC1_BYPASS |
  1184. MRDCKD0_BYPASS |
  1185. MRDCKD1_BYPASS);
  1186. /* evergreen only */
  1187. if (rdev->family <= CHIP_HEMLOCK)
  1188. spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN;
  1189. spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
  1190. spll_func_cntl_2 |= SCLK_MUX_SEL(4);
  1191. table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL =
  1192. cpu_to_be32(mpll_ad_func_cntl);
  1193. table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 =
  1194. cpu_to_be32(mpll_ad_func_cntl_2);
  1195. table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL =
  1196. cpu_to_be32(mpll_dq_func_cntl);
  1197. table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 =
  1198. cpu_to_be32(mpll_dq_func_cntl_2);
  1199. table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL =
  1200. cpu_to_be32(mclk_pwrmgt_cntl);
  1201. table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl);
  1202. table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0;
  1203. table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
  1204. cpu_to_be32(spll_func_cntl);
  1205. table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
  1206. cpu_to_be32(spll_func_cntl_2);
  1207. table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
  1208. cpu_to_be32(spll_func_cntl_3);
  1209. table->ACPIState.levels[0].sclk.sclk_value = 0;
  1210. cypress_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
  1211. if (eg_pi->dynamic_ac_timing)
  1212. table->ACPIState.levels[0].ACIndex = 1;
  1213. table->ACPIState.levels[1] = table->ACPIState.levels[0];
  1214. table->ACPIState.levels[2] = table->ACPIState.levels[0];
  1215. return 0;
  1216. }
  1217. static void cypress_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
  1218. struct atom_voltage_table *voltage_table)
  1219. {
  1220. unsigned int i, diff;
  1221. if (voltage_table->count <= MAX_NO_VREG_STEPS)
  1222. return;
  1223. diff = voltage_table->count - MAX_NO_VREG_STEPS;
  1224. for (i= 0; i < MAX_NO_VREG_STEPS; i++)
  1225. voltage_table->entries[i] = voltage_table->entries[i + diff];
  1226. voltage_table->count = MAX_NO_VREG_STEPS;
  1227. }
  1228. int cypress_construct_voltage_tables(struct radeon_device *rdev)
  1229. {
  1230. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  1231. int ret;
  1232. ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 0,
  1233. &eg_pi->vddc_voltage_table);
  1234. if (ret)
  1235. return ret;
  1236. if (eg_pi->vddc_voltage_table.count > MAX_NO_VREG_STEPS)
  1237. cypress_trim_voltage_table_to_fit_state_table(rdev,
  1238. &eg_pi->vddc_voltage_table);
  1239. if (eg_pi->vddci_control) {
  1240. ret = radeon_atom_get_voltage_table(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 0,
  1241. &eg_pi->vddci_voltage_table);
  1242. if (ret)
  1243. return ret;
  1244. if (eg_pi->vddci_voltage_table.count > MAX_NO_VREG_STEPS)
  1245. cypress_trim_voltage_table_to_fit_state_table(rdev,
  1246. &eg_pi->vddci_voltage_table);
  1247. }
  1248. return 0;
  1249. }
  1250. static void cypress_populate_smc_voltage_table(struct radeon_device *rdev,
  1251. struct atom_voltage_table *voltage_table,
  1252. RV770_SMC_STATETABLE *table)
  1253. {
  1254. unsigned int i;
  1255. for (i = 0; i < voltage_table->count; i++) {
  1256. table->highSMIO[i] = 0;
  1257. table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
  1258. }
  1259. }
  1260. int cypress_populate_smc_voltage_tables(struct radeon_device *rdev,
  1261. RV770_SMC_STATETABLE *table)
  1262. {
  1263. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  1264. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  1265. unsigned char i;
  1266. if (eg_pi->vddc_voltage_table.count) {
  1267. cypress_populate_smc_voltage_table(rdev,
  1268. &eg_pi->vddc_voltage_table,
  1269. table);
  1270. table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDC] = 0;
  1271. table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDC] =
  1272. cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
  1273. for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
  1274. if (pi->max_vddc_in_table <=
  1275. eg_pi->vddc_voltage_table.entries[i].value) {
  1276. table->maxVDDCIndexInPPTable = i;
  1277. break;
  1278. }
  1279. }
  1280. }
  1281. if (eg_pi->vddci_voltage_table.count) {
  1282. cypress_populate_smc_voltage_table(rdev,
  1283. &eg_pi->vddci_voltage_table,
  1284. table);
  1285. table->voltageMaskTable.highMask[RV770_SMC_VOLTAGEMASK_VDDCI] = 0;
  1286. table->voltageMaskTable.lowMask[RV770_SMC_VOLTAGEMASK_VDDCI] =
  1287. cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
  1288. }
  1289. return 0;
  1290. }
  1291. static u32 cypress_get_mclk_split_point(struct atom_memory_info *memory_info)
  1292. {
  1293. if ((memory_info->mem_type == MEM_TYPE_GDDR3) ||
  1294. (memory_info->mem_type == MEM_TYPE_DDR3))
  1295. return 30000;
  1296. return 0;
  1297. }
  1298. int cypress_get_mvdd_configuration(struct radeon_device *rdev)
  1299. {
  1300. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  1301. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  1302. u8 module_index;
  1303. struct atom_memory_info memory_info;
  1304. u32 tmp = RREG32(GENERAL_PWRMGT);
  1305. if (!(tmp & BACKBIAS_PAD_EN)) {
  1306. eg_pi->mvdd_high_index = 0;
  1307. eg_pi->mvdd_low_index = 1;
  1308. pi->mvdd_control = false;
  1309. return 0;
  1310. }
  1311. if (tmp & BACKBIAS_VALUE)
  1312. eg_pi->mvdd_high_index = 1;
  1313. else
  1314. eg_pi->mvdd_high_index = 0;
  1315. eg_pi->mvdd_low_index =
  1316. (eg_pi->mvdd_high_index == 0) ? 1 : 0;
  1317. module_index = rv770_get_memory_module_index(rdev);
  1318. if (radeon_atom_get_memory_info(rdev, module_index, &memory_info)) {
  1319. pi->mvdd_control = false;
  1320. return 0;
  1321. }
  1322. pi->mvdd_split_frequency =
  1323. cypress_get_mclk_split_point(&memory_info);
  1324. if (pi->mvdd_split_frequency == 0) {
  1325. pi->mvdd_control = false;
  1326. return 0;
  1327. }
  1328. return 0;
  1329. }
  1330. static int cypress_init_smc_table(struct radeon_device *rdev,
  1331. struct radeon_ps *radeon_boot_state)
  1332. {
  1333. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  1334. RV770_SMC_STATETABLE *table = &pi->smc_statetable;
  1335. int ret;
  1336. memset(table, 0, sizeof(RV770_SMC_STATETABLE));
  1337. cypress_populate_smc_voltage_tables(rdev, table);
  1338. switch (rdev->pm.int_thermal_type) {
  1339. case THERMAL_TYPE_EVERGREEN:
  1340. case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
  1341. table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
  1342. break;
  1343. case THERMAL_TYPE_NONE:
  1344. table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
  1345. break;
  1346. default:
  1347. table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
  1348. break;
  1349. }
  1350. if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
  1351. table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
  1352. if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT)
  1353. table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
  1354. if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
  1355. table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
  1356. if (pi->mem_gddr5)
  1357. table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
  1358. ret = cypress_populate_smc_initial_state(rdev, radeon_boot_state, table);
  1359. if (ret)
  1360. return ret;
  1361. ret = cypress_populate_smc_acpi_state(rdev, table);
  1362. if (ret)
  1363. return ret;
  1364. table->driverState = table->initialState;
  1365. return rv770_copy_bytes_to_smc(rdev,
  1366. pi->state_table_start,
  1367. (u8 *)table, sizeof(RV770_SMC_STATETABLE),
  1368. pi->sram_end);
  1369. }
  1370. int cypress_populate_mc_reg_table(struct radeon_device *rdev,
  1371. struct radeon_ps *radeon_boot_state)
  1372. {
  1373. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  1374. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  1375. struct rv7xx_ps *boot_state = rv770_get_ps(radeon_boot_state);
  1376. SMC_Evergreen_MCRegisters mc_reg_table = { 0 };
  1377. rv770_write_smc_soft_register(rdev,
  1378. RV770_SMC_SOFT_REGISTER_seq_index, 1);
  1379. cypress_populate_mc_reg_addresses(rdev, &mc_reg_table);
  1380. cypress_convert_mc_reg_table_entry_to_smc(rdev,
  1381. &boot_state->low,
  1382. &mc_reg_table.data[0]);
  1383. cypress_convert_mc_registers(&eg_pi->mc_reg_table.mc_reg_table_entry[0],
  1384. &mc_reg_table.data[1], eg_pi->mc_reg_table.last,
  1385. eg_pi->mc_reg_table.valid_flag);
  1386. cypress_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, &mc_reg_table);
  1387. return rv770_copy_bytes_to_smc(rdev, eg_pi->mc_reg_table_start,
  1388. (u8 *)&mc_reg_table, sizeof(SMC_Evergreen_MCRegisters),
  1389. pi->sram_end);
  1390. }
  1391. int cypress_get_table_locations(struct radeon_device *rdev)
  1392. {
  1393. struct rv7xx_power_info *pi = rv770_get_pi(rdev);
  1394. struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
  1395. u32 tmp;
  1396. int ret;
  1397. ret = rv770_read_smc_sram_dword(rdev,
  1398. EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
  1399. EVERGREEN_SMC_FIRMWARE_HEADER_stateTable,
  1400. &tmp, pi->sram_end);
  1401. if (ret)
  1402. return ret;
  1403. pi->state_table_start = (u16)tmp;
  1404. ret = rv770_read_smc_sram_dword(rdev,
  1405. EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
  1406. EVERGREEN_SMC_FIRMWARE_HEADER_softRegisters,
  1407. &tmp, pi->sram_end);
  1408. if (ret)
  1409. return ret;
  1410. pi->soft_regs_start = (u16)tmp;
  1411. ret = rv770_read_smc_sram_dword(rdev,
  1412. EVERGREEN_SMC_FIRMWARE_HEADER_LOCATION +
  1413. EVERGREEN_SMC_FIRMWARE_HEADER_mcRegisterTable,
  1414. &tmp, pi->sram_end);
  1415. if (ret)
  1416. retu

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