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/include/libopencm3/stm32/f3/memorymap.h

https://gitlab.com/madresistor/libopencm3
C Header | 129 lines | 69 code | 18 blank | 42 comment | 0 complexity | 3e98dc8f5b29ff16d0844d2d769520f7 MD5 | raw file
    

  1. /*
    2. 

  2.  * This file is part of the libopencm3 project.
    3. 

  3.  *
    4. 

  4.  * Copyright (C) 2011 Fergus Noble <fergusnoble@gmail.com>
    5. 

  5.  * Modified by 2013 Fernando Cortes <fernando.corcam@gmail.com> (stm32f3)
    6. 

  6.  * Modified by 2013 Guillermo Rivera <memogrg@gmail.com> (stm32f3)
    7. 

  7.  *
    8. 

  8.  * This library is free software: you can redistribute it and/or modify
    9. 

  9.  * it under the terms of the GNU Lesser General Public License as published by
    10. 

  10.  * the Free Software Foundation, either version 3 of the License, or
    11. 

  11.  * (at your option) any later version.
    12. 

  12.  *
    13. 

  13.  * This library is distributed in the hope that it will be useful,
    14. 

  14.  * but WITHOUT ANY WARRANTY; without even the implied warranty of
    15. 

  15.  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    16. 

  16.  * GNU Lesser General Public License for more details.
    17. 

  17.  *
    18. 

  18.  * You should have received a copy of the GNU Lesser General Public License
    19. 

  19.  * along with this library.  If not, see <http://www.gnu.org/licenses/>.
    20. 

  20.  */
    21. 

  21. 

  22. #ifndef LIBOPENCM3_MEMORYMAP_H
    23. 

  23. #define LIBOPENCM3_MEMORYMAP_H
    24. 

  24. 

  25. #include <libopencm3/cm3/memorymap.h>
    26. 

  26. 

  27. /* --- STM32F3 specific peripheral definitions ----------------------------- */
    28. 

  28. 

  29. /* Memory map for all busses */
    30. 

  30. #define PERIPH_BASE			(0x40000000U)
    31. 

  31. #define PERIPH_BASE_APB1		(PERIPH_BASE + 0x00000)
    32. 

  32. #define PERIPH_BASE_APB2		(PERIPH_BASE + 0x10000)
    33. 

  33. #define PERIPH_BASE_AHB1		(PERIPH_BASE + 0x20000)
    34. 

  34. #define PERIPH_BASE_AHB2		(0x48000000U)
    35. 

  35. #define PERIPH_BASE_AHB3		(0x50000000U)
    36. 

  36. 

  37. /* Register boundary addresses */
    38. 

  38. 

  39. /* APB1 */
    40. 

  40. #define TIM2_BASE			(PERIPH_BASE_APB1 + 0x0000)
    41. 

  41. #define TIM3_BASE			(PERIPH_BASE_APB1 + 0x0400)
    42. 

  42. #define TIM4_BASE			(PERIPH_BASE_APB1 + 0x0800)
    43. 

  43. /* PERIPH_BASE_APB1 + 0x0C00 (0x4000 0C00 - 0x4000 0FFF): Reserved */
    44. 

  44. #define TIM6_BASE			(PERIPH_BASE_APB1 + 0x1000)
    45. 

  45. #define TIM7_BASE			(PERIPH_BASE_APB1 + 0x1400)
    46. 

  46. /* PERIPH_BASE_APB1 + 0x1800 (0x4000 1800 - 0x4000 27FF): Reserved */
    47. 

  47. #define RTC_BASE			(PERIPH_BASE_APB1 + 0x2800)
    48. 

  48. #define WWDG_BASE			(PERIPH_BASE_APB1 + 0x2c00)
    49. 

  49. #define IWDG_BASE			(PERIPH_BASE_APB1 + 0x3000)
    50. 

  50. #define I2S2_EXT_BASE			(PERIPH_BASE_APB1 + 0x3400)
    51. 

  51. #define SPI2_BASE			(PERIPH_BASE_APB1 + 0x3800)
    52. 

  52. #define SPI3_BASE			(PERIPH_BASE_APB1 + 0x3c00)
    53. 

  53. #define I2S3_EXT_BASE			(PERIPH_BASE_APB1 + 0x4000)
    54. 

  54. #define USART2_BASE			(PERIPH_BASE_APB1 + 0x4400)
    55. 

  55. #define USART3_BASE			(PERIPH_BASE_APB1 + 0x4800)
    56. 

  56. #define UART4_BASE			(PERIPH_BASE_APB1 + 0x4c00)
    57. 

  57. #define UART5_BASE			(PERIPH_BASE_APB1 + 0x5000)
    58. 

  58. #define I2C1_BASE			(PERIPH_BASE_APB1 + 0x5400)
    59. 

  59. #define I2C2_BASE			(PERIPH_BASE_APB1 + 0x5800)
    60. 

  60. #define USB_DEV_FS_BASE			(PERIPH_BASE_APB1 + 0x5C00)
    61. 

  61. #define USB_PMA_BASE			(PERIPH_BASE_APB1 + 0x6000)
    62. 

  62. #define BX_CAN_BASE			(PERIPH_BASE_APB1 + 0x6400)
    63. 

  63. /* PERIPH_BASE_APB1 + 0x6800 (0x4000 6800 - 0x4000 6BFF): Reserved */
    64. 

  64. /* PERIPH_BASE_APB1 + 0x6C00 (0x4000 6C00 - 0x4000 6FFF): Reserved */
    65. 

  65. #define POWER_CONTROL_BASE		(PERIPH_BASE_APB1 + 0x7000)
    66. 

  66. #define DAC_BASE			(PERIPH_BASE_APB1 + 0x7400)
    67. 

  67. /* PERIPH_BASE_APB1 + 0x7800 (0x4000 7800 - 0x4000 7FFF): Reserved */
    68. 

  68. 

  69. 

  70. /* APB2 */
    71. 

  71. #define TIM17_BASE			(PERIPH_BASE_APB2 + 0x4800)
    72. 

  72. #define TIM16_BASE			(PERIPH_BASE_APB2 + 0x4400)
    73. 

  73. #define TIM15_BASE			(PERIPH_BASE_APB2 + 0x4000)
    74. 

  74. /* PERIPH_BASE_APB2 + 0x3C00 (0x4001 3C00 - 0x4001 3FFF): Reserved */
    75. 

  75. #define USART1_BASE			(PERIPH_BASE_APB2 + 0x3800)
    76. 

  76. #define TIM8_BASE			(PERIPH_BASE_APB2 + 0x3400)
    77. 

  77. #define SPI1_BASE			(PERIPH_BASE_APB2 + 0x3000)
    78. 

  78. #define TIM1_BASE			(PERIPH_BASE_APB2 + 0x2C00)
    79. 

  79. /* PERIPH_BASE_APB2 + 0x0800 (0x4001 0800 - 0x4001 2BFF): Reserved */
    80. 

  80. #define EXTI_BASE			(PERIPH_BASE_APB2 + 0x0400)
    81. 

  81. #define SYSCFG_BASE			(PERIPH_BASE_APB2 + 0x0000)
    82. 

  82. #define COMP_BASE			(PERIPH_BASE_APB2 + 0x0000)
    83. 

  83. #define OPAMP_BASE			(PERIPH_BASE_APB2 + 0x0000)
    84. 

  84. 

  85. 

  86. /* AHB2 */
    87. 

  87. #define GPIO_PORT_A_BASE		(PERIPH_BASE_AHB2 + 0x0000)
    88. 

  88. #define GPIO_PORT_B_BASE		(PERIPH_BASE_AHB2 + 0x0400)
    89. 

  89. #define GPIO_PORT_C_BASE		(PERIPH_BASE_AHB2 + 0x0800)
    90. 

  90. #define GPIO_PORT_D_BASE		(PERIPH_BASE_AHB2 + 0x0C00)
    91. 

  91. #define GPIO_PORT_E_BASE		(PERIPH_BASE_AHB2 + 0x1000)
    92. 

  92. #define GPIO_PORT_F_BASE		(PERIPH_BASE_AHB2 + 0x1400)
    93. 

  93. 

  94. 

  95. /* AHB1 */
    96. 

  96. #define TSC_BASE			(PERIPH_BASE_AHB1 + 0x4000)
    97. 

  97. /* PERIPH_BASE_AHB1 + 0x3400 (0x4002 3400 - 0x4002 37FF): Reserved */
    98. 

  98. #define CRC_BASE			(PERIPH_BASE_AHB1 + 0x3000)
    99. 

  99. /* PERIPH_BASE_AHB1 + 0x2400 (0x4002 2400 - 0x4002 2FFF): Reserved */
    100. 

  100. #define FLASH_MEM_INTERFACE_BASE	(PERIPH_BASE_AHB1 + 0x2000)
    101. 

  101. /* PERIPH_BASE_AHB1 + 0x1400 (0x4002 1400 - 0x4002 1FFF): Reserved */
    102. 

  102. #define RCC_BASE			(PERIPH_BASE_AHB1 + 0x1000)
    103. 

  103. /* PERIPH_BASE_AHB1 + 0x0800 (0x4002 0800 - 0x4002 0FFF): Reserved */
    104. 

  104. #define DMA1_BASE			(PERIPH_BASE_AHB1 + 0x0000)
    105. 

  105. #define DMA2_BASE			(PERIPH_BASE_AHB1 + 0x0400)
    106. 

  106. 

  107. 

  108. /* AHB3 */
    109. 

  109. #define ADC3_BASE			(PERIPH_BASE_AHB3 + 0x0400)
    110. 

  110. #define ADC4_BASE			(PERIPH_BASE_AHB3 + 0x0500)
    111. 

  111. #define ADC1_BASE			(PERIPH_BASE_AHB3 + 0x0000)
    112. 

  112. #define ADC2_BASE			(PERIPH_BASE_AHB3 + 0x0100)
    113. 

  113. 

  114. /* PPIB */
    115. 

  115. #define DBGMCU_BASE			(PPBI_BASE + 0x00042000)
    116. 

  116. 

  117. /* Device Electronic Signature */
    118. 

  118. #define DESIG_FLASH_SIZE_BASE		(0x1FFFF7CCU)
    119. 

  119. #define DESIG_UNIQUE_ID_BASE		(0x1FFFF7ACU)
    120. 

  120. #define DESIG_UNIQUE_ID0		MMIO32(DESIG_UNIQUE_ID_BASE)
    121. 

  121. #define DESIG_UNIQUE_ID1		MMIO32(DESIG_UNIQUE_ID_BASE + 4)
    122. 

  122. #define DESIG_UNIQUE_ID2		MMIO32(DESIG_UNIQUE_ID_BASE + 8)
    123. 

  123. 

  124. /* ST provided factory calibration values @ 3.3V */
    125. 

  125. #define ST_VREFINT_CAL		MMIO16(0x1FFFF7BA)
    126. 

  126. #define ST_TSENSE_CAL1_30C	MMIO16(0x1FFFF7B8)
    127. 

  127. #define ST_TSENSE_CAL2_110	MMIO16(0x1FFFF7C2)
    128. 

  128. 

  129. #endif
    130. 

  130.