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/arch/blackfin/mach-bf548/include/mach/anomaly.h

https://gitlab.com/Sean.W/pru-linux-drivers
C Header | 267 lines | 149 code | 6 blank | 112 comment | 2 complexity | e503562dc883a00af9a0d699963b3d5b MD5 | raw file
    

  1. /*
    2. 

  2.  * DO NOT EDIT THIS FILE
    3. 

  3.  * This file is under version control at
    4. 

  4.  *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
    5. 

  5.  * and can be replaced with that version at any time
    6. 

  6.  * DO NOT EDIT THIS FILE
    7. 

  7.  *
    8. 

  8.  * Copyright 2004-2009 Analog Devices Inc.
    9. 

  9.  * Licensed under the ADI BSD license.
    10. 

  10.  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
    11. 

  11.  */
    12. 

  12. 

  13. /* This file should be up to date with:
    14. 

  14.  *  - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
    15. 

  15.  */
    16. 

  16. 

  17. #ifndef _MACH_ANOMALY_H_
    18. 

  18. #define _MACH_ANOMALY_H_
    19. 

  19. 

  20. /* We do not support 0.0 or 0.1 silicon - sorry */
    21. 

  21. #if __SILICON_REVISION__ < 2
    22. 

  22. # error will not work on BF548 silicon version 0.0, or 0.1
    23. 

  23. #endif
    24. 

  24. 

  25. /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
    26. 

  26. #define ANOMALY_05000074 (1)
    27. 

  27. /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
    28. 

  28. #define ANOMALY_05000119 (1)
    29. 

  29. /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
    30. 

  30. #define ANOMALY_05000122 (1)
    31. 

  31. /* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
    32. 

  32. #define ANOMALY_05000220 (1)
    33. 

  33. /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
    34. 

  34. #define ANOMALY_05000245 (1)
    35. 

  35. /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
    36. 

  36. #define ANOMALY_05000265 (1)
    37. 

  37. /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
    38. 

  38. #define ANOMALY_05000272 (1)
    39. 

  39. /* False Hardware Error Exception when ISR Context Is Not Restored */
    40. 

  40. #define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
    41. 

  41. /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
    42. 

  42. #define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
    43. 

  43. /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
    44. 

  44. #define ANOMALY_05000310 (1)
    45. 

  45. /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
    46. 

  46. #define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
    47. 

  47. /* TWI Slave Boot Mode Is Not Functional */
    48. 

  48. #define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
    49. 

  49. /* FIFO Boot Mode Not Functional */
    50. 

  50. #define ANOMALY_05000325 (__SILICON_REVISION__ < 2)
    51. 

  51. /* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
    52. 

  52. #define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
    53. 

  53. /* Incorrect Access of OTP_STATUS During otp_write() Function */
    54. 

  54. #define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
    55. 

  55. /* Synchronous Burst Flash Boot Mode Is Not Functional */
    56. 

  56. #define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
    57. 

  57. /* Host DMA Boot Modes Are Not Functional */
    58. 

  58. #define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
    59. 

  59. /* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
    60. 

  60. #define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
    61. 

  61. /* Inadequate Rotary Debounce Logic Duration */
    62. 

  62. #define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
    63. 

  63. /* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
    64. 

  64. #define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
    65. 

  65. /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
    66. 

  66. #define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
    67. 

  67. /* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
    68. 

  68. #define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
    69. 

  69. /* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
    70. 

  70. #define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
    71. 

  71. /* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
    72. 

  72. #define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
    73. 

  73. /* USB Calibration Value Is Not Initialized */
    74. 

  74. #define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
    75. 

  75. /* USB Calibration Value to use */
    76. 

  76. #define ANOMALY_05000346_value 0x5411
    77. 

  77. /* Preboot Routine Incorrectly Alters Reset Value of USB Register */
    78. 

  78. #define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
    79. 

  79. /* Data Lost when Core Reads SDH Data FIFO */
    80. 

  80. #define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
    81. 

  81. /* PLL Status Register Is Inaccurate */
    82. 

  82. #define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
    83. 

  83. /* bfrom_SysControl() Firmware Function Performs Improper System Reset */
    84. 

  84. #define ANOMALY_05000353 (__SILICON_REVISION__ < 2)
    85. 

  85. /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
    86. 

  86. #define ANOMALY_05000355 (__SILICON_REVISION__ < 1)
    87. 

  87. /* System Stalled During A Core Access To AMC While A Core Access To NFC FIFO Is Required */
    88. 

  88. #define ANOMALY_05000356 (__SILICON_REVISION__ < 1)
    89. 

  89. /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
    90. 

  90. #define ANOMALY_05000357 (1)
    91. 

  91. /* External Memory Read Access Hangs Core With PLL Bypass */
    92. 

  92. #define ANOMALY_05000360 (1)
    93. 

  93. /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
    94. 

  94. #define ANOMALY_05000365 (1)
    95. 

  95. /* WURESET Bit In SYSCR Register Does Not Properly Indicate Hibernate Wake-Up */
    96. 

  96. #define ANOMALY_05000367 (__SILICON_REVISION__ < 1)
    97. 

  97. /* Addressing Conflict between Boot ROM and Asynchronous Memory */
    98. 

  98. #define ANOMALY_05000369 (1)
    99. 

  99. /* Default PLL MSEL and SSEL Settings Can Cause 400MHz Product To Violate Specifications */
    100. 

  100. #define ANOMALY_05000370 (__SILICON_REVISION__ < 1)
    101. 

  101. /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
    102. 

  102. #define ANOMALY_05000371 (__SILICON_REVISION__ < 2)
    103. 

  103. /* USB DP/DM Data Pins May Lose State When Entering Hibernate */
    104. 

  104. #define ANOMALY_05000372 (__SILICON_REVISION__ < 1)
    105. 

  105. /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
    106. 

  106. #define ANOMALY_05000378 (__SILICON_REVISION__ < 2)
    107. 

  107. /* 16-Bit NAND FLASH Boot Mode Is Not Functional */
    108. 

  108. #define ANOMALY_05000379 (1)
    109. 

  109. /* 8-Bit NAND Flash Boot Mode Not Functional */
    110. 

  110. #define ANOMALY_05000382 (__SILICON_REVISION__ < 1)
    111. 

  111. /* Some ATAPI Modes Are Not Functional */
    112. 

  112. #define ANOMALY_05000383 (1)
    113. 

  113. /* Boot from OTP Memory Not Functional */
    114. 

  114. #define ANOMALY_05000385 (__SILICON_REVISION__ < 1)
    115. 

  115. /* bfrom_SysControl() Firmware Routine Not Functional */
    116. 

  116. #define ANOMALY_05000386 (__SILICON_REVISION__ < 1)
    117. 

  117. /* Programmable Preboot Settings Not Functional */
    118. 

  118. #define ANOMALY_05000387 (__SILICON_REVISION__ < 1)
    119. 

  119. /* CRC32 Checksum Support Not Functional */
    120. 

  120. #define ANOMALY_05000388 (__SILICON_REVISION__ < 1)
    121. 

  121. /* Reset Vector Must Not Be in SDRAM Memory Space */
    122. 

  122. #define ANOMALY_05000389 (__SILICON_REVISION__ < 1)
    123. 

  123. /* Changed Meaning of BCODE Field in SYSCR Register */
    124. 

  124. #define ANOMALY_05000390 (__SILICON_REVISION__ < 1)
    125. 

  125. /* Repeated Boot from Page-Mode or Burst-Mode Flash Memory May Fail */
    126. 

  126. #define ANOMALY_05000391 (__SILICON_REVISION__ < 1)
    127. 

  127. /* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
    128. 

  128. #define ANOMALY_05000392 (__SILICON_REVISION__ < 1)
    129. 

  129. /* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
    130. 

  130. #define ANOMALY_05000393 (__SILICON_REVISION__ < 1)
    131. 

  131. /* Log Buffer Not Functional */
    132. 

  132. #define ANOMALY_05000394 (__SILICON_REVISION__ < 1)
    133. 

  133. /* Hook Routine Not Functional */
    134. 

  134. #define ANOMALY_05000395 (__SILICON_REVISION__ < 1)
    135. 

  135. /* Header Indirect Bit Not Functional */
    136. 

  136. #define ANOMALY_05000396 (__SILICON_REVISION__ < 1)
    137. 

  137. /* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
    138. 

  138. #define ANOMALY_05000397 (__SILICON_REVISION__ < 1)
    139. 

  139. /* Lockbox SESR Disallows Certain User Interrupts */
    140. 

  140. #define ANOMALY_05000404 (__SILICON_REVISION__ < 2)
    141. 

  141. /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
    142. 

  142. #define ANOMALY_05000405 (1)
    143. 

  143. /* Lockbox SESR Argument Checking Does Not Check L2 Memory Protection Range */
    144. 

  144. #define ANOMALY_05000406 (__SILICON_REVISION__ < 2)
    145. 

  145. /* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
    146. 

  146. #define ANOMALY_05000407 (__SILICON_REVISION__ < 2)
    147. 

  147. /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
    148. 

  148. #define ANOMALY_05000408 (1)
    149. 

  149. /* Lockbox firmware leaves MDMA0 channel enabled */
    150. 

  150. #define ANOMALY_05000409 (__SILICON_REVISION__ < 2)
    151. 

  151. /* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
    152. 

  152. #define ANOMALY_05000411 (__SILICON_REVISION__ < 2)
    153. 

  153. /* NAND Boot Mode Not Compatible With Some NAND Flash Devices */
    154. 

  154. #define ANOMALY_05000413 (__SILICON_REVISION__ < 2)
    155. 

  155. /* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
    156. 

  156. #define ANOMALY_05000414 (__SILICON_REVISION__ < 2)
    157. 

  157. /* Speculative Fetches Can Cause Undesired External FIFO Operations */
    158. 

  158. #define ANOMALY_05000416 (1)
    159. 

  159. /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
    160. 

  160. #define ANOMALY_05000425 (1)
    161. 

  161. /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
    162. 

  162. #define ANOMALY_05000426 (1)
    163. 

  163. /* CORE_EPPI_PRIO bit and SYS_EPPI_PRIO bit in the HMDMA1_CONTROL register are not functional */
    164. 

  164. #define ANOMALY_05000427 (__SILICON_REVISION__ < 2)
    165. 

  165. /* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
    166. 

  166. #define ANOMALY_05000429 (__SILICON_REVISION__ < 2)
    167. 

  167. /* Software System Reset Corrupts PLL_LOCKCNT Register */
    168. 

  168. #define ANOMALY_05000430 (__SILICON_REVISION__ >= 2)
    169. 

  169. /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
    170. 

  170. #define ANOMALY_05000431 (__SILICON_REVISION__ < 3)
    171. 

  171. /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
    172. 

  172. #define ANOMALY_05000434 (1)
    173. 

  173. /* OTP Write Accesses Not Supported */
    174. 

  174. #define ANOMALY_05000442 (__SILICON_REVISION__ < 1)
    175. 

  175. /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
    176. 

  176. #define ANOMALY_05000443 (1)
    177. 

  177. /* CDMAPRIO and L2DMAPRIO Bits in the SYSCR Register Are Not Functional */
    178. 

  178. #define ANOMALY_05000446 (1)
    179. 

  179. /* UART IrDA Receiver Fails on Extended Bit Pulses */
    180. 

  180. #define ANOMALY_05000447 (1)
    181. 

  181. /* DDR Clock Duty Cycle Spec Violation (tCH, tCL) */
    182. 

  182. #define ANOMALY_05000448 (__SILICON_REVISION__ == 1)
    183. 

  183. /* Reduced Timing Margins on DDR Output Setup and Hold (tDS and tDH) */
    184. 

  184. #define ANOMALY_05000449 (__SILICON_REVISION__ == 1)
    185. 

  185. /* USB DMA Mode 1 Short Packet Data Corruption */
    186. 

  186. #define ANOMALY_05000450 (1)
    187. 

  187. /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
    188. 

  188. #define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
    189. 

  189. /* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
    190. 

  190. #define ANOMALY_05000456 (1)
    191. 

  191. /* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
    192. 

  192. #define ANOMALY_05000457 (1)
    193. 

  193. /* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
    194. 

  194. #define ANOMALY_05000460 (1)
    195. 

  195. /* False Hardware Error when RETI Points to Invalid Memory */
    196. 

  196. #define ANOMALY_05000461 (1)
    197. 

  197. /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
    198. 

  198. #define ANOMALY_05000462 (1)
    199. 

  199. /* USB DMA RX Data Corruption */
    200. 

  200. #define ANOMALY_05000463 (1)
    201. 

  201. /* USB TX DMA Hang */
    202. 

  202. #define ANOMALY_05000464 (1)
    203. 

  203. /* USB Rx DMA hang */
    204. 

  204. #define ANOMALY_05000465 (1)
    205. 

  205. /* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
    206. 

  206. #define ANOMALY_05000466 (1)
    207. 

  207. /* Possible RX data corruption when control & data EP FIFOs are accessed via the core */
    208. 

  208. #define ANOMALY_05000467 (1)
    209. 

  209. /* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
    210. 

  210. #define ANOMALY_05000473 (1)
    211. 

  211. /* Access to DDR-SDRAM causes system hang under certain PLL/VR settings */
    212. 

  212. #define ANOMALY_05000474 (1)
    213. 

  213. /* Core Hang With L2/L3 Configured in Writeback Cache Mode */
    214. 

  214. #define ANOMALY_05000475 (1)
    215. 

  215. /* TESTSET Instruction Cannot Be Interrupted */
    216. 

  216. #define ANOMALY_05000477 (1)
    217. 

  217. 

  218. /* Anomalies that don't exist on this proc */
    219. 

  219. #define ANOMALY_05000099 (0)
    220. 

  220. #define ANOMALY_05000120 (0)
    221. 

  221. #define ANOMALY_05000125 (0)
    222. 

  222. #define ANOMALY_05000149 (0)
    223. 

  223. #define ANOMALY_05000158 (0)
    224. 

  224. #define ANOMALY_05000171 (0)
    225. 

  225. #define ANOMALY_05000179 (0)
    226. 

  226. #define ANOMALY_05000182 (0)
    227. 

  227. #define ANOMALY_05000183 (0)
    228. 

  228. #define ANOMALY_05000189 (0)
    229. 

  229. #define ANOMALY_05000198 (0)
    230. 

  230. #define ANOMALY_05000202 (0)
    231. 

  231. #define ANOMALY_05000215 (0)
    232. 

  232. #define ANOMALY_05000227 (0)
    233. 

  233. #define ANOMALY_05000230 (0)
    234. 

  234. #define ANOMALY_05000231 (0)
    235. 

  235. #define ANOMALY_05000233 (0)
    236. 

  236. #define ANOMALY_05000234 (0)
    237. 

  237. #define ANOMALY_05000242 (0)
    238. 

  238. #define ANOMALY_05000244 (0)
    239. 

  239. #define ANOMALY_05000248 (0)
    240. 

  240. #define ANOMALY_05000250 (0)
    241. 

  241. #define ANOMALY_05000254 (0)
    242. 

  242. #define ANOMALY_05000257 (0)
    243. 

  243. #define ANOMALY_05000261 (0)
    244. 

  244. #define ANOMALY_05000263 (0)
    245. 

  245. #define ANOMALY_05000266 (0)
    246. 

  246. #define ANOMALY_05000273 (0)
    247. 

  247. #define ANOMALY_05000274 (0)
    248. 

  248. #define ANOMALY_05000278 (0)
    249. 

  249. #define ANOMALY_05000283 (0)
    250. 

  250. #define ANOMALY_05000287 (0)
    251. 

  251. #define ANOMALY_05000301 (0)
    252. 

  252. #define ANOMALY_05000305 (0)
    253. 

  253. #define ANOMALY_05000307 (0)
    254. 

  254. #define ANOMALY_05000311 (0)
    255. 

  255. #define ANOMALY_05000315 (0)
    256. 

  256. #define ANOMALY_05000323 (0)
    257. 

  257. #define ANOMALY_05000362 (1)
    258. 

  258. #define ANOMALY_05000363 (0)
    259. 

  259. #define ANOMALY_05000364 (0)
    260. 

  260. #define ANOMALY_05000380 (0)
    261. 

  261. #define ANOMALY_05000400 (0)
    262. 

  262. #define ANOMALY_05000402 (0)
    263. 

  263. #define ANOMALY_05000412 (0)
    264. 

  264. #define ANOMALY_05000432 (0)
    265. 

  265. #define ANOMALY_05000435 (0)
    266. 

  266. 

  267. #endif
    268. 

  268.