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/drivers/pcmcia/cardbus.c

https://gitlab.com/rychly/nst-linux-sources
C | 252 lines | 145 code | 46 blank | 61 comment | 35 complexity | 336f681ede56011b510f8688f0bfc12e MD5 | raw file
  1. /*
  2. * cardbus.c -- 16-bit PCMCIA core support
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * The initial developer of the original code is David A. Hinds
  9. * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
  10. * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
  11. *
  12. * (C) 1999 David A. Hinds
  13. */
  14. /*
  15. * Cardbus handling has been re-written to be more of a PCI bridge thing,
  16. * and the PCI code basically does all the resource handling.
  17. *
  18. * Linus, Jan 2000
  19. */
  20. #include <linux/module.h>
  21. #include <linux/kernel.h>
  22. #include <linux/string.h>
  23. #include <linux/slab.h>
  24. #include <linux/mm.h>
  25. #include <linux/pci.h>
  26. #include <linux/ioport.h>
  27. #include <asm/irq.h>
  28. #include <asm/io.h>
  29. #include <pcmcia/cs_types.h>
  30. #include <pcmcia/ss.h>
  31. #include <pcmcia/cs.h>
  32. #include <pcmcia/cistpl.h>
  33. #include "cs_internal.h"
  34. /*====================================================================*/
  35. /* Offsets in the Expansion ROM Image Header */
  36. #define ROM_SIGNATURE 0x0000 /* 2 bytes */
  37. #define ROM_DATA_PTR 0x0018 /* 2 bytes */
  38. /* Offsets in the CardBus PC Card Data Structure */
  39. #define PCDATA_SIGNATURE 0x0000 /* 4 bytes */
  40. #define PCDATA_VPD_PTR 0x0008 /* 2 bytes */
  41. #define PCDATA_LENGTH 0x000a /* 2 bytes */
  42. #define PCDATA_REVISION 0x000c
  43. #define PCDATA_IMAGE_SZ 0x0010 /* 2 bytes */
  44. #define PCDATA_ROM_LEVEL 0x0012 /* 2 bytes */
  45. #define PCDATA_CODE_TYPE 0x0014
  46. #define PCDATA_INDICATOR 0x0015
  47. /*=====================================================================
  48. Expansion ROM's have a special layout, and pointers specify an
  49. image number and an offset within that image. xlate_rom_addr()
  50. converts an image/offset address to an absolute offset from the
  51. ROM's base address.
  52. =====================================================================*/
  53. static u_int xlate_rom_addr(void __iomem *b, u_int addr)
  54. {
  55. u_int img = 0, ofs = 0, sz;
  56. u_short data;
  57. while ((readb(b) == 0x55) && (readb(b + 1) == 0xaa)) {
  58. if (img == (addr >> 28))
  59. return (addr & 0x0fffffff) + ofs;
  60. data = readb(b + ROM_DATA_PTR) + (readb(b + ROM_DATA_PTR + 1) << 8);
  61. sz = 512 * (readb(b + data + PCDATA_IMAGE_SZ) +
  62. (readb(b + data + PCDATA_IMAGE_SZ + 1) << 8));
  63. if ((sz == 0) || (readb(b + data + PCDATA_INDICATOR) & 0x80))
  64. break;
  65. b += sz;
  66. ofs += sz;
  67. img++;
  68. }
  69. return 0;
  70. }
  71. /*=====================================================================
  72. These are similar to setup_cis_mem and release_cis_mem for 16-bit
  73. cards. The "result" that is used externally is the cb_cis_virt
  74. pointer in the struct pcmcia_socket structure.
  75. =====================================================================*/
  76. static void cb_release_cis_mem(struct pcmcia_socket * s)
  77. {
  78. if (s->cb_cis_virt) {
  79. cs_dbg(s, 1, "cb_release_cis_mem()\n");
  80. iounmap(s->cb_cis_virt);
  81. s->cb_cis_virt = NULL;
  82. s->cb_cis_res = NULL;
  83. }
  84. }
  85. static int cb_setup_cis_mem(struct pcmcia_socket * s, struct resource *res)
  86. {
  87. unsigned int start, size;
  88. if (res == s->cb_cis_res)
  89. return 0;
  90. if (s->cb_cis_res)
  91. cb_release_cis_mem(s);
  92. start = res->start;
  93. size = res->end - start + 1;
  94. s->cb_cis_virt = ioremap(start, size);
  95. if (!s->cb_cis_virt)
  96. return -1;
  97. s->cb_cis_res = res;
  98. return 0;
  99. }
  100. /*=====================================================================
  101. This is used by the CIS processing code to read CIS information
  102. from a CardBus device.
  103. =====================================================================*/
  104. int read_cb_mem(struct pcmcia_socket * s, int space, u_int addr, u_int len, void *ptr)
  105. {
  106. struct pci_dev *dev;
  107. struct resource *res;
  108. cs_dbg(s, 3, "read_cb_mem(%d, %#x, %u)\n", space, addr, len);
  109. dev = pci_get_slot(s->cb_dev->subordinate, 0);
  110. if (!dev)
  111. goto fail;
  112. /* Config space? */
  113. if (space == 0) {
  114. if (addr + len > 0x100)
  115. goto failput;
  116. for (; len; addr++, ptr++, len--)
  117. pci_read_config_byte(dev, addr, ptr);
  118. return 0;
  119. }
  120. res = dev->resource + space - 1;
  121. pci_dev_put(dev);
  122. if (!res->flags)
  123. goto fail;
  124. if (cb_setup_cis_mem(s, res) != 0)
  125. goto fail;
  126. if (space == 7) {
  127. addr = xlate_rom_addr(s->cb_cis_virt, addr);
  128. if (addr == 0)
  129. goto fail;
  130. }
  131. if (addr + len > res->end - res->start)
  132. goto fail;
  133. memcpy_fromio(ptr, s->cb_cis_virt + addr, len);
  134. return 0;
  135. failput:
  136. pci_dev_put(dev);
  137. fail:
  138. memset(ptr, 0xff, len);
  139. return -1;
  140. }
  141. /*=====================================================================
  142. cb_alloc() and cb_free() allocate and free the kernel data
  143. structures for a Cardbus device, and handle the lowest level PCI
  144. device setup issues.
  145. =====================================================================*/
  146. /*
  147. * Since there is only one interrupt available to CardBus
  148. * devices, all devices downstream of this device must
  149. * be using this IRQ.
  150. */
  151. static void cardbus_assign_irqs(struct pci_bus *bus, int irq)
  152. {
  153. struct pci_dev *dev;
  154. list_for_each_entry(dev, &bus->devices, bus_list) {
  155. u8 irq_pin;
  156. pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq_pin);
  157. if (irq_pin) {
  158. dev->irq = irq;
  159. pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
  160. }
  161. if (dev->subordinate)
  162. cardbus_assign_irqs(dev->subordinate, irq);
  163. }
  164. }
  165. int __ref cb_alloc(struct pcmcia_socket * s)
  166. {
  167. struct pci_bus *bus = s->cb_dev->subordinate;
  168. struct pci_dev *dev;
  169. unsigned int max, pass;
  170. s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
  171. // pcibios_fixup_bus(bus);
  172. max = bus->secondary;
  173. for (pass = 0; pass < 2; pass++)
  174. list_for_each_entry(dev, &bus->devices, bus_list)
  175. if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
  176. dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
  177. max = pci_scan_bridge(bus, dev, max, pass);
  178. /*
  179. * Size all resources below the CardBus controller.
  180. */
  181. pci_bus_size_bridges(bus);
  182. pci_bus_assign_resources(bus);
  183. cardbus_assign_irqs(bus, s->pci_irq);
  184. /* socket specific tune function */
  185. if (s->tune_bridge)
  186. s->tune_bridge(s, bus);
  187. pci_enable_bridges(bus);
  188. pci_bus_add_devices(bus);
  189. s->irq.AssignedIRQ = s->pci_irq;
  190. return 0;
  191. }
  192. void cb_free(struct pcmcia_socket * s)
  193. {
  194. struct pci_dev *bridge = s->cb_dev;
  195. cb_release_cis_mem(s);
  196. if (bridge)
  197. pci_remove_behind_bridge(bridge);
  198. }