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/hw/intc/arm_gic_common.c

https://gitlab.com/storedmirrors/qemu
C | 394 lines | 285 code | 46 blank | 63 comment | 45 complexity | 46c533ccd8efac4a4ea0ed1d9b8a9071 MD5 | raw file
  1. /*
  2. * ARM GIC support - common bits of emulated and KVM kernel model
  3. *
  4. * Copyright (c) 2012 Linaro Limited
  5. * Written by Peter Maydell
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation, either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, see <http://www.gnu.org/licenses/>.
  19. */
  20. #include "qemu/osdep.h"
  21. #include "qapi/error.h"
  22. #include "qemu/module.h"
  23. #include "gic_internal.h"
  24. #include "hw/arm/linux-boot-if.h"
  25. #include "hw/qdev-properties.h"
  26. #include "migration/vmstate.h"
  27. static int gic_pre_save(void *opaque)
  28. {
  29. GICState *s = (GICState *)opaque;
  30. ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  31. if (c->pre_save) {
  32. c->pre_save(s);
  33. }
  34. return 0;
  35. }
  36. static int gic_post_load(void *opaque, int version_id)
  37. {
  38. GICState *s = (GICState *)opaque;
  39. ARMGICCommonClass *c = ARM_GIC_COMMON_GET_CLASS(s);
  40. if (c->post_load) {
  41. c->post_load(s);
  42. }
  43. return 0;
  44. }
  45. static bool gic_virt_state_needed(void *opaque)
  46. {
  47. GICState *s = (GICState *)opaque;
  48. return s->virt_extn;
  49. }
  50. static const VMStateDescription vmstate_gic_irq_state = {
  51. .name = "arm_gic_irq_state",
  52. .version_id = 1,
  53. .minimum_version_id = 1,
  54. .fields = (VMStateField[]) {
  55. VMSTATE_UINT8(enabled, gic_irq_state),
  56. VMSTATE_UINT8(pending, gic_irq_state),
  57. VMSTATE_UINT8(active, gic_irq_state),
  58. VMSTATE_UINT8(level, gic_irq_state),
  59. VMSTATE_BOOL(model, gic_irq_state),
  60. VMSTATE_BOOL(edge_trigger, gic_irq_state),
  61. VMSTATE_UINT8(group, gic_irq_state),
  62. VMSTATE_END_OF_LIST()
  63. }
  64. };
  65. static const VMStateDescription vmstate_gic_virt_state = {
  66. .name = "arm_gic_virt_state",
  67. .version_id = 1,
  68. .minimum_version_id = 1,
  69. .needed = gic_virt_state_needed,
  70. .fields = (VMStateField[]) {
  71. /* Virtual interface */
  72. VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU),
  73. VMSTATE_UINT32_ARRAY(h_misr, GICState, GIC_NCPU),
  74. VMSTATE_UINT32_2DARRAY(h_lr, GICState, GIC_MAX_LR, GIC_NCPU),
  75. VMSTATE_UINT32_ARRAY(h_apr, GICState, GIC_NCPU),
  76. /* Virtual CPU interfaces */
  77. VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, GIC_NCPU, GIC_NCPU),
  78. VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, GIC_NCPU, GIC_NCPU),
  79. VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, GIC_NCPU, GIC_NCPU),
  80. VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, GIC_NCPU, GIC_NCPU),
  81. VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, GIC_NCPU, GIC_NCPU),
  82. VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, GIC_NCPU, GIC_NCPU),
  83. VMSTATE_END_OF_LIST()
  84. }
  85. };
  86. static const VMStateDescription vmstate_gic = {
  87. .name = "arm_gic",
  88. .version_id = 12,
  89. .minimum_version_id = 12,
  90. .pre_save = gic_pre_save,
  91. .post_load = gic_post_load,
  92. .fields = (VMStateField[]) {
  93. VMSTATE_UINT32(ctlr, GICState),
  94. VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, 0, GIC_NCPU),
  95. VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
  96. vmstate_gic_irq_state, gic_irq_state),
  97. VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
  98. VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
  99. VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
  100. VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
  101. VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, 0, GIC_NCPU),
  102. VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, 0, GIC_NCPU),
  103. VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, 0, GIC_NCPU),
  104. VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, 0, GIC_NCPU),
  105. VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, 0, GIC_NCPU),
  106. VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
  107. VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
  108. VMSTATE_END_OF_LIST()
  109. },
  110. .subsections = (const VMStateDescription * []) {
  111. &vmstate_gic_virt_state,
  112. NULL
  113. }
  114. };
  115. void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
  116. const MemoryRegionOps *ops,
  117. const MemoryRegionOps *virt_ops)
  118. {
  119. SysBusDevice *sbd = SYS_BUS_DEVICE(s);
  120. int i = s->num_irq - GIC_INTERNAL;
  121. /* For the GIC, also expose incoming GPIO lines for PPIs for each CPU.
  122. * GPIO array layout is thus:
  123. * [0..N-1] SPIs
  124. * [N..N+31] PPIs for CPU 0
  125. * [N+32..N+63] PPIs for CPU 1
  126. * ...
  127. */
  128. i += (GIC_INTERNAL * s->num_cpu);
  129. qdev_init_gpio_in(DEVICE(s), handler, i);
  130. for (i = 0; i < s->num_cpu; i++) {
  131. sysbus_init_irq(sbd, &s->parent_irq[i]);
  132. }
  133. for (i = 0; i < s->num_cpu; i++) {
  134. sysbus_init_irq(sbd, &s->parent_fiq[i]);
  135. }
  136. for (i = 0; i < s->num_cpu; i++) {
  137. sysbus_init_irq(sbd, &s->parent_virq[i]);
  138. }
  139. for (i = 0; i < s->num_cpu; i++) {
  140. sysbus_init_irq(sbd, &s->parent_vfiq[i]);
  141. }
  142. if (s->virt_extn) {
  143. for (i = 0; i < s->num_cpu; i++) {
  144. sysbus_init_irq(sbd, &s->maintenance_irq[i]);
  145. }
  146. }
  147. /* Distributor */
  148. memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
  149. sysbus_init_mmio(sbd, &s->iomem);
  150. /* This is the main CPU interface "for this core". It is always
  151. * present because it is required by both software emulation and KVM.
  152. */
  153. memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
  154. s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
  155. sysbus_init_mmio(sbd, &s->cpuiomem[0]);
  156. if (s->virt_extn) {
  157. memory_region_init_io(&s->vifaceiomem[0], OBJECT(s), virt_ops,
  158. s, "gic_viface", 0x1000);
  159. sysbus_init_mmio(sbd, &s->vifaceiomem[0]);
  160. memory_region_init_io(&s->vcpuiomem, OBJECT(s),
  161. virt_ops ? &virt_ops[1] : NULL,
  162. s, "gic_vcpu", 0x2000);
  163. sysbus_init_mmio(sbd, &s->vcpuiomem);
  164. }
  165. }
  166. static void arm_gic_common_realize(DeviceState *dev, Error **errp)
  167. {
  168. GICState *s = ARM_GIC_COMMON(dev);
  169. int num_irq = s->num_irq;
  170. if (s->num_cpu > GIC_NCPU) {
  171. error_setg(errp, "requested %u CPUs exceeds GIC maximum %d",
  172. s->num_cpu, GIC_NCPU);
  173. return;
  174. }
  175. if (s->num_irq > GIC_MAXIRQ) {
  176. error_setg(errp,
  177. "requested %u interrupt lines exceeds GIC maximum %d",
  178. num_irq, GIC_MAXIRQ);
  179. return;
  180. }
  181. /* ITLinesNumber is represented as (N / 32) - 1 (see
  182. * gic_dist_readb) so this is an implementation imposed
  183. * restriction, not an architectural one:
  184. */
  185. if (s->num_irq < 32 || (s->num_irq % 32)) {
  186. error_setg(errp,
  187. "%d interrupt lines unsupported: not divisible by 32",
  188. num_irq);
  189. return;
  190. }
  191. if (s->security_extn &&
  192. (s->revision == REV_11MPCORE)) {
  193. error_setg(errp, "this GIC revision does not implement "
  194. "the security extensions");
  195. return;
  196. }
  197. if (s->virt_extn) {
  198. if (s->revision != 2) {
  199. error_setg(errp, "GIC virtualization extensions are only "
  200. "supported by revision 2");
  201. return;
  202. }
  203. /* For now, set the number of implemented LRs to 4, as found in most
  204. * real GICv2. This could be promoted as a QOM property if we need to
  205. * emulate a variant with another num_lrs.
  206. */
  207. s->num_lrs = 4;
  208. }
  209. }
  210. static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
  211. int resetprio)
  212. {
  213. int i, j;
  214. for (i = first_cpu; i < first_cpu + s->num_cpu; i++) {
  215. if (s->revision == REV_11MPCORE) {
  216. s->priority_mask[i] = 0xf0;
  217. } else {
  218. s->priority_mask[i] = resetprio;
  219. }
  220. s->current_pending[i] = 1023;
  221. s->running_priority[i] = 0x100;
  222. s->cpu_ctlr[i] = 0;
  223. s->bpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
  224. s->abpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_ABPR : GIC_MIN_ABPR;
  225. if (!gic_is_vcpu(i)) {
  226. for (j = 0; j < GIC_INTERNAL; j++) {
  227. s->priority1[j][i] = resetprio;
  228. }
  229. for (j = 0; j < GIC_NR_SGIS; j++) {
  230. s->sgi_pending[j][i] = 0;
  231. }
  232. }
  233. }
  234. }
  235. static void arm_gic_common_reset(DeviceState *dev)
  236. {
  237. GICState *s = ARM_GIC_COMMON(dev);
  238. int i, j;
  239. int resetprio;
  240. /* If we're resetting a TZ-aware GIC as if secure firmware
  241. * had set it up ready to start a kernel in non-secure,
  242. * we need to set interrupt priorities to a "zero for the
  243. * NS view" value. This is particularly critical for the
  244. * priority_mask[] values, because if they are zero then NS
  245. * code cannot ever rewrite the priority to anything else.
  246. */
  247. if (s->security_extn && s->irq_reset_nonsecure) {
  248. resetprio = 0x80;
  249. } else {
  250. resetprio = 0;
  251. }
  252. memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
  253. arm_gic_common_reset_irq_state(s, 0, resetprio);
  254. if (s->virt_extn) {
  255. /* vCPU states are stored at indexes GIC_NCPU .. GIC_NCPU+num_cpu.
  256. * The exposed vCPU interface does not have security extensions.
  257. */
  258. arm_gic_common_reset_irq_state(s, GIC_NCPU, 0);
  259. }
  260. for (i = 0; i < GIC_NR_SGIS; i++) {
  261. GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK);
  262. GIC_DIST_SET_EDGE_TRIGGER(i);
  263. }
  264. for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
  265. s->priority2[i] = resetprio;
  266. }
  267. for (i = 0; i < GIC_MAXIRQ; i++) {
  268. /* For uniprocessor GICs all interrupts always target the sole CPU */
  269. if (s->num_cpu == 1) {
  270. s->irq_target[i] = 1;
  271. } else {
  272. s->irq_target[i] = 0;
  273. }
  274. }
  275. if (s->security_extn && s->irq_reset_nonsecure) {
  276. for (i = 0; i < GIC_MAXIRQ; i++) {
  277. GIC_DIST_SET_GROUP(i, ALL_CPU_MASK);
  278. }
  279. }
  280. if (s->virt_extn) {
  281. for (i = 0; i < s->num_lrs; i++) {
  282. for (j = 0; j < s->num_cpu; j++) {
  283. s->h_lr[i][j] = 0;
  284. }
  285. }
  286. for (i = 0; i < s->num_cpu; i++) {
  287. s->h_hcr[i] = 0;
  288. s->h_misr[i] = 0;
  289. }
  290. }
  291. s->ctlr = 0;
  292. }
  293. static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
  294. bool secure_boot)
  295. {
  296. GICState *s = ARM_GIC_COMMON(obj);
  297. if (s->security_extn && !secure_boot) {
  298. /* We're directly booting a kernel into NonSecure. If this GIC
  299. * implements the security extensions then we must configure it
  300. * to have all the interrupts be NonSecure (this is a job that
  301. * is done by the Secure boot firmware in real hardware, and in
  302. * this mode QEMU is acting as a minimalist firmware-and-bootloader
  303. * equivalent).
  304. */
  305. s->irq_reset_nonsecure = true;
  306. }
  307. }
  308. static Property arm_gic_common_properties[] = {
  309. DEFINE_PROP_UINT32("num-cpu", GICState, num_cpu, 1),
  310. DEFINE_PROP_UINT32("num-irq", GICState, num_irq, 32),
  311. /* Revision can be 1 or 2 for GIC architecture specification
  312. * versions 1 or 2, or 0 to indicate the legacy 11MPCore GIC.
  313. */
  314. DEFINE_PROP_UINT32("revision", GICState, revision, 1),
  315. /* True if the GIC should implement the security extensions */
  316. DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
  317. /* True if the GIC should implement the virtualization extensions */
  318. DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
  319. DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8),
  320. DEFINE_PROP_END_OF_LIST(),
  321. };
  322. static void arm_gic_common_class_init(ObjectClass *klass, void *data)
  323. {
  324. DeviceClass *dc = DEVICE_CLASS(klass);
  325. ARMLinuxBootIfClass *albifc = ARM_LINUX_BOOT_IF_CLASS(klass);
  326. dc->reset = arm_gic_common_reset;
  327. dc->realize = arm_gic_common_realize;
  328. device_class_set_props(dc, arm_gic_common_properties);
  329. dc->vmsd = &vmstate_gic;
  330. albifc->arm_linux_init = arm_gic_common_linux_init;
  331. }
  332. static const TypeInfo arm_gic_common_type = {
  333. .name = TYPE_ARM_GIC_COMMON,
  334. .parent = TYPE_SYS_BUS_DEVICE,
  335. .instance_size = sizeof(GICState),
  336. .class_size = sizeof(ARMGICCommonClass),
  337. .class_init = arm_gic_common_class_init,
  338. .abstract = true,
  339. .interfaces = (InterfaceInfo []) {
  340. { TYPE_ARM_LINUX_BOOT_IF },
  341. { },
  342. },
  343. };
  344. static void register_types(void)
  345. {
  346. type_register_static(&arm_gic_common_type);
  347. }
  348. type_init(register_types)