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/drivers/edac/i82443bxgx_edac.c

https://gitlab.com/culot/kernel_lge_madai
C | 467 lines | 308 code | 84 blank | 75 comment | 41 complexity | f49de69a68f69daef0858cc3a47e152b MD5 | raw file
  1. /*
  2. * Intel 82443BX/GX (440BX/GX chipset) Memory Controller EDAC kernel
  3. * module (C) 2006 Tim Small
  4. *
  5. * This file may be distributed under the terms of the GNU General
  6. * Public License.
  7. *
  8. * Written by Tim Small <tim@buttersideup.com>, based on work by Linux
  9. * Networx, Thayne Harbaugh, Dan Hollis <goemon at anime dot net> and
  10. * others.
  11. *
  12. * 440GX fix by Jason Uhlenkott <juhlenko@akamai.com>.
  13. *
  14. * Written with reference to 82443BX Host Bridge Datasheet:
  15. * http://download.intel.com/design/chipsets/datashts/29063301.pdf
  16. * references to this document given in [].
  17. *
  18. * This module doesn't support the 440LX, but it may be possible to
  19. * make it do so (the 440LX's register definitions are different, but
  20. * not completely so - I haven't studied them in enough detail to know
  21. * how easy this would be).
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/pci.h>
  26. #include <linux/pci_ids.h>
  27. #include <linux/edac.h>
  28. #include "edac_core.h"
  29. #define I82443_REVISION "0.1"
  30. #define EDAC_MOD_STR "i82443bxgx_edac"
  31. /* The 82443BX supports SDRAM, or EDO (EDO for mobile only), "Memory
  32. * Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory
  33. * rows" "The 82443BX supports multiple-bit error detection and
  34. * single-bit error correction when ECC mode is enabled and
  35. * single/multi-bit error detection when correction is disabled.
  36. * During writes to the DRAM, the 82443BX generates ECC for the data
  37. * on a QWord basis. Partial QWord writes require a read-modify-write
  38. * cycle when ECC is enabled."
  39. */
  40. /* "Additionally, the 82443BX ensures that the data is corrected in
  41. * main memory so that accumulation of errors is prevented. Another
  42. * error within the same QWord would result in a double-bit error
  43. * which is unrecoverable. This is known as hardware scrubbing since
  44. * it requires no software intervention to correct the data in memory."
  45. */
  46. /* [Also see page 100 (section 4.3), "DRAM Interface"]
  47. * [Also see page 112 (section 4.6.1.4), ECC]
  48. */
  49. #define I82443BXGX_NR_CSROWS 8
  50. #define I82443BXGX_NR_CHANS 1
  51. #define I82443BXGX_NR_DIMMS 4
  52. /* 82443 PCI Device 0 */
  53. #define I82443BXGX_NBXCFG 0x50 /* 32bit register starting at this PCI
  54. * config space offset */
  55. #define I82443BXGX_NBXCFG_OFFSET_NON_ECCROW 24 /* Array of bits, zero if
  56. * row is non-ECC */
  57. #define I82443BXGX_NBXCFG_OFFSET_DRAM_FREQ 12 /* 2 bits,00=100MHz,10=66 MHz */
  58. #define I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY 7 /* 2 bits: */
  59. #define I82443BXGX_NBXCFG_INTEGRITY_NONE 0x0 /* 00 = Non-ECC */
  60. #define I82443BXGX_NBXCFG_INTEGRITY_EC 0x1 /* 01 = EC (only) */
  61. #define I82443BXGX_NBXCFG_INTEGRITY_ECC 0x2 /* 10 = ECC */
  62. #define I82443BXGX_NBXCFG_INTEGRITY_SCRUB 0x3 /* 11 = ECC + HW Scrub */
  63. #define I82443BXGX_NBXCFG_OFFSET_ECC_DIAG_ENABLE 6
  64. /* 82443 PCI Device 0 */
  65. #define I82443BXGX_EAP 0x80 /* 32bit register starting at this PCI
  66. * config space offset, Error Address
  67. * Pointer Register */
  68. #define I82443BXGX_EAP_OFFSET_EAP 12 /* High 20 bits of error address */
  69. #define I82443BXGX_EAP_OFFSET_MBE BIT(1) /* Err at EAP was multi-bit (W1TC) */
  70. #define I82443BXGX_EAP_OFFSET_SBE BIT(0) /* Err at EAP was single-bit (W1TC) */
  71. #define I82443BXGX_ERRCMD 0x90 /* 8bit register starting at this PCI
  72. * config space offset. */
  73. #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_MBE BIT(1) /* 1 = enable */
  74. #define I82443BXGX_ERRCMD_OFFSET_SERR_ON_SBE BIT(0) /* 1 = enable */
  75. #define I82443BXGX_ERRSTS 0x91 /* 16bit register starting at this PCI
  76. * config space offset. */
  77. #define I82443BXGX_ERRSTS_OFFSET_MBFRE 5 /* 3 bits - first err row multibit */
  78. #define I82443BXGX_ERRSTS_OFFSET_MEF BIT(4) /* 1 = MBE occurred */
  79. #define I82443BXGX_ERRSTS_OFFSET_SBFRE 1 /* 3 bits - first err row singlebit */
  80. #define I82443BXGX_ERRSTS_OFFSET_SEF BIT(0) /* 1 = SBE occurred */
  81. #define I82443BXGX_DRAMC 0x57 /* 8bit register starting at this PCI
  82. * config space offset. */
  83. #define I82443BXGX_DRAMC_OFFSET_DT 3 /* 2 bits, DRAM Type */
  84. #define I82443BXGX_DRAMC_DRAM_IS_EDO 0 /* 00 = EDO */
  85. #define I82443BXGX_DRAMC_DRAM_IS_SDRAM 1 /* 01 = SDRAM */
  86. #define I82443BXGX_DRAMC_DRAM_IS_RSDRAM 2 /* 10 = Registered SDRAM */
  87. #define I82443BXGX_DRB 0x60 /* 8x 8bit registers starting at this PCI
  88. * config space offset. */
  89. /* FIXME - don't poll when ECC disabled? */
  90. struct i82443bxgx_edacmc_error_info {
  91. u32 eap;
  92. };
  93. static struct edac_pci_ctl_info *i82443bxgx_pci;
  94. static struct pci_dev *mci_pdev; /* init dev: in case that AGP code has
  95. * already registered driver
  96. */
  97. static int i82443bxgx_registered = 1;
  98. static void i82443bxgx_edacmc_get_error_info(struct mem_ctl_info *mci,
  99. struct i82443bxgx_edacmc_error_info
  100. *info)
  101. {
  102. struct pci_dev *pdev;
  103. pdev = to_pci_dev(mci->dev);
  104. pci_read_config_dword(pdev, I82443BXGX_EAP, &info->eap);
  105. if (info->eap & I82443BXGX_EAP_OFFSET_SBE)
  106. /* Clear error to allow next error to be reported [p.61] */
  107. pci_write_bits32(pdev, I82443BXGX_EAP,
  108. I82443BXGX_EAP_OFFSET_SBE,
  109. I82443BXGX_EAP_OFFSET_SBE);
  110. if (info->eap & I82443BXGX_EAP_OFFSET_MBE)
  111. /* Clear error to allow next error to be reported [p.61] */
  112. pci_write_bits32(pdev, I82443BXGX_EAP,
  113. I82443BXGX_EAP_OFFSET_MBE,
  114. I82443BXGX_EAP_OFFSET_MBE);
  115. }
  116. static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
  117. struct
  118. i82443bxgx_edacmc_error_info
  119. *info, int handle_errors)
  120. {
  121. int error_found = 0;
  122. u32 eapaddr, page, pageoffset;
  123. /* bits 30:12 hold the 4kb block in which the error occurred
  124. * [p.61] */
  125. eapaddr = (info->eap & 0xfffff000);
  126. page = eapaddr >> PAGE_SHIFT;
  127. pageoffset = eapaddr - (page << PAGE_SHIFT);
  128. if (info->eap & I82443BXGX_EAP_OFFSET_SBE) {
  129. error_found = 1;
  130. if (handle_errors)
  131. edac_mc_handle_ce(mci, page, pageoffset,
  132. /* 440BX/GX don't make syndrome information
  133. * available */
  134. 0, edac_mc_find_csrow_by_page(mci, page), 0,
  135. mci->ctl_name);
  136. }
  137. if (info->eap & I82443BXGX_EAP_OFFSET_MBE) {
  138. error_found = 1;
  139. if (handle_errors)
  140. edac_mc_handle_ue(mci, page, pageoffset,
  141. edac_mc_find_csrow_by_page(mci, page),
  142. mci->ctl_name);
  143. }
  144. return error_found;
  145. }
  146. static void i82443bxgx_edacmc_check(struct mem_ctl_info *mci)
  147. {
  148. struct i82443bxgx_edacmc_error_info info;
  149. debugf1("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__);
  150. i82443bxgx_edacmc_get_error_info(mci, &info);
  151. i82443bxgx_edacmc_process_error_info(mci, &info, 1);
  152. }
  153. static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
  154. struct pci_dev *pdev,
  155. enum edac_type edac_mode,
  156. enum mem_type mtype)
  157. {
  158. struct csrow_info *csrow;
  159. int index;
  160. u8 drbar, dramc;
  161. u32 row_base, row_high_limit, row_high_limit_last;
  162. pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
  163. row_high_limit_last = 0;
  164. for (index = 0; index < mci->nr_csrows; index++) {
  165. csrow = &mci->csrows[index];
  166. pci_read_config_byte(pdev, I82443BXGX_DRB + index, &drbar);
  167. debugf1("MC%d: %s: %s() Row=%d DRB = %#0x\n",
  168. mci->mc_idx, __FILE__, __func__, index, drbar);
  169. row_high_limit = ((u32) drbar << 23);
  170. /* find the DRAM Chip Select Base address and mask */
  171. debugf1("MC%d: %s: %s() Row=%d, "
  172. "Boundary Address=%#0x, Last = %#0x\n",
  173. mci->mc_idx, __FILE__, __func__, index, row_high_limit,
  174. row_high_limit_last);
  175. /* 440GX goes to 2GB, represented with a DRB of 0. */
  176. if (row_high_limit_last && !row_high_limit)
  177. row_high_limit = 1UL << 31;
  178. /* This row is empty [p.49] */
  179. if (row_high_limit == row_high_limit_last)
  180. continue;
  181. row_base = row_high_limit_last;
  182. csrow->first_page = row_base >> PAGE_SHIFT;
  183. csrow->last_page = (row_high_limit >> PAGE_SHIFT) - 1;
  184. csrow->nr_pages = csrow->last_page - csrow->first_page + 1;
  185. /* EAP reports in 4kilobyte granularity [61] */
  186. csrow->grain = 1 << 12;
  187. csrow->mtype = mtype;
  188. /* I don't think 440BX can tell you device type? FIXME? */
  189. csrow->dtype = DEV_UNKNOWN;
  190. /* Mode is global to all rows on 440BX */
  191. csrow->edac_mode = edac_mode;
  192. row_high_limit_last = row_high_limit;
  193. }
  194. }
  195. static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
  196. {
  197. struct mem_ctl_info *mci;
  198. u8 dramc;
  199. u32 nbxcfg, ecc_mode;
  200. enum mem_type mtype;
  201. enum edac_type edac_mode;
  202. debugf0("MC: %s: %s()\n", __FILE__, __func__);
  203. /* Something is really hosed if PCI config space reads from
  204. * the MC aren't working.
  205. */
  206. if (pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg))
  207. return -EIO;
  208. mci = edac_mc_alloc(0, I82443BXGX_NR_CSROWS, I82443BXGX_NR_CHANS, 0);
  209. if (mci == NULL)
  210. return -ENOMEM;
  211. debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci);
  212. mci->dev = &pdev->dev;
  213. mci->mtype_cap = MEM_FLAG_EDO | MEM_FLAG_SDR | MEM_FLAG_RDR;
  214. mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_EC | EDAC_FLAG_SECDED;
  215. pci_read_config_byte(pdev, I82443BXGX_DRAMC, &dramc);
  216. switch ((dramc >> I82443BXGX_DRAMC_OFFSET_DT) & (BIT(0) | BIT(1))) {
  217. case I82443BXGX_DRAMC_DRAM_IS_EDO:
  218. mtype = MEM_EDO;
  219. break;
  220. case I82443BXGX_DRAMC_DRAM_IS_SDRAM:
  221. mtype = MEM_SDR;
  222. break;
  223. case I82443BXGX_DRAMC_DRAM_IS_RSDRAM:
  224. mtype = MEM_RDR;
  225. break;
  226. default:
  227. debugf0("Unknown/reserved DRAM type value "
  228. "in DRAMC register!\n");
  229. mtype = -MEM_UNKNOWN;
  230. }
  231. if ((mtype == MEM_SDR) || (mtype == MEM_RDR))
  232. mci->edac_cap = mci->edac_ctl_cap;
  233. else
  234. mci->edac_cap = EDAC_FLAG_NONE;
  235. mci->scrub_cap = SCRUB_FLAG_HW_SRC;
  236. pci_read_config_dword(pdev, I82443BXGX_NBXCFG, &nbxcfg);
  237. ecc_mode = ((nbxcfg >> I82443BXGX_NBXCFG_OFFSET_DRAM_INTEGRITY) &
  238. (BIT(0) | BIT(1)));
  239. mci->scrub_mode = (ecc_mode == I82443BXGX_NBXCFG_INTEGRITY_SCRUB)
  240. ? SCRUB_HW_SRC : SCRUB_NONE;
  241. switch (ecc_mode) {
  242. case I82443BXGX_NBXCFG_INTEGRITY_NONE:
  243. edac_mode = EDAC_NONE;
  244. break;
  245. case I82443BXGX_NBXCFG_INTEGRITY_EC:
  246. edac_mode = EDAC_EC;
  247. break;
  248. case I82443BXGX_NBXCFG_INTEGRITY_ECC:
  249. case I82443BXGX_NBXCFG_INTEGRITY_SCRUB:
  250. edac_mode = EDAC_SECDED;
  251. break;
  252. default:
  253. debugf0("%s(): Unknown/reserved ECC state "
  254. "in NBXCFG register!\n", __func__);
  255. edac_mode = EDAC_UNKNOWN;
  256. break;
  257. }
  258. i82443bxgx_init_csrows(mci, pdev, edac_mode, mtype);
  259. /* Many BIOSes don't clear error flags on boot, so do this
  260. * here, or we get "phantom" errors occurring at module-load
  261. * time. */
  262. pci_write_bits32(pdev, I82443BXGX_EAP,
  263. (I82443BXGX_EAP_OFFSET_SBE |
  264. I82443BXGX_EAP_OFFSET_MBE),
  265. (I82443BXGX_EAP_OFFSET_SBE |
  266. I82443BXGX_EAP_OFFSET_MBE));
  267. mci->mod_name = EDAC_MOD_STR;
  268. mci->mod_ver = I82443_REVISION;
  269. mci->ctl_name = "I82443BXGX";
  270. mci->dev_name = pci_name(pdev);
  271. mci->edac_check = i82443bxgx_edacmc_check;
  272. mci->ctl_page_to_phys = NULL;
  273. if (edac_mc_add_mc(mci)) {
  274. debugf3("%s(): failed edac_mc_add_mc()\n", __func__);
  275. goto fail;
  276. }
  277. /* allocating generic PCI control info */
  278. i82443bxgx_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
  279. if (!i82443bxgx_pci) {
  280. printk(KERN_WARNING
  281. "%s(): Unable to create PCI control\n",
  282. __func__);
  283. printk(KERN_WARNING
  284. "%s(): PCI error report via EDAC not setup\n",
  285. __func__);
  286. }
  287. debugf3("MC: %s: %s(): success\n", __FILE__, __func__);
  288. return 0;
  289. fail:
  290. edac_mc_free(mci);
  291. return -ENODEV;
  292. }
  293. EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_probe1);
  294. /* returns count (>= 0), or negative on error */
  295. static int __devinit i82443bxgx_edacmc_init_one(struct pci_dev *pdev,
  296. const struct pci_device_id *ent)
  297. {
  298. int rc;
  299. debugf0("MC: %s: %s()\n", __FILE__, __func__);
  300. /* don't need to call pci_enable_device() */
  301. rc = i82443bxgx_edacmc_probe1(pdev, ent->driver_data);
  302. if (mci_pdev == NULL)
  303. mci_pdev = pci_dev_get(pdev);
  304. return rc;
  305. }
  306. static void __devexit i82443bxgx_edacmc_remove_one(struct pci_dev *pdev)
  307. {
  308. struct mem_ctl_info *mci;
  309. debugf0("%s: %s()\n", __FILE__, __func__);
  310. if (i82443bxgx_pci)
  311. edac_pci_release_generic_ctl(i82443bxgx_pci);
  312. if ((mci = edac_mc_del_mc(&pdev->dev)) == NULL)
  313. return;
  314. edac_mc_free(mci);
  315. }
  316. EXPORT_SYMBOL_GPL(i82443bxgx_edacmc_remove_one);
  317. static DEFINE_PCI_DEVICE_TABLE(i82443bxgx_pci_tbl) = {
  318. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0)},
  319. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2)},
  320. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0)},
  321. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2)},
  322. {0,} /* 0 terminated list. */
  323. };
  324. MODULE_DEVICE_TABLE(pci, i82443bxgx_pci_tbl);
  325. static struct pci_driver i82443bxgx_edacmc_driver = {
  326. .name = EDAC_MOD_STR,
  327. .probe = i82443bxgx_edacmc_init_one,
  328. .remove = __devexit_p(i82443bxgx_edacmc_remove_one),
  329. .id_table = i82443bxgx_pci_tbl,
  330. };
  331. static int __init i82443bxgx_edacmc_init(void)
  332. {
  333. int pci_rc;
  334. /* Ensure that the OPSTATE is set correctly for POLL or NMI */
  335. opstate_init();
  336. pci_rc = pci_register_driver(&i82443bxgx_edacmc_driver);
  337. if (pci_rc < 0)
  338. goto fail0;
  339. if (mci_pdev == NULL) {
  340. const struct pci_device_id *id = &i82443bxgx_pci_tbl[0];
  341. int i = 0;
  342. i82443bxgx_registered = 0;
  343. while (mci_pdev == NULL && id->vendor != 0) {
  344. mci_pdev = pci_get_device(id->vendor,
  345. id->device, NULL);
  346. i++;
  347. id = &i82443bxgx_pci_tbl[i];
  348. }
  349. if (!mci_pdev) {
  350. debugf0("i82443bxgx pci_get_device fail\n");
  351. pci_rc = -ENODEV;
  352. goto fail1;
  353. }
  354. pci_rc = i82443bxgx_edacmc_init_one(mci_pdev, i82443bxgx_pci_tbl);
  355. if (pci_rc < 0) {
  356. debugf0("i82443bxgx init fail\n");
  357. pci_rc = -ENODEV;
  358. goto fail1;
  359. }
  360. }
  361. return 0;
  362. fail1:
  363. pci_unregister_driver(&i82443bxgx_edacmc_driver);
  364. fail0:
  365. if (mci_pdev != NULL)
  366. pci_dev_put(mci_pdev);
  367. return pci_rc;
  368. }
  369. static void __exit i82443bxgx_edacmc_exit(void)
  370. {
  371. pci_unregister_driver(&i82443bxgx_edacmc_driver);
  372. if (!i82443bxgx_registered)
  373. i82443bxgx_edacmc_remove_one(mci_pdev);
  374. if (mci_pdev)
  375. pci_dev_put(mci_pdev);
  376. }
  377. module_init(i82443bxgx_edacmc_init);
  378. module_exit(i82443bxgx_edacmc_exit);
  379. MODULE_LICENSE("GPL");
  380. MODULE_AUTHOR("Tim Small <tim@buttersideup.com> - WPAD");
  381. MODULE_DESCRIPTION("EDAC MC support for Intel 82443BX/GX memory controllers");
  382. module_param(edac_op_state, int, 0444);
  383. MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");