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/u-boot-2011.09/arch/blackfin/include/asm/mach-bf537/anomaly.h

https://gitlab.com/pine64-android/brandy
C Header | 241 lines | 141 code | 9 blank | 91 comment | 12 complexity | edc66a5da41a1017c5144bdaa33c2f31 MD5 | raw file
    

  1. /*
    2. 

  2.  * DO NOT EDIT THIS FILE
    3. 

  3.  * This file is under version control at
    4. 

  4.  *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
    5. 

  5.  * and can be replaced with that version at any time
    6. 

  6.  * DO NOT EDIT THIS FILE
    7. 

  7.  *
    8. 

  8.  * Copyright 2004-2011 Analog Devices Inc.
    9. 

  9.  * Licensed under the ADI BSD license.
    10. 

  10.  *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
    11. 

  11.  */
    12. 

  12. 

  13. /* This file should be up to date with:
    14. 

  14.  *  - Revision F, 05/23/2011; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
    15. 

  15.  */
    16. 

  16. 

  17. #ifndef _MACH_ANOMALY_H_
    18. 

  18. #define _MACH_ANOMALY_H_
    19. 

  19. 

  20. /* We do not support 0.1 silicon - sorry */
    21. 

  21. #if __SILICON_REVISION__ < 2
    22. 

  22. # error will not work on BF537 silicon version 0.0 or 0.1
    23. 

  23. #endif
    24. 

  24. 

  25. #if defined(__ADSPBF534__)
    26. 

  26. # define ANOMALY_BF534 1
    27. 

  27. #else
    28. 

  28. # define ANOMALY_BF534 0
    29. 

  29. #endif
    30. 

  30. #if defined(__ADSPBF536__)
    31. 

  31. # define ANOMALY_BF536 1
    32. 

  32. #else
    33. 

  33. # define ANOMALY_BF536 0
    34. 

  34. #endif
    35. 

  35. #if defined(__ADSPBF537__)
    36. 

  36. # define ANOMALY_BF537 1
    37. 

  37. #else
    38. 

  38. # define ANOMALY_BF537 0
    39. 

  39. #endif
    40. 

  40. 

  41. /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
    42. 

  42. #define ANOMALY_05000074 (1)
    43. 

  43. /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
    44. 

  44. #define ANOMALY_05000119 (1)
    45. 

  45. /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
    46. 

  46. #define ANOMALY_05000122 (1)
    47. 

  47. /* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
    48. 

  48. #define ANOMALY_05000180 (1)
    49. 

  49. /* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
    50. 

  50. #define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
    51. 

  51. /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
    52. 

  52. #define ANOMALY_05000245 (1)
    53. 

  53. /* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
    54. 

  54. #define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
    55. 

  55. /* EMAC TX DMA Error After an Early Frame Abort */
    56. 

  56. #define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
    57. 

  57. /* Maximum External Clock Speed for Timers */
    58. 

  58. #define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
    59. 

  59. /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
    60. 

  60. #define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
    61. 

  61. /* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
    62. 

  62. #define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
    63. 

  63. /* EMAC MDIO Input Latched on Wrong MDC Edge */
    64. 

  64. #define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
    65. 

  65. /* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
    66. 

  66. #define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
    67. 

  67. /* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
    68. 

  68. #define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
    69. 

  69. /* ICPLB_STATUS MMR Register May Be Corrupted */
    70. 

  70. #define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
    71. 

  71. /* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
    72. 

  72. #define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
    73. 

  73. /* Stores To Data Cache May Be Lost */
    74. 

  74. #define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
    75. 

  75. /* Hardware Loop Corrupted When Taking an ICPLB Exception */
    76. 

  76. #define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
    77. 

  77. /* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
    78. 

  78. #define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
    79. 

  79. /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
    80. 

  80. #define ANOMALY_05000265 (1)
    81. 

  81. /* Memory DMA Error when Peripheral DMA Is Running with Non-Zero DEB_TRAFFIC_PERIOD */
    82. 

  82. #define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
    83. 

  83. /* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
    84. 

  84. #define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
    85. 

  85. /* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
    86. 

  86. #define ANOMALY_05000272 (1)
    87. 

  87. /* Writes to Synchronous SDRAM Memory May Be Lost */
    88. 

  88. #define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
    89. 

  89. /* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
    90. 

  90. #define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
    91. 

  91. /* Disabling Peripherals with DMA Running May Cause DMA System Instability */
    92. 

  92. #define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
    93. 

  93. /* SPI Master Boot Mode Does Not Work Well with Atmel Data Flash Devices */
    94. 

  94. #define ANOMALY_05000280 (1)
    95. 

  95. /* False Hardware Error when ISR Context Is Not Restored */
    96. 

  96. #define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
    97. 

  97. /* Memory DMA Corruption with 32-Bit Data and Traffic Control */
    98. 

  98. #define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
    99. 

  99. /* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
    100. 

  100. #define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
    101. 

  101. /* TXDWA Bit in EMAC_SYSCTL Register Is Not Functional */
    102. 

  102. #define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
    103. 

  103. /* SPORTs May Receive Bad Data If FIFOs Fill Up */
    104. 

  104. #define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
    105. 

  105. /* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
    106. 

  106. #define ANOMALY_05000301 (1)
    107. 

  107. /* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
    108. 

  108. #define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
    109. 

  109. /* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
    110. 

  110. #define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
    111. 

  111. /* SCKELOW Bit Does Not Maintain State Through Hibernate */
    112. 

  112. #define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
    113. 

  113. /* Writing UART_THR While UART Clock Is Disabled Sends Erroneous Start Bit */
    114. 

  114. #define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
    115. 

  115. /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
    116. 

  116. #define ANOMALY_05000310 (1)
    117. 

  117. /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
    118. 

  118. #define ANOMALY_05000312 (1)
    119. 

  119. /* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
    120. 

  120. #define ANOMALY_05000313 (1)
    121. 

  121. /* Killed System MMR Write Completes Erroneously on Next System MMR Access */
    122. 

  122. #define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
    123. 

  123. /* EMAC RMII Mode: Collisions Occur in Full Duplex Mode */
    124. 

  124. #define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
    125. 

  125. /* EMAC RMII Mode: TX Frames in Half Duplex Fail with Status "No Carrier" */
    126. 

  126. #define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
    127. 

  127. /* EMAC RMII Mode at 10-Base-T Speed: RX Frames Not Received Properly */
    128. 

  128. #define ANOMALY_05000322 (1)
    129. 

  129. /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
    130. 

  130. #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
    131. 

  131. /* UART Gets Disabled after UART Boot */
    132. 

  132. #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
    133. 

  133. /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
    134. 

  134. #define ANOMALY_05000355 (1)
    135. 

  135. /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
    136. 

  136. #define ANOMALY_05000357 (1)
    137. 

  137. /* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
    138. 

  138. #define ANOMALY_05000359 (1)
    139. 

  139. /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
    140. 

  140. #define ANOMALY_05000366 (1)
    141. 

  141. /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
    142. 

  142. #define ANOMALY_05000371 (1)
    143. 

  143. /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
    144. 

  144. #define ANOMALY_05000402 (__SILICON_REVISION__ == 2)
    145. 

  145. /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
    146. 

  146. #define ANOMALY_05000403 (1)
    147. 

  147. /* Speculative Fetches Can Cause Undesired External FIFO Operations */
    148. 

  148. #define ANOMALY_05000416 (1)
    149. 

  149. /* Multichannel SPORT Channel Misalignment Under Specific Configuration */
    150. 

  150. #define ANOMALY_05000425 (1)
    151. 

  151. /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
    152. 

  152. #define ANOMALY_05000426 (1)
    153. 

  153. /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
    154. 

  154. #define ANOMALY_05000443 (1)
    155. 

  155. /* False Hardware Error when RETI Points to Invalid Memory */
    156. 

  156. #define ANOMALY_05000461 (1)
    157. 

  157. /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
    158. 

  158. #define ANOMALY_05000462 (1)
    159. 

  159. /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
    160. 

  160. #define ANOMALY_05000473 (1)
    161. 

  161. /* Possible Lockup Condition when Modifying PLL from External Memory */
    162. 

  162. #define ANOMALY_05000475 (1)
    163. 

  163. /* TESTSET Instruction Cannot Be Interrupted */
    164. 

  164. #define ANOMALY_05000477 (1)
    165. 

  165. /* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
    166. 

  166. #define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
    167. 

  167. /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
    168. 

  168. #define ANOMALY_05000481 (1)
    169. 

  169. /* PLL May Latch Incorrect Values Coming Out of Reset */
    170. 

  170. #define ANOMALY_05000489 (1)
    171. 

  171. /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
    172. 

  172. #define ANOMALY_05000491 (1)
    173. 

  173. /* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
    174. 

  174. #define ANOMALY_05000494 (1)
    175. 

  175. /* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
    176. 

  176. #define ANOMALY_05000501 (1)
    177. 

  177. 

  178. /*
    179. 

  179.  * These anomalies have been "phased" out of analog.com anomaly sheets and are
    180. 

  180.  * here to show running on older silicon just isn't feasible.
    181. 

  181.  */
    182. 

  182. 

  183. /* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
    184. 

  184. #define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
    185. 

  185. /* Instruction Cache Is Not Functional */
    186. 

  186. #define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
    187. 

  187. /* Buffered CLKIN Output Is Disabled by Default */
    188. 

  188. #define ANOMALY_05000247 (__SILICON_REVISION__ < 2)
    189. 

  189. 

  190. /* Anomalies that don't exist on this proc */
    191. 

  191. #define ANOMALY_05000099 (0)
    192. 

  192. #define ANOMALY_05000120 (0)
    193. 

  193. #define ANOMALY_05000125 (0)
    194. 

  194. #define ANOMALY_05000149 (0)
    195. 

  195. #define ANOMALY_05000158 (0)
    196. 

  196. #define ANOMALY_05000171 (0)
    197. 

  197. #define ANOMALY_05000179 (0)
    198. 

  198. #define ANOMALY_05000182 (0)
    199. 

  199. #define ANOMALY_05000183 (0)
    200. 

  200. #define ANOMALY_05000189 (0)
    201. 

  201. #define ANOMALY_05000198 (0)
    202. 

  202. #define ANOMALY_05000202 (0)
    203. 

  203. #define ANOMALY_05000215 (0)
    204. 

  204. #define ANOMALY_05000219 (0)
    205. 

  205. #define ANOMALY_05000220 (0)
    206. 

  206. #define ANOMALY_05000227 (0)
    207. 

  207. #define ANOMALY_05000230 (0)
    208. 

  208. #define ANOMALY_05000231 (0)
    209. 

  209. #define ANOMALY_05000233 (0)
    210. 

  210. #define ANOMALY_05000234 (0)
    211. 

  211. #define ANOMALY_05000242 (0)
    212. 

  212. #define ANOMALY_05000248 (0)
    213. 

  213. #define ANOMALY_05000266 (0)
    214. 

  214. #define ANOMALY_05000274 (0)
    215. 

  215. #define ANOMALY_05000287 (0)
    216. 

  216. #define ANOMALY_05000311 (0)
    217. 

  217. #define ANOMALY_05000323 (0)
    218. 

  218. #define ANOMALY_05000353 (1)
    219. 

  219. #define ANOMALY_05000362 (1)
    220. 

  220. #define ANOMALY_05000363 (0)
    221. 

  221. #define ANOMALY_05000364 (0)
    222. 

  222. #define ANOMALY_05000380 (0)
    223. 

  223. #define ANOMALY_05000383 (0)
    224. 

  224. #define ANOMALY_05000386 (1)
    225. 

  225. #define ANOMALY_05000389 (0)
    226. 

  226. #define ANOMALY_05000400 (0)
    227. 

  227. #define ANOMALY_05000412 (0)
    228. 

  228. #define ANOMALY_05000430 (0)
    229. 

  229. #define ANOMALY_05000432 (0)
    230. 

  230. #define ANOMALY_05000435 (0)
    231. 

  231. #define ANOMALY_05000440 (0)
    232. 

  232. #define ANOMALY_05000447 (0)
    233. 

  233. #define ANOMALY_05000448 (0)
    234. 

  234. #define ANOMALY_05000456 (0)
    235. 

  235. #define ANOMALY_05000450 (0)
    236. 

  236. #define ANOMALY_05000465 (0)
    237. 

  237. #define ANOMALY_05000467 (0)
    238. 

  238. #define ANOMALY_05000474 (0)
    239. 

  239. #define ANOMALY_05000485 (0)
    240. 

  240. 

  241. #endif
    242. 

  242.