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/src/orion/SIM_time.c

https://gitlab.com/pranith/macsim
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  1. /*-------------------------------------------------------------------------

    2. 

  2.  *                             ORION 2.0 

    3. 

  3.  *

    4. 

  4.  *         					Copyright 2009 

    5. 

  5.  *  	Princeton University, and Regents of the University of California 

    6. 

  6.  *                         All Rights Reserved

    7. 

  7.  *

    8. 

  8.  *                         

    9. 

  9.  *  ORION 2.0 was developed by Bin Li at Princeton University and Kambiz Samadi at

    10. 

  10.  *  University of California, San Diego. ORION 2.0 was built on top of ORION 1.0. 

    11. 

  11.  *  ORION 1.0 was developed by Hangsheng Wang, Xinping Zhu and Xuning Chen at 

    12. 

  12.  *  Princeton University.

    13. 

  13.  *

    14. 

  14.  *  If your use of this software contributes to a published paper, we

    15. 

  15.  *  request that you cite our paper that appears on our website 

    16. 

  16.  *  http://www.princeton.edu/~peh/orion.html

    17. 

  17.  *

    18. 

  18.  *  Permission to use, copy, and modify this software and its documentation is

    19. 

  19.  *  granted only under the following terms and conditions.  Both the

    20. 

  20.  *  above copyright notice and this permission notice must appear in all copies

    21. 

  21.  *  of the software, derivative works or modified versions, and any portions

    22. 

  22.  *  thereof, and both notices must appear in supporting documentation.

    23. 

  23.  *

    24. 

  24.  *  This software may be distributed (but not offered for sale or transferred

    25. 

  25.  *  for compensation) to third parties, provided such third parties agree to

    26. 

  26.  *  abide by the terms and conditions of this notice.

    27. 

  27.  *

    28. 

  28.  *  This software is distributed in the hope that it will be useful to the

    29. 

  29.  *  community, but WITHOUT ANY WARRANTY; without even the implied warranty of

    30. 

  30.  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  

    31. 

  31.  *

    32. 

  32.  *-----------------------------------------------------------------------*/

    33. 

  33. 

    34. 

  34. /*------------------------------------------------------------

    35. 

  35.  *  Copyright 1994 Digital Equipment Corporation and Steve Wilton

    36. 

  36.  *                         All Rights Reserved

    37. 

  37.  *

    38. 

  38.  * Permission to use, copy, and modify this software and its documentation is

    39. 

  39.  * hereby granted only under the following terms and conditions.  Both the

    40. 

  40.  * above copyright notice and this permission notice must appear in all copies

    41. 

  41.  * of the software, derivative works or modified versions, and any portions

    42. 

  42.  * thereof, and both notices must appear in supporting documentation.

    43. 

  43.  *

    44. 

  44.  * Users of this software agree to the terms and conditions set forth herein,

    45. 

  45.  * and hereby grant back to Digital a non-exclusive, unrestricted, royalty-

    46. 

  46.  * free right and license under any changes, enhancements or extensions

    47. 

  47.  * made to the core functions of the software, including but not limited to

    48. 

  48.  * those affording compatibility with other hardware or software

    49. 

  49.  * environments, but excluding applications which incorporate this software.

    50. 

  50.  * Users further agree to use their best efforts to return to Digital any

    51. 

  51.  * such changes, enhancements or extensions that they make and inform Digital

    52. 

  52.  * of noteworthy uses of this software.  Correspondence should be provided

    53. 

  53.  * to Digital at:

    54. 

  54.  *

    55. 

  55.  *                       Director of Licensing

    56. 

  56.  *                       Western Research Laboratory

    57. 

  57.  *                       Digital Equipment Corporation

    58. 

  58.  *                       100 Hamilton Avenue

    59. 

  59.  *                       Palo Alto, California  94301

    60. 

  60.  *

    61. 

  61.  * This software may be distributed (but not offered for sale or transferred

    62. 

  62.  * for compensation) to third parties, provided such third parties agree to

    63. 

  63.  * abide by the terms and conditions of this notice.

    64. 

  64.  *

    65. 

  65.  * THE SOFTWARE IS PROVIDED "AS IS" AND DIGITAL EQUIPMENT CORP. DISCLAIMS ALL

    66. 

  66.  * WARRANTIES WITH REGARD TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES

    67. 

  67.  * OF MERCHANTABILITY AND FITNESS.   IN NO EVENT SHALL DIGITAL EQUIPMENT

    68. 

  68.  * CORPORATION BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL

    69. 

  69.  * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR

    70. 

  70.  * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS

    71. 

  71.  * ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS

    72. 

  72.  * SOFTWARE.

    73. 

  73.  *------------------------------------------------------------*/

    74. 

  74. 

    75. 

  75. #include <math.h>

    76. 

  76. #include <assert.h>

    77. 

  77. #include <stdio.h>

    78. 

  78. 

    79. 

  79. #include "SIM_parameter.h"

    80. 

  80. #include "SIM_time.h"

    81. 

  81. #include "SIM_array.h"

    82. 

  82. 

    83. 

  83. static double logtwo(double x)

    84. 

  84. {

    85. 

  85. 	assert(x > 0);

    86. 

  86. 	return log10(x)/log10(2);

    87. 

  87. }

    88. 

  88. 

    89. 

  89. 

    90. 

  90. /*----------------------------------------------------------------------*/

    91. 

  91. 

    92. 

  92. /*

    93. 

  93.  * width - gate width in um (length is Leff)   

    94. 

  94.  * wirelength - poly wire length going to gate in lambda

    95. 

  95.  * return gate capacitance in Farads 

    96. 

  96.  */

    97. 

  97. double SIM_gatecap(double width,double wirelength)

    98. 

  98. {

    99. 

  99. 

    100. 

  100. 	double overlapCap;

    101. 

  101. 	double gateCap;

    102. 

  102. 	double l = 0.1525;

    103. 

  103. 

    104. 

  104. #if defined(Pdelta_w)

    105. 

  105. 	overlapCap = (width - 2*Pdelta_w) * PCov;

    106. 

  106. 	gateCap  = ((width - 2*Pdelta_w) * (l * LSCALE - 2*Pdelta_l) *

    107. 

  107. 			PCg) + 2.0 * overlapCap;

    108. 

  108. 

    109. 

  109. 	return gateCap;

    110. 

  110. #endif

    111. 

  111. 	return(width*Leff*PARM(Cgate)*SCALE_T+wirelength*Cpolywire*Leff * SCALE_T);

    112. 

  112. 	/* return(width*Leff*PARM(Cgate)); */

    113. 

  113. 	/* return(width*CgateLeff+wirelength*Cpolywire*Leff);*/

    114. 

  114. }

    115. 

  115. 

    116. 

  116. /*

    117. 

  117.  * width - gate width in um (length is Leff)   

    118. 

  118.  * wirelength - poly wire length going to gate in lambda

    119. 

  119.  *

    120. 

  120.  * return gate capacitance in Farads 

    121. 

  121.  */

    122. 

  122. double SIM_gatecappass(double width, double wirelength)

    123. 

  123. {

    124. 

  124. 	return(SIM_gatecap(width,wirelength));

    125. 

  125. 	/* return(width*Leff*PARM(Cgatepass)+wirelength*Cpolywire*Leff); */

    126. 

  126. }

    127. 

  127. 

    128. 

  128. 

    129. 

  129. /*----------------------------------------------------------------------*/

    130. 

  130. 

    131. 

  131. /* Routine for calculating drain capacitances.  The draincap routine

    132. 

  132.  * folds transistors larger than 10um */

    133. 

  133. /*

    134. 

  134.  * width - um   

    135. 

  135.  * nchannel - whether n or p-channel (boolean)

    136. 

  136.  * stack - number of transistors in series that are on

    137. 

  137.  *

    138. 

  138.  * return drain cap in Farads 

    139. 

  139.  */

    140. 

  140. double SIM_draincap(double width, int nchannel, int stack)

    141. 

  141. {

    142. 

  142. 	double Cdiffside,Cdiffarea,Coverlap,cap;

    143. 

  143. 

    144. 

  144. 	double overlapCap;

    145. 

  145. 	double swAreaUnderGate;

    146. 

  146. 	double area_peri;

    147. 

  147. 	double diffArea;

    148. 

  148. 	double diffPeri;

    149. 

  149. 	double l = 0.4 * LSCALE;

    150. 

  150. 

    151. 

  151. 

    152. 

  152. 	diffArea = l * width;

    153. 

  153. 	diffPeri = 2 * l + 2 * width;

    154. 

  154. 

    155. 

  155. #if defined(Pdelta_w)

    156. 

  156. 	if(nchannel == 0) {

    157. 

  157. 		overlapCap = (width - 2 * Pdelta_w) * PCov;

    158. 

  158. 		swAreaUnderGate = (width - 2 * Pdelta_w) * PCjswA;

    159. 

  159. 		area_peri = ((diffArea * PCja)

    160. 

  160. 				+  (diffPeri * PCjsw));

    161. 

  161. 

    162. 

  162. 		return(stack*(area_peri + overlapCap + swAreaUnderGate));

    163. 

  163. 	}

    164. 

  164. 	else {

    165. 

  165. 		overlapCap = (width - 2 * Ndelta_w) * NCov;

    166. 

  166. 		swAreaUnderGate = (width - 2 * Ndelta_w) * NCjswA;

    167. 

  167. 		area_peri = ((diffArea * NCja * LSCALE)

    168. 

  168. 				+  (diffPeri * NCjsw * LSCALE));

    169. 

  169. 

    170. 

  170. 		return(stack*(area_peri + overlapCap + swAreaUnderGate));

    171. 

  171. 	}

    172. 

  172. #endif

    173. 

  173. 

    174. 

  174. 	Cdiffside = (nchannel) ? PARM(Cndiffside) : PARM(Cpdiffside);

    175. 

  175. 	Cdiffarea = (nchannel) ? PARM(Cndiffarea) : PARM(Cpdiffarea);

    176. 

  176. 	//Coverlap = (nchannel) ? (PARM(Cndiffovlp)+PARM(Cnoxideovlp)) :

    177. 

  177. 	//			(PARM(Cpdiffovlp)+PARM(Cpoxideovlp));

    178. 

  178. 	Coverlap = (nchannel) ? PARM(Cnoverlap) : PARM(Cpoverlap);

    179. 

  179. 	/* calculate directly-connected (non-stacked) capacitance */

    180. 

  180. 	/* then add in capacitance due to stacking */

    181. 

  181. 	if (width >= 10) {

    182. 

  182. 		cap = 3.0*Leff*width/2.0*Cdiffarea + 6.0*Leff*Cdiffside +

    183. 

  183. 			width*Coverlap; 

    184. 

  184. 		cap += (double)(stack-1)*(Leff*width*Cdiffarea +

    185. 

  185. 				4.0*Leff*Cdiffside + 2.0*width*Coverlap);

    186. 

  186. 	} else {

    187. 

  187. 		cap = 3.0*Leff*width*Cdiffarea + (6.0*Leff+width)*Cdiffside +

    188. 

  188. 			width*Coverlap;

    189. 

  189. 		cap += (double)(stack-1)*(Leff*width*Cdiffarea +

    190. 

  190. 				2.0*Leff*Cdiffside + 2.0*width*Coverlap);

    191. 

  191. 	}

    192. 

  192. 	return(cap * SCALE_T);

    193. 

  193. }

    194. 

  194. 

    195. 

  195. 

    196. 

  196. /*----------------------------------------------------------------------*/

    197. 

  197. 

    198. 

  198. /* The following routines estimate the effective resistance of an

    199. 

  199.    on transistor as described in the tech report.  The first routine

    200. 

  200.    gives the "switching" resistance, and the second gives the 

    201. 

  201.    "full-on" resistance */

    202. 

  202. /*

    203. 

  203.  * width - um   

    204. 

  204.  * nchannel - whether n or p-channel (boolean)

    205. 

  205.  * stack - number of transistors in series

    206. 

  206.  *

    207. 

  207.  * return resistance in ohms

    208. 

  208.  */

    209. 

  209. double SIM_transresswitch(double width, int nchannel, int stack)

    210. 

  210. {

    211. 

  211. 	double restrans;

    212. 

  212. 	restrans = (nchannel) ? (Rnchannelstatic):

    213. 

  213. 		(Rpchannelstatic);

    214. 

  214. 	/* calculate resistance of stack - assume all but switching trans

    215. 

  215. 	   have 0.8X the resistance since they are on throughout switching */

    216. 

  216. 	return((1.0+((stack-1.0)*0.8))*restrans/width);	

    217. 

  217. }

    218. 

  218. 

    219. 

  219. 

    220. 

  220. /*----------------------------------------------------------------------*/

    221. 

  221. /*

    222. 

  222.  * width - um   

    223. 

  223.  * nchannel - whether n or p-channel (boolean)

    224. 

  224.  * stack - number of transistors in series

    225. 

  225.  *

    226. 

  226.  * return resistance in ohms

    227. 

  227.  */

    228. 

  228. double SIM_transreson(double width, int nchannel, int stack)

    229. 

  229. {

    230. 

  230. 	double restrans;

    231. 

  231. 	restrans = (nchannel) ? Rnchannelon : Rpchannelon;

    232. 

  232. 

    233. 

  233. 	/* calculate resistance of stack.  Unlike transres, we don't

    234. 

  234. 	   multiply the stacked transistors by 0.8 */

    235. 

  235. 	return(stack*restrans/width);

    236. 

  236. }

    237. 

  237. 

    238. 

  238. 

    239. 

  239. /*----------------------------------------------------------------------*/

    240. 

  240. 

    241. 

  241. /* This routine operates in reverse: given a resistance, it finds

    242. 

  242.  * the transistor width that would have this R.  It is used in the

    243. 

  243.  * data wordline to estimate the wordline driver size. */

    244. 

  244. /*

    245. 

  245.  * res - resistance in ohms   

    246. 

  246.  * nchannel - whether n or p-channel (boolean)

    247. 

  247.  *

    248. 

  248.  * return width in um

    249. 

  249.  */

    250. 

  250. double SIM_restowidth(double res, int nchannel)

    251. 

  251. {

    252. 

  252. 	double restrans;

    253. 

  253. 

    254. 

  254. 	restrans = (nchannel) ? Rnchannelon : Rpchannelon;

    255. 

  255. 

    256. 

  256. 	return(restrans/res);

    257. 

  257. }

    258. 

  258. 

    259. 

  259. 

    260. 

  260. /*----------------------------------------------------------------------*/

    261. 

  261. /*

    262. 

  262.  * inputramptime - input rise time

    263. 

  263.  * tf - time constant of gate

    264. 

  264.  * vs1 - threshold voltages

    265. 

  265.  * vs2 - threshold voltages

    266. 

  266.  * rise - whether INPUT rise or fall (boolean)

    267. 

  267.  */

    268. 

  268. double SIM_horowitz(double inputramptime, double tf, double vs1, double vs2, int rise)

    269. 

  269. {

    270. 

  270. 	double a,b,td;

    271. 

  271. 

    272. 

  272. 	a = inputramptime/tf;

    273. 

  273. 	if (rise==RISE) {

    274. 

  274. 		b = 0.5;

    275. 

  275. 		td = tf*sqrt(fabs( log(vs1)*log(vs1)+2*a*b*(1.0-vs1))) +

    276. 

  276. 			tf*(log(vs1)-log(vs2));

    277. 

  277. 	} else {

    278. 

  278. 		b = 0.4;

    279. 

  279. 		td = tf*sqrt(fabs( log(1.0-vs1)*log(1.0-vs1)+2*a*b*(vs1))) +

    280. 

  280. 			tf*(log(1.0-vs1)-log(1.0-vs2));

    281. 

  281. 	}

    282. 

  282. 

    283. 

  283. 	return(td);

    284. 

  284. }

    285. 

  285. 

    286. 

  286. 

    287. 

  287. 

    288. 

  288. /*======================================================================*/

    289. 

  289. 

    290. 

  290. 

    291. 

  291. 

    292. 

  292. /* 

    293. 

  293.  * This part of the code contains routines for each section as

    294. 

  294.  * described in the tech report.  See the tech report for more details

    295. 

  295.  * and explanations */

    296. 

  296. 

    297. 

  297. /*----------------------------------------------------------------------*/

    298. 

  298. 

    299. 

  299. /* Decoder delay:  (see section 6.1 of tech report) */

    300. 

  300. double SIM_decoder_delay(int C, int B, int A, int Ndwl, int Ndbl, int Nspd, int Ntwl, int Ntbl, int Ntspd, double *Tdecdrive,

    301. 

  301.              double *Tdecoder1, double *Tdecoder2, double *outrisetime)

    302. 

  302. {

    303. 

  303.         double Ceq,Req,Rwire,rows,tf,nextinputtime,vth = 0,tstep,m,a,b,c;

    304. 

  304.         int numstack;

    305. 

  305. 	double z = 0.0;

    306. 

  306. 

    307. 

  307.         /* Calculate rise time.  Consider two inverters */

    308. 

  308. 

    309. 

  309.         Ceq = SIM_draincap(Wdecdrivep,PCH,1)+SIM_draincap(Wdecdriven,NCH,1) +

    310. 

  310.               SIM_gatecap(Wdecdrivep+Wdecdriven,0.0);

    311. 

  311.         tf = Ceq*SIM_transreson(Wdecdriven,NCH,1);

    312. 

  312.         nextinputtime = SIM_horowitz(z,tf,PARM(VTHINV100x60),PARM(VTHINV100x60),FALL)/

    313. 

  313.                                   (PARM(VTHINV100x60));

    314. 

  314. 

    315. 

  315.         Ceq = SIM_draincap(Wdecdrivep,PCH,1)+SIM_draincap(Wdecdriven,NCH,1) +

    316. 

  316.               SIM_gatecap(Wdecdrivep+Wdecdriven,0.0);

    317. 

  317.         tf = Ceq*SIM_transreson(Wdecdriven,NCH,1);

    318. 

  318.         nextinputtime = SIM_horowitz(nextinputtime,tf,PARM(VTHINV100x60),PARM(VTHINV100x60),

    319. 

  319.                                RISE)/

    320. 

  320.                                   (1.0-PARM(VTHINV100x60));

    321. 

  321. 

    322. 

  322.         /* First stage: driving the decoders */

    323. 

  323. 

    324. 

  324.         rows = C/(8*B*A*Ndbl*Nspd);

    325. 

  325.         Ceq = SIM_draincap(Wdecdrivep,PCH,1)+SIM_draincap(Wdecdriven,NCH,1) +

    326. 

  326.             4*SIM_gatecap(Wdec3to8n+Wdec3to8p,10.0)*(Ndwl*Ndbl)+

    327. 

  327.             Cwordmetal*0.25*8*B*A*Ndbl*Nspd;

    328. 

  328.         Rwire = Rwordmetal*0.125*8*B*A*Ndbl*Nspd;

    329. 

  329.         tf = (Rwire + SIM_transreson(Wdecdrivep,PCH,1))*Ceq;

    330. 

  330.         *Tdecdrive = SIM_horowitz(nextinputtime,tf,PARM(VTHINV100x60),PARM(VTHNAND60x90),

    331. 

  331.                      FALL);

    332. 

  332.         nextinputtime = *Tdecdrive/PARM(VTHNAND60x90);

    333. 

  333. 

    334. 

  334.         /* second stage: driving a bunch of nor gates with a nand */

    335. 

  335. 

    336. 

  336.         numstack =

    337. 

  337.           (int)(ceil((1.0/3.0)*logtwo( (double)((double)C/(double)(B*A*Ndbl*Nspd)))));

    338. 

  338.         if (numstack==0) numstack = 1;

    339. 

  339.         if (numstack>5) numstack = 5;

    340. 

  340.         Ceq = 3*SIM_draincap(Wdec3to8p,PCH,1) +SIM_draincap(Wdec3to8n,NCH,3) +

    341. 

  341.               SIM_gatecap(WdecNORn+WdecNORp,((numstack*40)+20.0))*rows +

    342. 

  342.               Cbitmetal*rows*8;

    343. 

  343. 

    344. 

  344.         Rwire = Rbitmetal*rows*8/2;

    345. 

  345.         tf = Ceq*(Rwire+SIM_transreson(Wdec3to8n,NCH,3)); 

    346. 

  346. 

    347. 

  347.         /* we only want to charge the output to the threshold of the

    348. 

  348.            nor gate.  But the threshold depends on the number of inputs

    349. 

  349.            to the nor.  */

    350. 

  350. 

    351. 

  351.         switch(numstack) {

    352. 

  352.           case 1: vth = PARM(VTHNOR12x4x1); break;

    353. 

  353.           case 2: vth = PARM(VTHNOR12x4x2); break;

    354. 

  354.           case 3: vth = PARM(VTHNOR12x4x3); break;

    355. 

  355.           case 4: vth = PARM(VTHNOR12x4x4); break;

    356. 

  356.           case 5: vth = PARM(VTHNOR12x4x4); break;

    357. 

  357.           default: printf("error:numstack=%d\n",numstack);

    358. 

  358. 	}

    359. 

  359.         *Tdecoder1 = SIM_horowitz(nextinputtime,tf,PARM(VTHNAND60x90),vth,RISE);

    360. 

  360.         nextinputtime = *Tdecoder1/(1.0-vth);

    361. 

  361. 

    362. 

  362.         /* Final stage: driving an inverter with the nor */

    363. 

  363. 

    364. 

  364.         Req = SIM_transreson(WdecNORp,PCH,numstack);

    365. 

  365.         Ceq = (SIM_gatecap(Wdecinvn+Wdecinvp,20.0)+

    366. 

  366.               numstack*SIM_draincap(WdecNORn,NCH,1)+

    367. 

  367.                      SIM_draincap(WdecNORp,PCH,numstack));

    368. 

  368.         tf = Req*Ceq;

    369. 

  369.         *Tdecoder2 = SIM_horowitz(nextinputtime,tf,vth,PARM(VSINV),FALL);

    370. 

  370.         *outrisetime = *Tdecoder2/(PARM(VSINV));

    371. 

  371.         return(*Tdecdrive+*Tdecoder1+*Tdecoder2);

    372. 

  372. }

    373. 

  373. 

    374. 

  374. 

    375. 

  375. /*----------------------------------------------------------------------*/

    376. 

  376. 

    377. 

  377. /* Decoder delay in the tag array (see section 6.1 of tech report) */

    378. 

  378. double SIM_decoder_tag_delay(int C, int B, int A, int Ndwl, int Ndbl, int Nspd, int Ntwl, int Ntbl, int Ntspd, 

    379. 

  379.              double *Tdecdrive, double *Tdecoder1, double *Tdecoder2, double *outrisetime)

    380. 

  380. {

    381. 

  381.         double Ceq,Req,Rwire,rows,tf,nextinputtime,vth = 0,tstep,m,a,b,c;

    382. 

  382.         int numstack;

    383. 

  383. 

    384. 

  384. 

    385. 

  385.         /* Calculate rise time.  Consider two inverters */

    386. 

  386. 

    387. 

  387.         Ceq = SIM_draincap(Wdecdrivep,PCH,1)+SIM_draincap(Wdecdriven,NCH,1) +

    388. 

  388.               SIM_gatecap(Wdecdrivep+Wdecdriven,0.0);

    389. 

  389.         tf = Ceq*SIM_transreson(Wdecdriven,NCH,1);

    390. 

  390.         nextinputtime = SIM_horowitz(0.0,tf,PARM(VTHINV100x60),PARM(VTHINV100x60),FALL)/

    391. 

  391.                                   (PARM(VTHINV100x60));

    392. 

  392. 

    393. 

  393.         Ceq = SIM_draincap(Wdecdrivep,PCH,1)+SIM_draincap(Wdecdriven,NCH,1) +

    394. 

  394.               SIM_gatecap(Wdecdrivep+Wdecdriven,0.0);

    395. 

  395.         tf = Ceq*SIM_transreson(Wdecdriven,NCH,1);

    396. 

  396.         nextinputtime = SIM_horowitz(nextinputtime,tf,PARM(VTHINV100x60),PARM(VTHINV100x60),

    397. 

  397.                                RISE)/

    398. 

  398.                                   (1.0-PARM(VTHINV100x60));

    399. 

  399. 

    400. 

  400.         /* First stage: driving the decoders */

    401. 

  401. 

    402. 

  402.         rows = C/(8*B*A*Ntbl*Ntspd);

    403. 

  403.         Ceq = SIM_draincap(Wdecdrivep,PCH,1)+SIM_draincap(Wdecdriven,NCH,1) +

    404. 

  404.             4*SIM_gatecap(Wdec3to8n+Wdec3to8p,10.0)*(Ntwl*Ntbl)+

    405. 

  405.             Cwordmetal*0.25*8*B*A*Ntbl*Ntspd;

    406. 

  406.         Rwire = Rwordmetal*0.125*8*B*A*Ntbl*Ntspd;

    407. 

  407.         tf = (Rwire + SIM_transreson(Wdecdrivep,PCH,1))*Ceq;

    408. 

  408.         *Tdecdrive = SIM_horowitz(nextinputtime,tf,PARM(VTHINV100x60),PARM(VTHNAND60x90),

    409. 

  409.                      FALL);

    410. 

  410.         nextinputtime = *Tdecdrive/PARM(VTHNAND60x90);

    411. 

  411. 

    412. 

  412.         /* second stage: driving a bunch of nor gates with a nand */

    413. 

  413. 

    414. 

  414.         numstack =

    415. 

  415.           (int)(ceil((1.0/3.0)*logtwo( (double)((double)C/(double)(B*A*Ntbl*Ntspd)))));

    416. 

  416.         if (numstack==0) numstack = 1;

    417. 

  417.         if (numstack>5) numstack = 5;

    418. 

  418. 

    419. 

  419.         Ceq = 3*SIM_draincap(Wdec3to8p,PCH,1) +SIM_draincap(Wdec3to8n,NCH,3) +

    420. 

  420.               SIM_gatecap(WdecNORn+WdecNORp,((numstack*40)+20.0))*rows +

    421. 

  421.               Cbitmetal*rows*8;

    422. 

  422. 

    423. 

  423.         Rwire = Rbitmetal*rows*8/2;

    424. 

  424.         tf = Ceq*(Rwire+SIM_transreson(Wdec3to8n,NCH,3)); 

    425. 

  425. 

    426. 

  426.         /* we only want to charge the output to the threshold of the

    427. 

  427.            nor gate.  But the threshold depends on the number of inputs

    428. 

  428.            to the nor.  */

    429. 

  429. 

    430. 

  430.         switch(numstack) {

    431. 

  431.           case 1: vth = PARM(VTHNOR12x4x1); break;

    432. 

  432.           case 2: vth = PARM(VTHNOR12x4x2); break;

    433. 

  433.           case 3: vth = PARM(VTHNOR12x4x3); break;

    434. 

  434.           case 4: vth = PARM(VTHNOR12x4x4); break;

    435. 

  435.           case 5: vth = PARM(VTHNOR12x4x4); break;

    436. 

  436.           case 6: vth = PARM(VTHNOR12x4x4); break;

    437. 

  437.           default: printf("error:numstack=%d\n",numstack);

    438. 

  438. 	}

    439. 

  439.         *Tdecoder1 = SIM_horowitz(nextinputtime,tf,PARM(VTHNAND60x90),vth,RISE);

    440. 

  440.         nextinputtime = *Tdecoder1/(1.0-vth);

    441. 

  441. 

    442. 

  442.         /* Final stage: driving an inverter with the nor */

    443. 

  443. 

    444. 

  444.         Req = SIM_transreson(WdecNORp,PCH,numstack);

    445. 

  445.         Ceq = (SIM_gatecap(Wdecinvn+Wdecinvp,20.0)+

    446. 

  446.               numstack*SIM_draincap(WdecNORn,NCH,1)+

    447. 

  447.                      SIM_draincap(WdecNORp,PCH,numstack));

    448. 

  448.         tf = Req*Ceq;

    449. 

  449.         *Tdecoder2 = SIM_horowitz(nextinputtime,tf,vth,PARM(VSINV),FALL);

    450. 

  450.         *outrisetime = *Tdecoder2/(PARM(VSINV));

    451. 

  451.         return(*Tdecdrive+*Tdecoder1+*Tdecoder2);

    452. 

  452. }

    453. 

  453. 

    454. 

  454. 

    455. 

  455. /*----------------------------------------------------------------------*/

    456. 

  456. 

    457. 

  457. /* Data array wordline delay (see section 6.2 of tech report) */

    458. 

  458. double SIM_wordline_delay(int B, int A, int Ndwl, int Nspd, double inrisetime, double *outrisetime)

    459. 

  459. {

    460. 

  460. 	double Rpdrive,nextrisetime;

    461. 

  461. 	double desiredrisetime,psize,nsize;

    462. 

  462. 	double tf,nextinputtime,Ceq,Req,Rline,Cline;

    463. 

  463. 	int cols;

    464. 

  464. 	double Tworddrivedel,Twordchargedel;

    465. 

  465. 

    466. 

  466. 	cols = 8*B*A*Nspd/Ndwl;

    467. 

  467. 

    468. 

  468. 	/* Choose a transistor size that makes sense */

    469. 

  469. 	/* Use a first-order approx */

    470. 

  470. 

    471. 

  471. 	desiredrisetime = krise*log((double)(cols))/2.0;

    472. 

  472. 	Cline = (SIM_gatecappass(Wmemcella,0.0)+

    473. 

  473. 			SIM_gatecappass(Wmemcella,0.0)+

    474. 

  474. 			Cwordmetal)*cols;

    475. 

  475. 	Rpdrive = desiredrisetime/(Cline*log(PARM(VSINV))*-1.0);

    476. 

  476. 	psize = SIM_restowidth(Rpdrive,PCH);

    477. 

  477. 	if (psize > Wworddrivemax) {

    478. 

  478. 		psize = Wworddrivemax;

    479. 

  479. 	}

    480. 

  480. 

    481. 

  481. 	/* Now that we have a reasonable psize, do the rest as before */

    482. 

  482. 	/* If we keep the ratio the same as the tag wordline driver,

    483. 

  483. 	   the threshold voltage will be close to VSINV */

    484. 

  484. 

    485. 

  485. 	nsize = psize * Wdecinvn/Wdecinvp;

    486. 

  486. 

    487. 

  487. 	Ceq = SIM_draincap(Wdecinvn,NCH,1) + SIM_draincap(Wdecinvp,PCH,1) +

    488. 

  488. 		SIM_gatecap(nsize+psize,20.0);

    489. 

  489. 	tf = SIM_transreson(Wdecinvn,NCH,1)*Ceq;

    490. 

  490. 

    491. 

  491. 	Tworddrivedel = SIM_horowitz(inrisetime,tf,PARM(VSINV),PARM(VSINV),RISE);

    492. 

  492. 	nextinputtime = Tworddrivedel/(1.0-PARM(VSINV));

    493. 

  493. 

    494. 

  494. 	Cline = (SIM_gatecappass(Wmemcella,(BitWidth-2*Wmemcella)/2.0)+

    495. 

  495. 			SIM_gatecappass(Wmemcella,(BitWidth-2*Wmemcella)/2.0)+

    496. 

  496. 			Cwordmetal)*cols+

    497. 

  497. 		SIM_draincap(nsize,NCH,1) + SIM_draincap(psize,PCH,1);

    498. 

  498. 	Rline = Rwordmetal*cols/2;

    499. 

  499. 	tf = (SIM_transreson(psize,PCH,1)+Rline)*Cline;

    500. 

  500. 	Twordchargedel = SIM_horowitz(nextinputtime,tf,PARM(VSINV),PARM(VSINV),FALL);

    501. 

  501. 	*outrisetime = Twordchargedel/PARM(VSINV);

    502. 

  502. 

    503. 

  503. 	return(Tworddrivedel+Twordchargedel);

    504. 

  504. }

    505. 

  505. 

    506. 

  506. 

    507. 

  507. /*----------------------------------------------------------------------*/

    508. 

  508. 

    509. 

  509. /* Tag array wordline delay (see section 6.3 of tech report) */

    510. 

  510. double SIM_wordline_tag_delay(int C, int A, int Ntspd, int Ntwl, double inrisetime, double *outrisetime)

    511. 

  511. {

    512. 

  512. 	double tf,m,a,b,c;

    513. 

  513. 	double Cline,Rline,Ceq,nextinputtime;

    514. 

  514. 	int tagbits;

    515. 

  515. 	double Tworddrivedel,Twordchargedel;

    516. 

  516. 

    517. 

  517. 	/* number of tag bits */

    518. 

  518. 

    519. 

  519. 	tagbits = PARM(ADDRESS_BITS)+2-(int)logtwo((double)C)+(int)logtwo((double)A);

    520. 

  520. 

    521. 

  521. 	/* first stage */

    522. 

  522. 

    523. 

  523. 	Ceq = SIM_draincap(Wdecinvn,NCH,1) + SIM_draincap(Wdecinvp,PCH,1) +

    524. 

  524. 		SIM_gatecap(Wdecinvn+Wdecinvp,20.0);

    525. 

  525. 	tf = SIM_transreson(Wdecinvn,NCH,1)*Ceq;

    526. 

  526. 

    527. 

  527. 	Tworddrivedel = SIM_horowitz(inrisetime,tf,PARM(VSINV),PARM(VSINV),RISE);

    528. 

  528. 	nextinputtime = Tworddrivedel/(1.0-PARM(VSINV));

    529. 

  529. 

    530. 

  530. 	/* second stage */

    531. 

  531. 	Cline = (SIM_gatecappass(Wmemcella,(BitWidth-2*Wmemcella)/2.0)+

    532. 

  532. 			SIM_gatecappass(Wmemcella,(BitWidth-2*Wmemcella)/2.0)+

    533. 

  533. 			Cwordmetal)*tagbits*A*Ntspd/Ntwl+

    534. 

  534. 		SIM_draincap(Wdecinvn,NCH,1) + SIM_draincap(Wdecinvp,PCH,1);

    535. 

  535. 	Rline = Rwordmetal*tagbits*A*Ntspd/(2*Ntwl);

    536. 

  536. 	tf = (SIM_transreson(Wdecinvp,PCH,1)+Rline)*Cline;

    537. 

  537. 	Twordchargedel = SIM_horowitz(nextinputtime,tf,PARM(VSINV),PARM(VSINV),FALL);

    538. 

  538. 	*outrisetime = Twordchargedel/PARM(VSINV);

    539. 

  539. 	return(Tworddrivedel+Twordchargedel);

    540. 

  540. }

    541. 

  541. 

    542. 

  542. 

    543. 

  543. /*----------------------------------------------------------------------*/

    544. 

  544. 

    545. 

  545. /* Data array bitline: (see section 6.4 in tech report) */

    546. 

  546. double SIM_bitline_delay(int C, int A, int B, int Ndwl, int Ndbl, int Nspd, double inrisetime, double *outrisetime)

    547. 

  547. {

    548. 

  548.         double Tbit,Cline,Ccolmux,Rlineb,r1,r2,c1,c2,a,b,c;

    549. 

  549.         double m,tstep;

    550. 

  550.         double Cbitrow;    /* bitline capacitance due to access transistor */

    551. 

  551.         int rows,cols;

    552. 

  552. 

    553. 

  553.         Cbitrow = SIM_draincap(Wmemcella,NCH,1)/2.0; /* due to shared contact */

    554. 

  554.         rows = C/(B*A*Ndbl*Nspd);

    555. 

  555.         cols = 8*B*A*Nspd/Ndwl;

    556. 

  556.         if (Ndbl*Nspd == 1) {

    557. 

  557.            Cline = rows*(Cbitrow+Cbitmetal)+2*SIM_draincap(Wbitpreequ,PCH,1);

    558. 

  558.            Ccolmux = 2*SIM_gatecap(WsenseQ1to4,10.0);

    559. 

  559.            Rlineb = Rbitmetal*rows/2.0;

    560. 

  560.            r1 = Rlineb;

    561. 

  561. 	} else { 

    562. 

  562.            Cline = rows*(Cbitrow+Cbitmetal) + 2*SIM_draincap(Wbitpreequ,PCH,1) +

    563. 

  563.                    SIM_draincap(Wbitmuxn,NCH,1);

    564. 

  564.            Ccolmux = Nspd*Ndbl*(SIM_draincap(Wbitmuxn,NCH,1))+2*SIM_gatecap(WsenseQ1to4,10.0);

    565. 

  565.            Rlineb = Rbitmetal*rows/2.0;

    566. 

  566.            r1 = Rlineb + 

    567. 

  567.                  SIM_transreson(Wbitmuxn,NCH,1);

    568. 

  568. 	}

    569. 

  569.         r2 = SIM_transreson(Wmemcella,NCH,1) +

    570. 

  570.              SIM_transreson(Wmemcella*Wmemcellbscale,NCH,1);

    571. 

  571.         c1 = Ccolmux;

    572. 

  572.         c2 = Cline;

    573. 

  573. 

    574. 

  574. 

    575. 

  575.         tstep = (r2*c2+(r1+r2)*c1)*log((Vbitpre)/(Vbitpre-Vbitsense));

    576. 

  576. 

    577. 

  577.         /* take input rise time into account */

    578. 

  578. 

    579. 

  579.         m = Vdd/inrisetime;

    580. 

  580.         if (tstep <= (0.5*(Vdd-Vt)/m)) {

    581. 

  581.               a = m;

    582. 

  582.               b = 2*((Vdd*0.5)-Vt);

    583. 

  583.               c = -2*tstep*(Vdd-Vt)+1/m*((Vdd*0.5)-Vt)*

    584. 

  584.                   ((Vdd*0.5)-Vt);

    585. 

  585.               Tbit = (-b+sqrt(b*b-4*a*c))/(2*a);

    586. 

  586.         } else {

    587. 

  587.               Tbit = tstep + (Vdd+Vt)/(2*m) - (Vdd*0.5)/m;

    588. 

  588.         }

    589. 

  589. 

    590. 

  590.         *outrisetime = Tbit/(log((Vbitpre-Vbitsense)/Vdd));

    591. 

  591.         return(Tbit);

    592. 

  592. }

    593. 

  593. 

    594. 

  594. 

    595. 

  595. /*----------------------------------------------------------------------*/

    596. 

  596. 

    597. 

  597. /* Tag array bitline: (see section 6.4 in tech report) */

    598. 

  598. double SIM_bitline_tag_delay(int C, int A, int B, int Ntwl, int Ntbl, int Ntspd, double inrisetime, double *outrisetime)

    599. 

  599. {

    600. 

  600. 	double Tbit,Cline,Ccolmux,Rlineb,r1,r2,c1,c2,a,b,c;

    601. 

  601. 	double m,tstep;

    602. 

  602. 	double Cbitrow;    /* bitline capacitance due to access transistor */

    603. 

  603. 	int rows,cols;

    604. 

  604. 

    605. 

  605. 	Cbitrow = SIM_draincap(Wmemcella,NCH,1)/2.0; /* due to shared contact */

    606. 

  606. 	rows = C/(B*A*Ntbl*Ntspd);

    607. 

  607. 	cols = 8*B*A*Ntspd/Ntwl;

    608. 

  608. 	if (Ntbl*Ntspd == 1) {

    609. 

  609. 		Cline = rows*(Cbitrow+Cbitmetal)+2*SIM_draincap(Wbitpreequ,PCH,1);

    610. 

  610. 		Ccolmux = 2*SIM_gatecap(WsenseQ1to4,10.0);

    611. 

  611. 		Rlineb = Rbitmetal*rows/2.0;

    612. 

  612. 		r1 = Rlineb;

    613. 

  613. 	} else { 

    614. 

  614. 		Cline = rows*(Cbitrow+Cbitmetal) + 2*SIM_draincap(Wbitpreequ,PCH,1) +

    615. 

  615. 			SIM_draincap(Wbitmuxn,NCH,1);

    616. 

  616. 		Ccolmux = Ntspd*Ntbl*(SIM_draincap(Wbitmuxn,NCH,1))+2*SIM_gatecap(WsenseQ1to4,10.0);

    617. 

  617. 		Rlineb = Rbitmetal*rows/2.0;

    618. 

  618. 		r1 = Rlineb + 

    619. 

  619. 			SIM_transreson(Wbitmuxn,NCH,1);

    620. 

  620. 	}

    621. 

  621. 	r2 = SIM_transreson(Wmemcella,NCH,1) +

    622. 

  622. 		SIM_transreson(Wmemcella*Wmemcellbscale,NCH,1);

    623. 

  623. 

    624. 

  624. 	c1 = Ccolmux;

    625. 

  625. 	c2 = Cline;

    626. 

  626. 

    627. 

  627. 	tstep = (r2*c2+(r1+r2)*c1)*log((Vbitpre)/(Vbitpre-Vbitsense));

    628. 

  628. 

    629. 

  629. 	/* take into account input rise time */

    630. 

  630. 

    631. 

  631. 	m = Vdd/inrisetime;

    632. 

  632. 	if (tstep <= (0.5*(Vdd-Vt)/m)) {

    633. 

  633. 		a = m;

    634. 

  634. 		b = 2*((Vdd*0.5)-Vt);

    635. 

  635. 		c = -2*tstep*(Vdd-Vt)+1/m*((Vdd*0.5)-Vt)*

    636. 

  636. 			((Vdd*0.5)-Vt);

    637. 

  637. 		Tbit = (-b+sqrt(b*b-4*a*c))/(2*a);

    638. 

  638. 	} else {

    639. 

  639. 		Tbit = tstep + (Vdd+Vt)/(2*m) - (Vdd*0.5)/m;

    640. 

  640. 	}

    641. 

  641. 

    642. 

  642. 	*outrisetime = Tbit/(log((Vbitpre-Vbitsense)/Vdd));

    643. 

  643. 	return(Tbit);

    644. 

  644. }

    645. 

  645. 

    646. 

  646. 

    647. 

  647. /*----------------------------------------------------------------------*/

    648. 

  648. 

    649. 

  649. /* It is assumed the sense amps have a constant delay

    650. 

  650.    (see section 6.5) */

    651. 

  651. double SIM_sense_amp_delay(double inrisetime,double *outrisetime)

    652. 

  652. {

    653. 

  653. 	*outrisetime = tfalldata;

    654. 

  654. 	return(tsensedata);

    655. 

  655. }

    656. 

  656. 

    657. 

  657. 

    658. 

  658. /*--------------------------------------------------------------*/

    659. 

  659. 

    660. 

  660. double SIM_sense_amp_tag_delay(double inrisetime, double *outrisetime)

    661. 

  661. {

    662. 

  662. 	*outrisetime = tfalltag;

    663. 

  663. 	return(tsensetag);

    664. 

  664. }

    665. 

  665. 

    666. 

  666. 

    667. 

  667. /*----------------------------------------------------------------------*/

    668. 

  668. 

    669. 

  669. /* Comparator Delay (see section 6.6) */

    670. 

  670. double SIM_compare_time(int C, int A, int Ntbl, int Ntspd, double inputtime, double *outputtime)

    671. 

  671. {

    672. 

  672. 	double Req,Ceq,tf,st1del,st2del,st3del,nextinputtime,m;

    673. 

  673. 	double c1,c2,r1,r2,tstep,a,b,c;

    674. 

  674. 	double Tcomparatorni;

    675. 

  675. 	int cols,tagbits;

    676. 

  676. 

    677. 

  677. 	/* First Inverter */

    678. 

  678. 

    679. 

  679. 	Ceq = SIM_gatecap(Wcompinvn2+Wcompinvp2,10.0) +

    680. 

  680. 		SIM_draincap(Wcompinvp1,PCH,1) + SIM_draincap(Wcompinvn1,NCH,1);

    681. 

  681. 	Req = SIM_transreson(Wcompinvp1,PCH,1);

    682. 

  682. 	tf = Req*Ceq;

    683. 

  683. 	st1del = SIM_horowitz(inputtime,tf,PARM(VTHCOMPINV),PARM(VTHCOMPINV),FALL);

    684. 

  684. 	nextinputtime = st1del/PARM(VTHCOMPINV);

    685. 

  685. 

    686. 

  686. 	/* Second Inverter */

    687. 

  687. 

    688. 

  688. 	Ceq = SIM_gatecap(Wcompinvn3+Wcompinvp3,10.0) +

    689. 

  689. 		SIM_draincap(Wcompinvp2,PCH,1) + SIM_draincap(Wcompinvn2,NCH,1);

    690. 

  690. 	Req = SIM_transreson(Wcompinvn2,NCH,1);

    691. 

  691. 	tf = Req*Ceq;

    692. 

  692. 	st2del = SIM_horowitz(inputtime,tf,PARM(VTHCOMPINV),PARM(VTHCOMPINV),RISE);

    693. 

  693. 	nextinputtime = st1del/(1.0-PARM(VTHCOMPINV));

    694. 

  694. 

    695. 

  695. 	/* Third Inverter */

    696. 

  696. 

    697. 

  697. 	Ceq = SIM_gatecap(Wevalinvn+Wevalinvp,10.0) +

    698. 

  698. 		SIM_draincap(Wcompinvp3,PCH,1) + SIM_draincap(Wcompinvn3,NCH,1);

    699. 

  699. 	Req = SIM_transreson(Wcompinvp3,PCH,1);

    700. 

  700. 	tf = Req*Ceq;

    701. 

  701. 	st3del = SIM_horowitz(nextinputtime,tf,PARM(VTHCOMPINV),PARM(VTHEVALINV),FALL);

    702. 

  702. 	nextinputtime = st1del/(PARM(VTHEVALINV));

    703. 

  703. 

    704. 

  704. 	/* Final Inverter (virtual ground driver) discharging compare part */

    705. 

  705. 

    706. 

  706. 	tagbits = PARM(ADDRESS_BITS) - (int)logtwo((double)C) + (int)logtwo((double)A);

    707. 

  707. 	cols = tagbits*Ntbl*Ntspd;

    708. 

  708. 

    709. 

  709. 	r1 = SIM_transreson(Wcompn,NCH,2);

    710. 

  710. 	r2 = SIM_transresswitch(Wevalinvn,NCH,1);

    711. 

  711. 	c2 = (tagbits)*(SIM_draincap(Wcompn,NCH,1)+SIM_draincap(Wcompn,NCH,2))+

    712. 

  712. 		SIM_draincap(Wevalinvp,PCH,1) + SIM_draincap(Wevalinvn,NCH,1);

    713. 

  713. 	c1 = (tagbits)*(SIM_draincap(Wcompn,NCH,1)+SIM_draincap(Wcompn,NCH,2))

    714. 

  714. 		+SIM_draincap(Wcompp,PCH,1) + SIM_gatecap(Wmuxdrv12n+Wmuxdrv12p,20.0) +

    715. 

  715. 		cols*Cwordmetal;

    716. 

  716. 

    717. 

  717. 	/* time to go to threshold of mux driver */

    718. 

  718. 

    719. 

  719. 	tstep = (r2*c2+(r1+r2)*c1)*log(1.0/PARM(VTHMUXDRV1));

    720. 

  720. 

    721. 

  721. 	/* take into account non-zero input rise time */

    722. 

  722. 

    723. 

  723. 	m = Vdd/nextinputtime;

    724. 

  724. 

    725. 

  725. 	if ((tstep) <= (0.5*(Vdd-Vt)/m)) {

    726. 

  726. 		a = m;

    727. 

  727. 		b = 2*((Vdd*PARM(VTHEVALINV))-Vt);

    728. 

  728. 		c = -2*(tstep)*(Vdd-Vt)+1/m*((Vdd*PARM(VTHEVALINV))-Vt)*((Vdd*PARM(VTHEVALINV))-Vt);

    729. 

  729. 		Tcomparatorni = (-b+sqrt(b*b-4*a*c))/(2*a);

    730. 

  730. 	} else {

    731. 

  731. 		Tcomparatorni = (tstep) + (Vdd+Vt)/(2*m) - (Vdd*PARM(VTHEVALINV))/m;

    732. 

  732. 	}

    733. 

  733. 	*outputtime = Tcomparatorni/(1.0-PARM(VTHMUXDRV1));

    734. 

  734. 

    735. 

  735. 	return(Tcomparatorni+st1del+st2del+st3del);

    736. 

  736. }

    737. 

  737. 

    738. 

  738. 

    739. 

  739. /*----------------------------------------------------------------------*/

    740. 

  740. 

    741. 

  741. /* Delay of the multiplexor Driver (see section 6.7) */

    742. 

  742. double SIM_mux_driver_delay(int C, int B, int A, int Ndbl, int Nspd, int Ndwl, int Ntbl, int Ntspd, double inputtime, double *outputtime)

    743. 

  743. {

    744. 

  744. 	double Ceq,Req,tf,nextinputtime;

    745. 

  745. 	double Tst1,Tst2,Tst3;

    746. 

  746. 

    747. 

  747. 	/* first driver stage - Inverte "match" to produce "matchb" */

    748. 

  748. 	/* the critical path is the DESELECTED case, so consider what

    749. 

  749. 	   happens when the address bit is true, but match goes low */

    750. 

  750. 

    751. 

  751. 	Ceq = SIM_gatecap(WmuxdrvNORn+WmuxdrvNORp,15.0)*(8*B/PARM(BITOUT)) +

    752. 

  752. 		SIM_draincap(Wmuxdrv12n,NCH,1) + SIM_draincap(Wmuxdrv12p,PCH,1);

    753. 

  753. 	Req = SIM_transreson(Wmuxdrv12p,PCH,1);

    754. 

  754. 	tf = Ceq*Req;

    755. 

  755. 	Tst1 = SIM_horowitz(inputtime,tf,PARM(VTHMUXDRV1),PARM(VTHMUXDRV2),FALL);

    756. 

  756. 	nextinputtime = Tst1/PARM(VTHMUXDRV2);

    757. 

  757. 

    758. 

  758. 	/* second driver stage - NOR "matchb" with address bits to produce sel */

    759. 

  759. 

    760. 

  760. 	Ceq = SIM_gatecap(Wmuxdrv3n+Wmuxdrv3p,15.0) + 2*SIM_draincap(WmuxdrvNORn,NCH,1) +

    761. 

  761. 		SIM_draincap(WmuxdrvNORp,PCH,2);

    762. 

  762. 	Req = SIM_transreson(WmuxdrvNORn,NCH,1);

    763. 

  763. 	tf = Ceq*Req;

    764. 

  764. 	Tst2 = SIM_horowitz(nextinputtime,tf,PARM(VTHMUXDRV2),PARM(VTHMUXDRV3),RISE);

    765. 

  765. 	nextinputtime = Tst2/(1-PARM(VTHMUXDRV3));

    766. 

  766. 

    767. 

  767. 	/* third driver stage - invert "select" to produce "select bar" */

    768. 

  768. 

    769. 

  769. 	Ceq = PARM(BITOUT)*SIM_gatecap(Woutdrvseln+Woutdrvselp+Woutdrvnorn+Woutdrvnorp,20.0)+

    770. 

  770. 		SIM_draincap(Wmuxdrv3p,PCH,1) + SIM_draincap(Wmuxdrv3n,NCH,1) +

    771. 

  771. 		Cwordmetal*8*B*A*Nspd*Ndbl/2.0;

    772. 

  772. 	Req = (Rwordmetal*8*B*A*Nspd*Ndbl/2)/2 + SIM_transreson(Wmuxdrv3p,PCH,1);

    773. 

  773. 	tf = Ceq*Req;

    774. 

  774. 	Tst3 = SIM_horowitz(nextinputtime,tf,PARM(VTHMUXDRV3),PARM(VTHOUTDRINV),FALL);

    775. 

  775. 	*outputtime = Tst3/(PARM(VTHOUTDRINV));

    776. 

  776. 

    777. 

  777. 	return(Tst1 + Tst2 + Tst3);

    778. 

  778. 

    779. 

  779. }

    780. 

  780. 

    781. 

  781. 

    782. 

  782. /*----------------------------------------------------------------------*/

    783. 

  783. 

    784. 

  784. /* Valid driver (see section 6.9 of tech report)

    785. 

  785.    Note that this will only be called for a direct mapped cache */

    786. 

  786. double SIM_valid_driver_delay(int C, int A, int Ntbl, int Ntspd, double inputtime)

    787. 

  787. {

    788. 

  788. 	double Ceq,Tst1,tf;

    789. 

  789. 

    790. 

  790. 	Ceq = SIM_draincap(Wmuxdrv12n,NCH,1)+SIM_draincap(Wmuxdrv12p,PCH,1)+Cout;

    791. 

  791. 	tf = Ceq*SIM_transreson(Wmuxdrv12p,PCH,1);

    792. 

  792. 	Tst1 = SIM_horowitz(inputtime,tf,PARM(VTHMUXDRV1),0.5,FALL);

    793. 

  793. 

    794. 

  794. 	return(Tst1);

    795. 

  795. }

    796. 

  796. 

    797. 

  797. 

    798. 

  798. /*----------------------------------------------------------------------*/

    799. 

  799. 

    800. 

  800. /* Data output delay (data side) -- see section 6.8

    801. 

  801.    This is the time through the NAND/NOR gate and the final inverter 

    802. 

  802.    assuming sel is already present */

    803. 

  803. double SIM_dataoutput_delay(int C, int B, int A, int Ndbl, int Nspd, int Ndwl,

    804. 

  804.               double inrisetime, double *outrisetime)

    805. 

  805. {

    806. 

  806. 	double Ceq,Rwire,Rline;

    807. 

  807. 	double aspectRatio;     /* as height over width */

    808. 

  808. 	double ramBlocks;       /* number of RAM blocks */

    809. 

  809. 	double tf;

    810. 

  810. 	double nordel,outdel,nextinputtime;       

    811. 

  811. 	double hstack,vstack;

    812. 

  812. 

    813. 

  813. 	/* calculate some layout info */

    814. 

  814. 

    815. 

  815. 	aspectRatio = (2.0*C)/(8.0*B*B*A*A*Ndbl*Ndbl*Nspd*Nspd);

    816. 

  816. 	hstack = (aspectRatio > 1.0) ? aspectRatio : 1.0/aspectRatio;

    817. 

  817. 	ramBlocks = Ndwl*Ndbl;

    818. 

  818. 	hstack = hstack * sqrt(ramBlocks/ hstack);

    819. 

  819. 	vstack = ramBlocks/ hstack;

    820. 

  820. 

    821. 

  821. 	/* Delay of NOR gate */

    822. 

  822. 

    823. 

  823. 	Ceq = 2*SIM_draincap(Woutdrvnorn,NCH,1)+SIM_draincap(Woutdrvnorp,PCH,2)+

    824. 

  824. 		SIM_gatecap(Woutdrivern,10.0);

    825. 

  825. 	tf = Ceq*SIM_transreson(Woutdrvnorp,PCH,2);

    826. 

  826. 	nordel = SIM_horowitz(inrisetime,tf,PARM(VTHOUTDRNOR),PARM(VTHOUTDRIVE),FALL);

    827. 

  827. 	nextinputtime = nordel/(PARM(VTHOUTDRIVE));

    828. 

  828. 

    829. 

  829. 	/* Delay of final output driver */

    830. 

  830. 

    831. 

  831. 	Ceq = (SIM_draincap(Woutdrivern,NCH,1)+SIM_draincap(Woutdriverp,PCH,1))*

    832. 

  832. 		((8*B*A)/PARM(BITOUT)) +

    833. 

  833. 		Cwordmetal*(8*B*A*Nspd* (vstack)) + Cout;

    834. 

  834. 	Rwire = Rwordmetal*(8*B*A*Nspd* (vstack))/2;

    835. 

  835. 

    836. 

  836. 	tf = Ceq*(SIM_transreson(Woutdriverp,PCH,1)+Rwire);

    837. 

  837. 	outdel = SIM_horowitz(nextinputtime,tf,PARM(VTHOUTDRIVE),0.5,RISE);

    838. 

  838. 	*outrisetime = outdel/0.5;

    839. 

  839. 	return(outdel+nordel);

    840. 

  840. }

    841. 

  841. 

    842. 

  842. 

    843. 

  843. /*----------------------------------------------------------------------*/

    844. 

  844. 

    845. 

  845. /* Sel inverter delay (part of the output driver)  see section 6.8 */

    846. 

  846. double SIM_selb_delay_tag_path(double inrisetime, double *outrisetime)

    847. 

  847. {

    848. 

  848. 	double Ceq,Tst1,tf;

    849. 

  849. 

    850. 

  850. 	Ceq = SIM_draincap(Woutdrvseln,NCH,1)+SIM_draincap(Woutdrvselp,PCH,1)+

    851. 

  851. 		SIM_gatecap(Woutdrvnandn+Woutdrvnandp,10.0);

    852. 

  852. 	tf = Ceq*SIM_transreson(Woutdrvseln,NCH,1);

    853. 

  853. 	Tst1 = SIM_horowitz(inrisetime,tf,PARM(VTHOUTDRINV),PARM(VTHOUTDRNAND),RISE);

    854. 

  854. 	*outrisetime = Tst1/(1.0-PARM(VTHOUTDRNAND));

    855. 

  855. 

    856. 

  856. 	return(Tst1);

    857. 

  857. }

    858. 

  858. 

    859. 

  859. 

    860. 

  860. /*----------------------------------------------------------------------*/

    861. 

  861. 

    862. 

  862. /* This routine calculates the extra time required after an access before

    863. 

  863.  * the next access can occur [ie.  it returns (cycle time-access time)].

    864. 

  864.  */

    865. 

  865. double SIM_precharge_delay(double worddata)

    866. 

  866. {

    867. 

  867. 	double Ceq,tf,pretime;

    868. 

  868. 

    869. 

  869. 	/* as discussed in the tech report, the delay is the delay of

    870. 

  870. 	   4 inverter delays (each with fanout of 4) plus the delay of

    871. 

  871. 	   the wordline */

    872. 

  872. 

    873. 

  873. 	Ceq = SIM_draincap(Wdecinvn,NCH,1)+SIM_draincap(Wdecinvp,PCH,1)+

    874. 

  874. 		4*SIM_gatecap(Wdecinvn+Wdecinvp,0.0);

    875. 

  875. 	tf = Ceq*SIM_transreson(Wdecinvn,NCH,1);

    876. 

  876. 	pretime = 4*SIM_horowitz(0.0,tf,0.5,0.5,RISE) + worddata;

    877. 

  877. 

    878. 

  878. 	return(pretime);

    879. 

  879. }

    880. 

  880. 

    881. 

  881. 

    882. 

  882. /*======================================================================*/

    883. 

  883. 

    884. 

  884. 

    885. 

  885. /* returns 1 if the parameters make up a valid organization */

    886. 

  886. /* Layout concerns drive any restrictions you might add here */

    887. 

  887. int SIM_organizational_parameters_valid(int rows, int cols, int Ndwl, int Ndbl, int Nspd, int Ntwl, int Ntbl, int Ntspd)

    888. 

  888. {

    889. 

  889. 	/* don't want more than 8 subarrays for each of data/tag */

    890. 

  890. 

    891. 

  891. 	if (Ndwl*Ndbl>PARM(MAXSUBARRAYS)) return(0);

    892. 

  892. 	if (Ntwl*Ntbl>PARM(MAXSUBARRAYS)) return(0);

    893. 

  893. 

    894. 

  894. 	/* add more constraints here as necessary */

    895. 

  895. 

    896. 

  896. 	return(1);

    897. 

  897. }

    898. 

  898. 

    899. 

  899. 

    900. 

  900. /*----------------------------------------------------------------------*/

    901. 

  901. 

    902. 

  902. 

    903. 

  903. void SIM_calculate_time(time_result_type *result, time_parameter_type *parameters)

    904. 

  904. {

    905. 

  905. 	int Ndwl,Ndbl,Nspd,Ntwl,Ntbl,Ntspd,rows,columns,tag_driver_size1,tag_driver_size2;

    906. 

  906. 	double access_time;

    907. 

  907. 	double before_mux,after_mux;

    908. 

  908. 	double decoder_data_driver,decoder_data_3to8,decoder_data_inv;

    909. 

  909. 	double decoder_data,decoder_tag,wordline_data,wordline_tag;

    910. 

  910. 	double decoder_tag_driver,decoder_tag_3to8,decoder_tag_inv;

    911. 

  911. 	double bitline_data,bitline_tag,sense_amp_data,sense_amp_tag;

    912. 

  912. 	double compare_tag,mux_driver,data_output,selb = 0;

    913. 

  913. 	double time_till_compare,time_till_select,driver_cap,valid_driver;

    914. 

  914. 	double cycle_time, precharge_del;

    915. 

  915. 	double outrisetime,inrisetime;   

    916. 

  916. 

    917. 

  917. 	rows = parameters->number_of_sets;

    918. 

  918. 	columns = 8*parameters->block_size*parameters->associativity;

    919. 

  919. 

    920. 

  920. 	/* go through possible Ndbl,Ndwl and find the smallest */

    921. 

  921. 	/* Because of area considerations, I don't think it makes sense

    922. 

  922. 	   to break either dimension up larger than MAXN */

    923. 

  923. 

    924. 

  924. 	result->cycle_time = BIGNUM;

    925. 

  925. 	result->access_time = BIGNUM;

    926. 

  926. 	for (Nspd=1;Nspd<=PARM(MAXSPD);Nspd=Nspd*2) {

    927. 

  927. 		for (Ndwl=1;Ndwl<=PARM(MAXN);Ndwl=Ndwl*2) {

    928. 

  928. 			for (Ndbl=1;Ndbl<=PARM(MAXN);Ndbl=Ndbl*2) {

    929. 

  929. 				for (Ntspd=1;Ntspd<=PARM(MAXSPD);Ntspd=Ntspd*2) {

    930. 

  930. 					for (Ntwl=1;Ntwl<=1;Ntwl=Ntwl*2) {

    931. 

  931. 						for (Ntbl=1;Ntbl<=PARM(MAXN);Ntbl=Ntbl*2) {

    932. 

  932. 

    933. 

  933. 							if (SIM_organizational_parameters_valid

    934. 

  934. 									(rows,columns,Ndwl,Ndbl,Nspd,Ntwl,Ntbl,Ntspd)) {

    935. 

  935. 

    936. 

  936. 

    937. 

  937. 								/* Calculate data side of cache */

    938. 

  938. 

    939. 

  939. 

    940. 

  940. 								decoder_data = SIM_decoder_delay(parameters->cache_size,parameters->block_size,

    941. 

  941. 										parameters->associativity,Ndwl,Ndbl,Nspd,Ntwl,Ntbl,Ntspd,

    942. 

  942. 										&decoder_data_driver,&decoder_data_3to8,

    943. 

  943. 										&decoder_data_inv,&outrisetime);

    944. 

  944. 

    945. 

  945. 

    946. 

  946. 								inrisetime = outrisetime;

    947. 

  947. 								wordline_data = SIM_wordline_delay(parameters->block_size,

    948. 

  948. 										parameters->associativity,Ndwl,Nspd,

    949. 

  949. 										inrisetime,&outrisetime);

    950. 

  950. 

    951. 

  951. 								inrisetime = outrisetime;

    952. 

  952. 								bitline_data = SIM_bitline_delay(parameters->cache_size,parameters->associativity,

    953. 

  953. 										parameters->block_size,Ndwl,Ndbl,Nspd,

    954. 

  954. 										inrisetime,&outrisetime);

    955. 

  955. 								inrisetime = outrisetime;

    956. 

  956. 								sense_amp_data = SIM_sense_amp_delay(inrisetime,&outrisetime);

    957. 

  957. 								inrisetime = outrisetime;

    958. 

  958. 								data_output = SIM_dataoutput_delay(parameters->cache_size,parameters->block_size,

    959. 

  959. 										parameters->associativity,Ndbl,Nspd,Ndwl,

    960. 

  960. 										inrisetime,&outrisetime);

    961. 

  961. 								inrisetime = outrisetime;

    962. 

  962. 

    963. 

  963. 

    964. 

  964. 								/* if the associativity is 1, the data output can come right

    965. 

  965. 								   after the sense amp.   Otherwise, it has to wait until 

    966. 

  966. 								   the data access has been done. */

    967. 

  967. 

    968. 

  968. 								if (parameters->associativity==1) {

    969. 

  969. 									before_mux = decoder_data + wordline_data + bitline_data +

    970. 

  970. 										sense_amp_data + data_output;

    971. 

  971. 									after_mux = 0;

    972. 

  972. 								} else {   

    973. 

  973. 									before_mux = decoder_data + wordline_data + bitline_data +

    974. 

  974. 										sense_amp_data;

    975. 

  975. 									after_mux = data_output;

    976. 

  976. 								}

    977. 

  977. 

    978. 

  978. 

    979. 

  979. 								/*

    980. 

  980. 								 * Now worry about the tag side.

    981. 

  981. 								 */

    982. 

  982. 

    983. 

  983. 

    984. 

  984. 								decoder_tag = SIM_decoder_tag_delay(parameters->cache_size,

    985. 

  985. 										parameters->block_size,parameters->associativity,

    986. 

  986. 										Ndwl,Ndbl,Nspd,Ntwl,Ntbl,Ntspd,

    987. 

  987. 										&decoder_tag_driver,&decoder_tag_3to8,

    988. 

  988. 										&decoder_tag_inv,&outrisetime);

    989. 

  989. 								inrisetime = outrisetime;

    990. 

  990. 

    991. 

  991. 								wordline_tag = SIM_wordline_tag_delay(parameters->cache_size,

    992. 

  992. 										parameters->associativity,Ntspd,Ntwl,

    993. 

  993. 										inrisetime,&outrisetime);

    994. 

  994. 								inrisetime = outrisetime;

    995. 

  995. 

    996. 

  996. 								bitline_tag = SIM_bitline_tag_delay(parameters->cache_size,parameters->associativity,

    997. 

  997. 										parameters->block_size,Ntwl,Ntbl,Ntspd,

    998. 

  998. 										inrisetime,&outrisetime);

    999. 

  999. 								inrisetime = outrisetime;

    1000. 

  1000. 

    1001. 

  1001. 								sense_amp_tag = SIM_sense_amp_tag_delay(inrisetime,&outrisetime);

    1002. 

  1002. 								inrisetime = outrisetime;

    1003. 

  1003. 

    1004. 

  1004. 								compare_tag = SIM_compare_time(parameters->cache_size,parameters->associativity,

    1005. 

  1005. 										Ntbl,Ntspd,

    1006. 

  1006. 										inrisetime,&outrisetime);

    1007. 

  1007. 								inrisetime = outrisetime;

    1008. 

  1008. 

    1009. 

  1009. 								if (parameters->associativity == 1) {

    1010. 

  1010. 									mux_driver = 0;

    1011. 

  1011. 									valid_driver = SIM_valid_driver_delay(parameters->cache_size,

    1012. 

  1012. 											parameters->associativity,Ntbl,Ntspd,inrisetime);

    1013. 

  1013. 									time_till_compare = decoder_tag + wordline_tag + bitline_tag +

    1014. 

  1014. 										sense_amp_tag;

    1015. 

  1015. 

    1016. 

  1016. 									time_till_select = time_till_compare+ compare_tag + valid_driver;

    1017. 

  1017. 

    1018. 

  1018. 

    1019. 

  1019. 									/*

    1020. 

  1020. 									 * From the above info, calculate the total access time

    1021. 

  1021. 									 */

    1022. 

  1022. 

    1023. 

  1023. 									access_time = MAX(before_mux+after_mux,time_till_select);

    1024. 

  1024. 

    1025. 

  1025. 

    1026. 

  1026. 								} else {

    1027. 

  1027. 									mux_driver = SIM_mux_driver_delay(parameters->cache_size,parameters->block_size,

    1028. 

  1028. 											parameters->associativity,Ndbl,Nspd,Ndwl,Ntbl,Ntspd,

    1029. 

  1029. 											inrisetime,&outrisetime);

    1030. 

  1030. 

    1031. 

  1031. 									selb = SIM_selb_delay_tag_path(inrisetime,&outrisetime);

    1032. 

  1032. 

    1033. 

  1033. 									valid_driver = 0;

    1034. 

  1034. 

    1035. 

  1035. 									time_till_compare = decoder_tag + wordline_tag + bitline_tag +

    1036. 

  1036. 										sense_amp_tag;

    1037. 

  1037. 

    1038. 

  1038. 									time_till_select = time_till_compare+ compare_tag + mux_driver

    1039. 

  1039. 										+ selb;

    1040. 

  1040. 

    1041. 

  1041. 									access_time = MAX(before_mux,time_till_select) +after_mux;

    1042. 

  1042. 								}

    1043. 

  1043. 

    1044. 

  1044. 								/*

    1045. 

  1045. 								 * Calcuate the cycle time

    1046. 

  1046. 								 */

    1047. 

  1047. 

    1048. 

  1048. 								precharge_del = SIM_precharge_delay(wordline_data);

    1049. 

  1049. 

    1050. 

  1050. 								cycle_time = access_time + precharge_del;

    1051. 

  1051. 

    1052. 

  1052. 								/*

    1053. 

  1053. 								 * The parameters are for a 0.8um process.  A quick way to

    1054. 

  1054. 								 * scale the results to another process is to divide all

    1055. 

  1055. 								 * the results by FUDGEFACTOR.  Normally, FUDGEFACTOR is 1.

    1056. 

  1056. 								 */

    1057. 

  1057. 

    1058. 

  1058. 								if (result->cycle_time+1e-11*(result->best_Ndwl+result->best_Ndbl+result->best_Nspd+result->best_Ntwl+result->best_Ntbl+result->best_Ntspd) > cycle_time/PARM(FUDGEFACTOR)+1e-11*(Ndwl+Ndbl+Nspd+Ntwl+Ntbl+Ntspd)) {

    1059. 

  1059. 									result->cycle_time = cycle_time/PARM(FUDGEFACTOR);

    1060. 

  1060. 									result->access_time = access_time/PARM(FUDGEFACTOR);

    1061. 

  1061. 									result->best_Ndwl = Ndwl;

    1062. 

  1062. 									result->best_Ndbl = Ndbl;

    1063. 

  1063. 									result->best_Nspd = Nspd;

    1064. 

  1064. 									result->best_Ntwl = Ntwl;

    1065. 

  1065. 									result->best_Ntbl = Ntbl;

    1066. 

  1066. 									result->best_Ntspd = Ntspd;

    1067. 

  1067. 									result->decoder_delay_data = decoder_data/PARM(FUDGEFACTOR);

    1068. 

  1068. 									result->decoder_delay_tag = decoder_tag/PARM(FUDGEFACTOR);

    1069. 

  1069. 									result->dec_tag_driver = decoder_tag_driver/PARM(FUDGEFACTOR);

    1070. 

  1070. 									result->dec_tag_3to8 = decoder_tag_3to8/PARM(FUDGEFACTOR);

    1071. 

  1071. 									result->dec_tag_inv = decoder_tag_inv/PARM(FUDGEFACTOR);

    1072. 

  1072. 									result->dec_data_driver = decoder_data_driver/PARM(FUDGEFACTOR);

    1073. 

  1073. 									result->dec_data_3to8 = decoder_data_3to8/PARM(FUDGEFACTOR);

    1074. 

  1074. 									result->dec_data_inv = decoder_data_inv/PARM(FUDGEFACTOR);

    1075. 

  1075. 									result->wordline_delay_data = wordline_data/PARM(FUDGEFACTOR);

    1076. 

  1076. 									result->wordline_delay_tag = wordline_tag/PARM(FUDGEFACTOR);

    1077. 

  1077. 									result->bitline_delay_data = bitline_data/PARM(FUDGEFACTOR);

    1078. 

  1078. 									result->bitline_delay_tag = bitline_tag/PARM(FUDGEFACTOR);

    1079. 

  1079. 									result->sense_amp_delay_data = sense_amp_data/PARM(FUDGEFACTOR);

    1080. 

  1080. 									result->sense_amp_delay_tag = sense_amp_tag/PARM(FUDGEFACTOR);

    1081. 

  1081. 									result->compare_part_delay = compare_tag/PARM(FUDGEFACTOR);

    1082. 

  1082. 									result->drive_mux_delay = mux_driver/PARM(FUDGEFACTOR);

    1083. 

  1083. 									result->selb_delay = selb/PARM(FUDGEFACTOR);

    1084. 

  1084. 									result->drive_valid_delay = valid_driver/PARM(FUDGEFACTOR);

    1085. 

  1085. 									result->data_output_delay = data_output/PARM(FUDGEFACTOR);

    1086. 

  1086. 									result->precharge_delay = precharge_del/PARM(FUDGEFACTOR);

    1087. 

  1087. 								}

    1088. 

  1088. 							}

    1089. 

  1089. 						}

    1090. 

  1090. 					}

    1091. 

  1091. 				}

    1092. 

  1092. 			}

    1093. 

  1093. 		}

    1094. 

  1094. 	}

    1095. 

  1095. }

    1096. 

  1096.