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/drivers/gpu/drm/arm/malidp_planes.c

https://gitlab.com/CadeLaRen/linux
C | 298 lines | 224 code | 54 blank | 20 comment | 35 complexity | 9c3fa513637ffba186a32e91ab07bf71 MD5 | raw file
  1. /*
  2. * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
  3. * Author: Liviu Dudau <Liviu.Dudau@arm.com>
  4. *
  5. * This program is free software and is provided to you under the terms of the
  6. * GNU General Public License version 2 as published by the Free Software
  7. * Foundation, and any use by you of this program is subject to the terms
  8. * of such GNU licence.
  9. *
  10. * ARM Mali DP plane manipulation routines.
  11. */
  12. #include <drm/drmP.h>
  13. #include <drm/drm_atomic_helper.h>
  14. #include <drm/drm_fb_cma_helper.h>
  15. #include <drm/drm_gem_cma_helper.h>
  16. #include <drm/drm_plane_helper.h>
  17. #include "malidp_hw.h"
  18. #include "malidp_drv.h"
  19. /* Layer specific register offsets */
  20. #define MALIDP_LAYER_FORMAT 0x000
  21. #define MALIDP_LAYER_CONTROL 0x004
  22. #define LAYER_ENABLE (1 << 0)
  23. #define LAYER_ROT_OFFSET 8
  24. #define LAYER_H_FLIP (1 << 10)
  25. #define LAYER_V_FLIP (1 << 11)
  26. #define LAYER_ROT_MASK (0xf << 8)
  27. #define MALIDP_LAYER_SIZE 0x00c
  28. #define LAYER_H_VAL(x) (((x) & 0x1fff) << 0)
  29. #define LAYER_V_VAL(x) (((x) & 0x1fff) << 16)
  30. #define MALIDP_LAYER_COMP_SIZE 0x010
  31. #define MALIDP_LAYER_OFFSET 0x014
  32. #define MALIDP_LAYER_STRIDE 0x018
  33. static void malidp_de_plane_destroy(struct drm_plane *plane)
  34. {
  35. struct malidp_plane *mp = to_malidp_plane(plane);
  36. if (mp->base.fb)
  37. drm_framebuffer_unreference(mp->base.fb);
  38. drm_plane_helper_disable(plane);
  39. drm_plane_cleanup(plane);
  40. devm_kfree(plane->dev->dev, mp);
  41. }
  42. struct drm_plane_state *malidp_duplicate_plane_state(struct drm_plane *plane)
  43. {
  44. struct malidp_plane_state *state, *m_state;
  45. if (!plane->state)
  46. return NULL;
  47. state = kmalloc(sizeof(*state), GFP_KERNEL);
  48. if (state) {
  49. m_state = to_malidp_plane_state(plane->state);
  50. __drm_atomic_helper_plane_duplicate_state(plane, &state->base);
  51. state->rotmem_size = m_state->rotmem_size;
  52. }
  53. return &state->base;
  54. }
  55. void malidp_destroy_plane_state(struct drm_plane *plane,
  56. struct drm_plane_state *state)
  57. {
  58. struct malidp_plane_state *m_state = to_malidp_plane_state(state);
  59. __drm_atomic_helper_plane_destroy_state(state);
  60. kfree(m_state);
  61. }
  62. static const struct drm_plane_funcs malidp_de_plane_funcs = {
  63. .update_plane = drm_atomic_helper_update_plane,
  64. .disable_plane = drm_atomic_helper_disable_plane,
  65. .destroy = malidp_de_plane_destroy,
  66. .reset = drm_atomic_helper_plane_reset,
  67. .atomic_duplicate_state = malidp_duplicate_plane_state,
  68. .atomic_destroy_state = malidp_destroy_plane_state,
  69. };
  70. static int malidp_de_plane_check(struct drm_plane *plane,
  71. struct drm_plane_state *state)
  72. {
  73. struct malidp_plane *mp = to_malidp_plane(plane);
  74. struct malidp_plane_state *ms = to_malidp_plane_state(state);
  75. u8 format_id;
  76. u32 src_w, src_h;
  77. if (!state->crtc || !state->fb)
  78. return 0;
  79. format_id = malidp_hw_get_format_id(&mp->hwdev->map, mp->layer->id,
  80. state->fb->pixel_format);
  81. if (format_id == MALIDP_INVALID_FORMAT_ID)
  82. return -EINVAL;
  83. src_w = state->src_w >> 16;
  84. src_h = state->src_h >> 16;
  85. if ((state->crtc_w > mp->hwdev->max_line_size) ||
  86. (state->crtc_h > mp->hwdev->max_line_size) ||
  87. (state->crtc_w < mp->hwdev->min_line_size) ||
  88. (state->crtc_h < mp->hwdev->min_line_size) ||
  89. (state->crtc_w != src_w) || (state->crtc_h != src_h))
  90. return -EINVAL;
  91. /* packed RGB888 / BGR888 can't be rotated or flipped */
  92. if (state->rotation != BIT(DRM_ROTATE_0) &&
  93. (state->fb->pixel_format == DRM_FORMAT_RGB888 ||
  94. state->fb->pixel_format == DRM_FORMAT_BGR888))
  95. return -EINVAL;
  96. ms->rotmem_size = 0;
  97. if (state->rotation & MALIDP_ROTATED_MASK) {
  98. int val;
  99. val = mp->hwdev->rotmem_required(mp->hwdev, state->crtc_h,
  100. state->crtc_w,
  101. state->fb->pixel_format);
  102. if (val < 0)
  103. return val;
  104. ms->rotmem_size = val;
  105. }
  106. return 0;
  107. }
  108. static void malidp_de_plane_update(struct drm_plane *plane,
  109. struct drm_plane_state *old_state)
  110. {
  111. struct drm_gem_cma_object *obj;
  112. struct malidp_plane *mp;
  113. const struct malidp_hw_regmap *map;
  114. u8 format_id;
  115. u16 ptr;
  116. u32 format, src_w, src_h, dest_w, dest_h, val = 0;
  117. int num_planes, i;
  118. mp = to_malidp_plane(plane);
  119. map = &mp->hwdev->map;
  120. format = plane->state->fb->pixel_format;
  121. format_id = malidp_hw_get_format_id(map, mp->layer->id, format);
  122. num_planes = drm_format_num_planes(format);
  123. /* convert src values from Q16 fixed point to integer */
  124. src_w = plane->state->src_w >> 16;
  125. src_h = plane->state->src_h >> 16;
  126. if (plane->state->rotation & MALIDP_ROTATED_MASK) {
  127. dest_w = plane->state->crtc_h;
  128. dest_h = plane->state->crtc_w;
  129. } else {
  130. dest_w = plane->state->crtc_w;
  131. dest_h = plane->state->crtc_h;
  132. }
  133. malidp_hw_write(mp->hwdev, format_id, mp->layer->base);
  134. for (i = 0; i < num_planes; i++) {
  135. /* calculate the offset for the layer's plane registers */
  136. ptr = mp->layer->ptr + (i << 4);
  137. obj = drm_fb_cma_get_gem_obj(plane->state->fb, i);
  138. malidp_hw_write(mp->hwdev, lower_32_bits(obj->paddr), ptr);
  139. malidp_hw_write(mp->hwdev, upper_32_bits(obj->paddr), ptr + 4);
  140. malidp_hw_write(mp->hwdev, plane->state->fb->pitches[i],
  141. mp->layer->base + MALIDP_LAYER_STRIDE);
  142. }
  143. malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
  144. mp->layer->base + MALIDP_LAYER_SIZE);
  145. malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
  146. mp->layer->base + MALIDP_LAYER_COMP_SIZE);
  147. malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) |
  148. LAYER_V_VAL(plane->state->crtc_y),
  149. mp->layer->base + MALIDP_LAYER_OFFSET);
  150. /* first clear the rotation bits in the register */
  151. malidp_hw_clearbits(mp->hwdev, LAYER_ROT_MASK,
  152. mp->layer->base + MALIDP_LAYER_CONTROL);
  153. /* setup the rotation and axis flip bits */
  154. if (plane->state->rotation & DRM_ROTATE_MASK)
  155. val = ilog2(plane->state->rotation & DRM_ROTATE_MASK) << LAYER_ROT_OFFSET;
  156. if (plane->state->rotation & BIT(DRM_REFLECT_X))
  157. val |= LAYER_V_FLIP;
  158. if (plane->state->rotation & BIT(DRM_REFLECT_Y))
  159. val |= LAYER_H_FLIP;
  160. /* set the 'enable layer' bit */
  161. val |= LAYER_ENABLE;
  162. malidp_hw_setbits(mp->hwdev, val,
  163. mp->layer->base + MALIDP_LAYER_CONTROL);
  164. }
  165. static void malidp_de_plane_disable(struct drm_plane *plane,
  166. struct drm_plane_state *state)
  167. {
  168. struct malidp_plane *mp = to_malidp_plane(plane);
  169. malidp_hw_clearbits(mp->hwdev, LAYER_ENABLE,
  170. mp->layer->base + MALIDP_LAYER_CONTROL);
  171. }
  172. static const struct drm_plane_helper_funcs malidp_de_plane_helper_funcs = {
  173. .atomic_check = malidp_de_plane_check,
  174. .atomic_update = malidp_de_plane_update,
  175. .atomic_disable = malidp_de_plane_disable,
  176. };
  177. int malidp_de_planes_init(struct drm_device *drm)
  178. {
  179. struct malidp_drm *malidp = drm->dev_private;
  180. const struct malidp_hw_regmap *map = &malidp->dev->map;
  181. struct malidp_plane *plane = NULL;
  182. enum drm_plane_type plane_type;
  183. unsigned long crtcs = 1 << drm->mode_config.num_crtc;
  184. u32 *formats;
  185. int ret, i, j, n;
  186. formats = kcalloc(map->n_input_formats, sizeof(*formats), GFP_KERNEL);
  187. if (!formats) {
  188. ret = -ENOMEM;
  189. goto cleanup;
  190. }
  191. for (i = 0; i < map->n_layers; i++) {
  192. u8 id = map->layers[i].id;
  193. plane = kzalloc(sizeof(*plane), GFP_KERNEL);
  194. if (!plane) {
  195. ret = -ENOMEM;
  196. goto cleanup;
  197. }
  198. /* build the list of DRM supported formats based on the map */
  199. for (n = 0, j = 0; j < map->n_input_formats; j++) {
  200. if ((map->input_formats[j].layer & id) == id)
  201. formats[n++] = map->input_formats[j].format;
  202. }
  203. plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
  204. DRM_PLANE_TYPE_OVERLAY;
  205. ret = drm_universal_plane_init(drm, &plane->base, crtcs,
  206. &malidp_de_plane_funcs, formats,
  207. n, plane_type, NULL);
  208. if (ret < 0)
  209. goto cleanup;
  210. if (!drm->mode_config.rotation_property) {
  211. unsigned long flags = BIT(DRM_ROTATE_0) |
  212. BIT(DRM_ROTATE_90) |
  213. BIT(DRM_ROTATE_180) |
  214. BIT(DRM_ROTATE_270) |
  215. BIT(DRM_REFLECT_X) |
  216. BIT(DRM_REFLECT_Y);
  217. drm->mode_config.rotation_property =
  218. drm_mode_create_rotation_property(drm, flags);
  219. }
  220. /* SMART layer can't be rotated */
  221. if (drm->mode_config.rotation_property && (id != DE_SMART))
  222. drm_object_attach_property(&plane->base.base,
  223. drm->mode_config.rotation_property,
  224. BIT(DRM_ROTATE_0));
  225. drm_plane_helper_add(&plane->base,
  226. &malidp_de_plane_helper_funcs);
  227. plane->hwdev = malidp->dev;
  228. plane->layer = &map->layers[i];
  229. }
  230. kfree(formats);
  231. return 0;
  232. cleanup:
  233. malidp_de_planes_destroy(drm);
  234. kfree(formats);
  235. return ret;
  236. }
  237. void malidp_de_planes_destroy(struct drm_device *drm)
  238. {
  239. struct drm_plane *p, *pt;
  240. list_for_each_entry_safe(p, pt, &drm->mode_config.plane_list, head) {
  241. drm_plane_cleanup(p);
  242. kfree(p);
  243. }
  244. }