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/drivers/pci/host/pci-hyperv.c

https://gitlab.com/CadeLaRen/linux
C | 1754 lines | 1093 code | 194 blank | 467 comment | 106 complexity | 3ea8e30c6f54b3f3498e87e6485da9a9 MD5 | raw file
  1. /*
  2. * Copyright (c) Microsoft Corporation.
  3. *
  4. * Author:
  5. * Jake Oshins <jakeo@microsoft.com>
  6. *
  7. * This driver acts as a paravirtual front-end for PCI Express root buses.
  8. * When a PCI Express function (either an entire device or an SR-IOV
  9. * Virtual Function) is being passed through to the VM, this driver exposes
  10. * a new bus to the guest VM. This is modeled as a root PCI bus because
  11. * no bridges are being exposed to the VM. In fact, with a "Generation 2"
  12. * VM within Hyper-V, there may seem to be no PCI bus at all in the VM
  13. * until a device as been exposed using this driver.
  14. *
  15. * Each root PCI bus has its own PCI domain, which is called "Segment" in
  16. * the PCI Firmware Specifications. Thus while each device passed through
  17. * to the VM using this front-end will appear at "device 0", the domain will
  18. * be unique. Typically, each bus will have one PCI function on it, though
  19. * this driver does support more than one.
  20. *
  21. * In order to map the interrupts from the device through to the guest VM,
  22. * this driver also implements an IRQ Domain, which handles interrupts (either
  23. * MSI or MSI-X) associated with the functions on the bus. As interrupts are
  24. * set up, torn down, or reaffined, this driver communicates with the
  25. * underlying hypervisor to adjust the mappings in the I/O MMU so that each
  26. * interrupt will be delivered to the correct virtual processor at the right
  27. * vector. This driver does not support level-triggered (line-based)
  28. * interrupts, and will report that the Interrupt Line register in the
  29. * function's configuration space is zero.
  30. *
  31. * The rest of this driver mostly maps PCI concepts onto underlying Hyper-V
  32. * facilities. For instance, the configuration space of a function exposed
  33. * by Hyper-V is mapped into a single page of memory space, and the
  34. * read and write handlers for config space must be aware of this mechanism.
  35. * Similarly, device setup and teardown involves messages sent to and from
  36. * the PCI back-end driver in Hyper-V.
  37. *
  38. * This program is free software; you can redistribute it and/or modify it
  39. * under the terms of the GNU General Public License version 2 as published
  40. * by the Free Software Foundation.
  41. *
  42. * This program is distributed in the hope that it will be useful, but
  43. * WITHOUT ANY WARRANTY; without even the implied warranty of
  44. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  45. * NON INFRINGEMENT. See the GNU General Public License for more
  46. * details.
  47. *
  48. */
  49. #include <linux/kernel.h>
  50. #include <linux/module.h>
  51. #include <linux/pci.h>
  52. #include <linux/semaphore.h>
  53. #include <linux/irqdomain.h>
  54. #include <asm/irqdomain.h>
  55. #include <asm/apic.h>
  56. #include <linux/msi.h>
  57. #include <linux/hyperv.h>
  58. #include <asm/mshyperv.h>
  59. /*
  60. * Protocol versions. The low word is the minor version, the high word the
  61. * major version.
  62. */
  63. #define PCI_MAKE_VERSION(major, minor) ((u32)(((major) << 16) | (major)))
  64. #define PCI_MAJOR_VERSION(version) ((u32)(version) >> 16)
  65. #define PCI_MINOR_VERSION(version) ((u32)(version) & 0xff)
  66. enum {
  67. PCI_PROTOCOL_VERSION_1_1 = PCI_MAKE_VERSION(1, 1),
  68. PCI_PROTOCOL_VERSION_CURRENT = PCI_PROTOCOL_VERSION_1_1
  69. };
  70. #define PCI_CONFIG_MMIO_LENGTH 0x2000
  71. #define CFG_PAGE_OFFSET 0x1000
  72. #define CFG_PAGE_SIZE (PCI_CONFIG_MMIO_LENGTH - CFG_PAGE_OFFSET)
  73. #define MAX_SUPPORTED_MSI_MESSAGES 0x400
  74. /*
  75. * Message Types
  76. */
  77. enum pci_message_type {
  78. /*
  79. * Version 1.1
  80. */
  81. PCI_MESSAGE_BASE = 0x42490000,
  82. PCI_BUS_RELATIONS = PCI_MESSAGE_BASE + 0,
  83. PCI_QUERY_BUS_RELATIONS = PCI_MESSAGE_BASE + 1,
  84. PCI_POWER_STATE_CHANGE = PCI_MESSAGE_BASE + 4,
  85. PCI_QUERY_RESOURCE_REQUIREMENTS = PCI_MESSAGE_BASE + 5,
  86. PCI_QUERY_RESOURCE_RESOURCES = PCI_MESSAGE_BASE + 6,
  87. PCI_BUS_D0ENTRY = PCI_MESSAGE_BASE + 7,
  88. PCI_BUS_D0EXIT = PCI_MESSAGE_BASE + 8,
  89. PCI_READ_BLOCK = PCI_MESSAGE_BASE + 9,
  90. PCI_WRITE_BLOCK = PCI_MESSAGE_BASE + 0xA,
  91. PCI_EJECT = PCI_MESSAGE_BASE + 0xB,
  92. PCI_QUERY_STOP = PCI_MESSAGE_BASE + 0xC,
  93. PCI_REENABLE = PCI_MESSAGE_BASE + 0xD,
  94. PCI_QUERY_STOP_FAILED = PCI_MESSAGE_BASE + 0xE,
  95. PCI_EJECTION_COMPLETE = PCI_MESSAGE_BASE + 0xF,
  96. PCI_RESOURCES_ASSIGNED = PCI_MESSAGE_BASE + 0x10,
  97. PCI_RESOURCES_RELEASED = PCI_MESSAGE_BASE + 0x11,
  98. PCI_INVALIDATE_BLOCK = PCI_MESSAGE_BASE + 0x12,
  99. PCI_QUERY_PROTOCOL_VERSION = PCI_MESSAGE_BASE + 0x13,
  100. PCI_CREATE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x14,
  101. PCI_DELETE_INTERRUPT_MESSAGE = PCI_MESSAGE_BASE + 0x15,
  102. PCI_MESSAGE_MAXIMUM
  103. };
  104. /*
  105. * Structures defining the virtual PCI Express protocol.
  106. */
  107. union pci_version {
  108. struct {
  109. u16 minor_version;
  110. u16 major_version;
  111. } parts;
  112. u32 version;
  113. } __packed;
  114. /*
  115. * Function numbers are 8-bits wide on Express, as interpreted through ARI,
  116. * which is all this driver does. This representation is the one used in
  117. * Windows, which is what is expected when sending this back and forth with
  118. * the Hyper-V parent partition.
  119. */
  120. union win_slot_encoding {
  121. struct {
  122. u32 func:8;
  123. u32 reserved:24;
  124. } bits;
  125. u32 slot;
  126. } __packed;
  127. /*
  128. * Pretty much as defined in the PCI Specifications.
  129. */
  130. struct pci_function_description {
  131. u16 v_id; /* vendor ID */
  132. u16 d_id; /* device ID */
  133. u8 rev;
  134. u8 prog_intf;
  135. u8 subclass;
  136. u8 base_class;
  137. u32 subsystem_id;
  138. union win_slot_encoding win_slot;
  139. u32 ser; /* serial number */
  140. } __packed;
  141. /**
  142. * struct hv_msi_desc
  143. * @vector: IDT entry
  144. * @delivery_mode: As defined in Intel's Programmer's
  145. * Reference Manual, Volume 3, Chapter 8.
  146. * @vector_count: Number of contiguous entries in the
  147. * Interrupt Descriptor Table that are
  148. * occupied by this Message-Signaled
  149. * Interrupt. For "MSI", as first defined
  150. * in PCI 2.2, this can be between 1 and
  151. * 32. For "MSI-X," as first defined in PCI
  152. * 3.0, this must be 1, as each MSI-X table
  153. * entry would have its own descriptor.
  154. * @reserved: Empty space
  155. * @cpu_mask: All the target virtual processors.
  156. */
  157. struct hv_msi_desc {
  158. u8 vector;
  159. u8 delivery_mode;
  160. u16 vector_count;
  161. u32 reserved;
  162. u64 cpu_mask;
  163. } __packed;
  164. /**
  165. * struct tran_int_desc
  166. * @reserved: unused, padding
  167. * @vector_count: same as in hv_msi_desc
  168. * @data: This is the "data payload" value that is
  169. * written by the device when it generates
  170. * a message-signaled interrupt, either MSI
  171. * or MSI-X.
  172. * @address: This is the address to which the data
  173. * payload is written on interrupt
  174. * generation.
  175. */
  176. struct tran_int_desc {
  177. u16 reserved;
  178. u16 vector_count;
  179. u32 data;
  180. u64 address;
  181. } __packed;
  182. /*
  183. * A generic message format for virtual PCI.
  184. * Specific message formats are defined later in the file.
  185. */
  186. struct pci_message {
  187. u32 message_type;
  188. } __packed;
  189. struct pci_child_message {
  190. u32 message_type;
  191. union win_slot_encoding wslot;
  192. } __packed;
  193. struct pci_incoming_message {
  194. struct vmpacket_descriptor hdr;
  195. struct pci_message message_type;
  196. } __packed;
  197. struct pci_response {
  198. struct vmpacket_descriptor hdr;
  199. s32 status; /* negative values are failures */
  200. } __packed;
  201. struct pci_packet {
  202. void (*completion_func)(void *context, struct pci_response *resp,
  203. int resp_packet_size);
  204. void *compl_ctxt;
  205. struct pci_message message;
  206. };
  207. /*
  208. * Specific message types supporting the PCI protocol.
  209. */
  210. /*
  211. * Version negotiation message. Sent from the guest to the host.
  212. * The guest is free to try different versions until the host
  213. * accepts the version.
  214. *
  215. * pci_version: The protocol version requested.
  216. * is_last_attempt: If TRUE, this is the last version guest will request.
  217. * reservedz: Reserved field, set to zero.
  218. */
  219. struct pci_version_request {
  220. struct pci_message message_type;
  221. enum pci_message_type protocol_version;
  222. } __packed;
  223. /*
  224. * Bus D0 Entry. This is sent from the guest to the host when the virtual
  225. * bus (PCI Express port) is ready for action.
  226. */
  227. struct pci_bus_d0_entry {
  228. struct pci_message message_type;
  229. u32 reserved;
  230. u64 mmio_base;
  231. } __packed;
  232. struct pci_bus_relations {
  233. struct pci_incoming_message incoming;
  234. u32 device_count;
  235. struct pci_function_description func[1];
  236. } __packed;
  237. struct pci_q_res_req_response {
  238. struct vmpacket_descriptor hdr;
  239. s32 status; /* negative values are failures */
  240. u32 probed_bar[6];
  241. } __packed;
  242. struct pci_set_power {
  243. struct pci_message message_type;
  244. union win_slot_encoding wslot;
  245. u32 power_state; /* In Windows terms */
  246. u32 reserved;
  247. } __packed;
  248. struct pci_set_power_response {
  249. struct vmpacket_descriptor hdr;
  250. s32 status; /* negative values are failures */
  251. union win_slot_encoding wslot;
  252. u32 resultant_state; /* In Windows terms */
  253. u32 reserved;
  254. } __packed;
  255. struct pci_resources_assigned {
  256. struct pci_message message_type;
  257. union win_slot_encoding wslot;
  258. u8 memory_range[0x14][6]; /* not used here */
  259. u32 msi_descriptors;
  260. u32 reserved[4];
  261. } __packed;
  262. struct pci_create_interrupt {
  263. struct pci_message message_type;
  264. union win_slot_encoding wslot;
  265. struct hv_msi_desc int_desc;
  266. } __packed;
  267. struct pci_create_int_response {
  268. struct pci_response response;
  269. u32 reserved;
  270. struct tran_int_desc int_desc;
  271. } __packed;
  272. struct pci_delete_interrupt {
  273. struct pci_message message_type;
  274. union win_slot_encoding wslot;
  275. struct tran_int_desc int_desc;
  276. } __packed;
  277. struct pci_dev_incoming {
  278. struct pci_incoming_message incoming;
  279. union win_slot_encoding wslot;
  280. } __packed;
  281. struct pci_eject_response {
  282. u32 message_type;
  283. union win_slot_encoding wslot;
  284. u32 status;
  285. } __packed;
  286. static int pci_ring_size = (4 * PAGE_SIZE);
  287. /*
  288. * Definitions or interrupt steering hypercall.
  289. */
  290. #define HV_PARTITION_ID_SELF ((u64)-1)
  291. #define HVCALL_RETARGET_INTERRUPT 0x7e
  292. struct retarget_msi_interrupt {
  293. u64 partition_id; /* use "self" */
  294. u64 device_id;
  295. u32 source; /* 1 for MSI(-X) */
  296. u32 reserved1;
  297. u32 address;
  298. u32 data;
  299. u64 reserved2;
  300. u32 vector;
  301. u32 flags;
  302. u64 vp_mask;
  303. } __packed;
  304. /*
  305. * Driver specific state.
  306. */
  307. enum hv_pcibus_state {
  308. hv_pcibus_init = 0,
  309. hv_pcibus_probed,
  310. hv_pcibus_installed,
  311. hv_pcibus_maximum
  312. };
  313. struct hv_pcibus_device {
  314. struct pci_sysdata sysdata;
  315. enum hv_pcibus_state state;
  316. atomic_t remove_lock;
  317. struct hv_device *hdev;
  318. resource_size_t low_mmio_space;
  319. resource_size_t high_mmio_space;
  320. struct resource *mem_config;
  321. struct resource *low_mmio_res;
  322. struct resource *high_mmio_res;
  323. struct completion *survey_event;
  324. struct completion remove_event;
  325. struct pci_bus *pci_bus;
  326. spinlock_t config_lock; /* Avoid two threads writing index page */
  327. spinlock_t device_list_lock; /* Protect lists below */
  328. void __iomem *cfg_addr;
  329. struct semaphore enum_sem;
  330. struct list_head resources_for_children;
  331. struct list_head children;
  332. struct list_head dr_list;
  333. struct work_struct wrk;
  334. struct msi_domain_info msi_info;
  335. struct msi_controller msi_chip;
  336. struct irq_domain *irq_domain;
  337. };
  338. /*
  339. * Tracks "Device Relations" messages from the host, which must be both
  340. * processed in order and deferred so that they don't run in the context
  341. * of the incoming packet callback.
  342. */
  343. struct hv_dr_work {
  344. struct work_struct wrk;
  345. struct hv_pcibus_device *bus;
  346. };
  347. struct hv_dr_state {
  348. struct list_head list_entry;
  349. u32 device_count;
  350. struct pci_function_description func[1];
  351. };
  352. enum hv_pcichild_state {
  353. hv_pcichild_init = 0,
  354. hv_pcichild_requirements,
  355. hv_pcichild_resourced,
  356. hv_pcichild_ejecting,
  357. hv_pcichild_maximum
  358. };
  359. enum hv_pcidev_ref_reason {
  360. hv_pcidev_ref_invalid = 0,
  361. hv_pcidev_ref_initial,
  362. hv_pcidev_ref_by_slot,
  363. hv_pcidev_ref_packet,
  364. hv_pcidev_ref_pnp,
  365. hv_pcidev_ref_childlist,
  366. hv_pcidev_irqdata,
  367. hv_pcidev_ref_max
  368. };
  369. struct hv_pci_dev {
  370. /* List protected by pci_rescan_remove_lock */
  371. struct list_head list_entry;
  372. atomic_t refs;
  373. enum hv_pcichild_state state;
  374. struct pci_function_description desc;
  375. bool reported_missing;
  376. struct hv_pcibus_device *hbus;
  377. struct work_struct wrk;
  378. /*
  379. * What would be observed if one wrote 0xFFFFFFFF to a BAR and then
  380. * read it back, for each of the BAR offsets within config space.
  381. */
  382. u32 probed_bar[6];
  383. };
  384. struct hv_pci_compl {
  385. struct completion host_event;
  386. s32 completion_status;
  387. };
  388. /**
  389. * hv_pci_generic_compl() - Invoked for a completion packet
  390. * @context: Set up by the sender of the packet.
  391. * @resp: The response packet
  392. * @resp_packet_size: Size in bytes of the packet
  393. *
  394. * This function is used to trigger an event and report status
  395. * for any message for which the completion packet contains a
  396. * status and nothing else.
  397. */
  398. static
  399. void
  400. hv_pci_generic_compl(void *context, struct pci_response *resp,
  401. int resp_packet_size)
  402. {
  403. struct hv_pci_compl *comp_pkt = context;
  404. if (resp_packet_size >= offsetofend(struct pci_response, status))
  405. comp_pkt->completion_status = resp->status;
  406. complete(&comp_pkt->host_event);
  407. }
  408. static struct hv_pci_dev *get_pcichild_wslot(struct hv_pcibus_device *hbus,
  409. u32 wslot);
  410. static void get_pcichild(struct hv_pci_dev *hv_pcidev,
  411. enum hv_pcidev_ref_reason reason);
  412. static void put_pcichild(struct hv_pci_dev *hv_pcidev,
  413. enum hv_pcidev_ref_reason reason);
  414. static void get_hvpcibus(struct hv_pcibus_device *hv_pcibus);
  415. static void put_hvpcibus(struct hv_pcibus_device *hv_pcibus);
  416. /**
  417. * devfn_to_wslot() - Convert from Linux PCI slot to Windows
  418. * @devfn: The Linux representation of PCI slot
  419. *
  420. * Windows uses a slightly different representation of PCI slot.
  421. *
  422. * Return: The Windows representation
  423. */
  424. static u32 devfn_to_wslot(int devfn)
  425. {
  426. union win_slot_encoding wslot;
  427. wslot.slot = 0;
  428. wslot.bits.func = PCI_SLOT(devfn) | (PCI_FUNC(devfn) << 5);
  429. return wslot.slot;
  430. }
  431. /**
  432. * wslot_to_devfn() - Convert from Windows PCI slot to Linux
  433. * @wslot: The Windows representation of PCI slot
  434. *
  435. * Windows uses a slightly different representation of PCI slot.
  436. *
  437. * Return: The Linux representation
  438. */
  439. static int wslot_to_devfn(u32 wslot)
  440. {
  441. union win_slot_encoding slot_no;
  442. slot_no.slot = wslot;
  443. return PCI_DEVFN(0, slot_no.bits.func);
  444. }
  445. /*
  446. * PCI Configuration Space for these root PCI buses is implemented as a pair
  447. * of pages in memory-mapped I/O space. Writing to the first page chooses
  448. * the PCI function being written or read. Once the first page has been
  449. * written to, the following page maps in the entire configuration space of
  450. * the function.
  451. */
  452. /**
  453. * _hv_pcifront_read_config() - Internal PCI config read
  454. * @hpdev: The PCI driver's representation of the device
  455. * @where: Offset within config space
  456. * @size: Size of the transfer
  457. * @val: Pointer to the buffer receiving the data
  458. */
  459. static void _hv_pcifront_read_config(struct hv_pci_dev *hpdev, int where,
  460. int size, u32 *val)
  461. {
  462. unsigned long flags;
  463. void __iomem *addr = hpdev->hbus->cfg_addr + CFG_PAGE_OFFSET + where;
  464. /*
  465. * If the attempt is to read the IDs or the ROM BAR, simulate that.
  466. */
  467. if (where + size <= PCI_COMMAND) {
  468. memcpy(val, ((u8 *)&hpdev->desc.v_id) + where, size);
  469. } else if (where >= PCI_CLASS_REVISION && where + size <=
  470. PCI_CACHE_LINE_SIZE) {
  471. memcpy(val, ((u8 *)&hpdev->desc.rev) + where -
  472. PCI_CLASS_REVISION, size);
  473. } else if (where >= PCI_SUBSYSTEM_VENDOR_ID && where + size <=
  474. PCI_ROM_ADDRESS) {
  475. memcpy(val, (u8 *)&hpdev->desc.subsystem_id + where -
  476. PCI_SUBSYSTEM_VENDOR_ID, size);
  477. } else if (where >= PCI_ROM_ADDRESS && where + size <=
  478. PCI_CAPABILITY_LIST) {
  479. /* ROM BARs are unimplemented */
  480. *val = 0;
  481. } else if (where >= PCI_INTERRUPT_LINE && where + size <=
  482. PCI_INTERRUPT_PIN) {
  483. /*
  484. * Interrupt Line and Interrupt PIN are hard-wired to zero
  485. * because this front-end only supports message-signaled
  486. * interrupts.
  487. */
  488. *val = 0;
  489. } else if (where + size <= CFG_PAGE_SIZE) {
  490. spin_lock_irqsave(&hpdev->hbus->config_lock, flags);
  491. /* Choose the function to be read. (See comment above) */
  492. writel(hpdev->desc.win_slot.slot, hpdev->hbus->cfg_addr);
  493. /* Make sure the function was chosen before we start reading. */
  494. mb();
  495. /* Read from that function's config space. */
  496. switch (size) {
  497. case 1:
  498. *val = readb(addr);
  499. break;
  500. case 2:
  501. *val = readw(addr);
  502. break;
  503. default:
  504. *val = readl(addr);
  505. break;
  506. }
  507. /*
  508. * Make sure the write was done before we release the spinlock
  509. * allowing consecutive reads/writes.
  510. */
  511. mb();
  512. spin_unlock_irqrestore(&hpdev->hbus->config_lock, flags);
  513. } else {
  514. dev_err(&hpdev->hbus->hdev->device,
  515. "Attempt to read beyond a function's config space.\n");
  516. }
  517. }
  518. /**
  519. * _hv_pcifront_write_config() - Internal PCI config write
  520. * @hpdev: The PCI driver's representation of the device
  521. * @where: Offset within config space
  522. * @size: Size of the transfer
  523. * @val: The data being transferred
  524. */
  525. static void _hv_pcifront_write_config(struct hv_pci_dev *hpdev, int where,
  526. int size, u32 val)
  527. {
  528. unsigned long flags;
  529. void __iomem *addr = hpdev->hbus->cfg_addr + CFG_PAGE_OFFSET + where;
  530. if (where >= PCI_SUBSYSTEM_VENDOR_ID &&
  531. where + size <= PCI_CAPABILITY_LIST) {
  532. /* SSIDs and ROM BARs are read-only */
  533. } else if (where >= PCI_COMMAND && where + size <= CFG_PAGE_SIZE) {
  534. spin_lock_irqsave(&hpdev->hbus->config_lock, flags);
  535. /* Choose the function to be written. (See comment above) */
  536. writel(hpdev->desc.win_slot.slot, hpdev->hbus->cfg_addr);
  537. /* Make sure the function was chosen before we start writing. */
  538. wmb();
  539. /* Write to that function's config space. */
  540. switch (size) {
  541. case 1:
  542. writeb(val, addr);
  543. break;
  544. case 2:
  545. writew(val, addr);
  546. break;
  547. default:
  548. writel(val, addr);
  549. break;
  550. }
  551. /*
  552. * Make sure the write was done before we release the spinlock
  553. * allowing consecutive reads/writes.
  554. */
  555. mb();
  556. spin_unlock_irqrestore(&hpdev->hbus->config_lock, flags);
  557. } else {
  558. dev_err(&hpdev->hbus->hdev->device,
  559. "Attempt to write beyond a function's config space.\n");
  560. }
  561. }
  562. /**
  563. * hv_pcifront_read_config() - Read configuration space
  564. * @bus: PCI Bus structure
  565. * @devfn: Device/function
  566. * @where: Offset from base
  567. * @size: Byte/word/dword
  568. * @val: Value to be read
  569. *
  570. * Return: PCIBIOS_SUCCESSFUL on success
  571. * PCIBIOS_DEVICE_NOT_FOUND on failure
  572. */
  573. static int hv_pcifront_read_config(struct pci_bus *bus, unsigned int devfn,
  574. int where, int size, u32 *val)
  575. {
  576. struct hv_pcibus_device *hbus =
  577. container_of(bus->sysdata, struct hv_pcibus_device, sysdata);
  578. struct hv_pci_dev *hpdev;
  579. hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(devfn));
  580. if (!hpdev)
  581. return PCIBIOS_DEVICE_NOT_FOUND;
  582. _hv_pcifront_read_config(hpdev, where, size, val);
  583. put_pcichild(hpdev, hv_pcidev_ref_by_slot);
  584. return PCIBIOS_SUCCESSFUL;
  585. }
  586. /**
  587. * hv_pcifront_write_config() - Write configuration space
  588. * @bus: PCI Bus structure
  589. * @devfn: Device/function
  590. * @where: Offset from base
  591. * @size: Byte/word/dword
  592. * @val: Value to be written to device
  593. *
  594. * Return: PCIBIOS_SUCCESSFUL on success
  595. * PCIBIOS_DEVICE_NOT_FOUND on failure
  596. */
  597. static int hv_pcifront_write_config(struct pci_bus *bus, unsigned int devfn,
  598. int where, int size, u32 val)
  599. {
  600. struct hv_pcibus_device *hbus =
  601. container_of(bus->sysdata, struct hv_pcibus_device, sysdata);
  602. struct hv_pci_dev *hpdev;
  603. hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(devfn));
  604. if (!hpdev)
  605. return PCIBIOS_DEVICE_NOT_FOUND;
  606. _hv_pcifront_write_config(hpdev, where, size, val);
  607. put_pcichild(hpdev, hv_pcidev_ref_by_slot);
  608. return PCIBIOS_SUCCESSFUL;
  609. }
  610. /* PCIe operations */
  611. static struct pci_ops hv_pcifront_ops = {
  612. .read = hv_pcifront_read_config,
  613. .write = hv_pcifront_write_config,
  614. };
  615. /* Interrupt management hooks */
  616. static void hv_int_desc_free(struct hv_pci_dev *hpdev,
  617. struct tran_int_desc *int_desc)
  618. {
  619. struct pci_delete_interrupt *int_pkt;
  620. struct {
  621. struct pci_packet pkt;
  622. u8 buffer[sizeof(struct pci_delete_interrupt) -
  623. sizeof(struct pci_message)];
  624. } ctxt;
  625. memset(&ctxt, 0, sizeof(ctxt));
  626. int_pkt = (struct pci_delete_interrupt *)&ctxt.pkt.message;
  627. int_pkt->message_type.message_type =
  628. PCI_DELETE_INTERRUPT_MESSAGE;
  629. int_pkt->wslot.slot = hpdev->desc.win_slot.slot;
  630. int_pkt->int_desc = *int_desc;
  631. vmbus_sendpacket(hpdev->hbus->hdev->channel, int_pkt, sizeof(*int_pkt),
  632. (unsigned long)&ctxt.pkt, VM_PKT_DATA_INBAND, 0);
  633. kfree(int_desc);
  634. }
  635. /**
  636. * hv_msi_free() - Free the MSI.
  637. * @domain: The interrupt domain pointer
  638. * @info: Extra MSI-related context
  639. * @irq: Identifies the IRQ.
  640. *
  641. * The Hyper-V parent partition and hypervisor are tracking the
  642. * messages that are in use, keeping the interrupt redirection
  643. * table up to date. This callback sends a message that frees
  644. * the IRT entry and related tracking nonsense.
  645. */
  646. static void hv_msi_free(struct irq_domain *domain, struct msi_domain_info *info,
  647. unsigned int irq)
  648. {
  649. struct hv_pcibus_device *hbus;
  650. struct hv_pci_dev *hpdev;
  651. struct pci_dev *pdev;
  652. struct tran_int_desc *int_desc;
  653. struct irq_data *irq_data = irq_domain_get_irq_data(domain, irq);
  654. struct msi_desc *msi = irq_data_get_msi_desc(irq_data);
  655. pdev = msi_desc_to_pci_dev(msi);
  656. hbus = info->data;
  657. int_desc = irq_data_get_irq_chip_data(irq_data);
  658. if (!int_desc)
  659. return;
  660. irq_data->chip_data = NULL;
  661. hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
  662. if (!hpdev) {
  663. kfree(int_desc);
  664. return;
  665. }
  666. hv_int_desc_free(hpdev, int_desc);
  667. put_pcichild(hpdev, hv_pcidev_ref_by_slot);
  668. }
  669. static int hv_set_affinity(struct irq_data *data, const struct cpumask *dest,
  670. bool force)
  671. {
  672. struct irq_data *parent = data->parent_data;
  673. return parent->chip->irq_set_affinity(parent, dest, force);
  674. }
  675. void hv_irq_mask(struct irq_data *data)
  676. {
  677. pci_msi_mask_irq(data);
  678. }
  679. /**
  680. * hv_irq_unmask() - "Unmask" the IRQ by setting its current
  681. * affinity.
  682. * @data: Describes the IRQ
  683. *
  684. * Build new a destination for the MSI and make a hypercall to
  685. * update the Interrupt Redirection Table. "Device Logical ID"
  686. * is built out of this PCI bus's instance GUID and the function
  687. * number of the device.
  688. */
  689. void hv_irq_unmask(struct irq_data *data)
  690. {
  691. struct msi_desc *msi_desc = irq_data_get_msi_desc(data);
  692. struct irq_cfg *cfg = irqd_cfg(data);
  693. struct retarget_msi_interrupt params;
  694. struct hv_pcibus_device *hbus;
  695. struct cpumask *dest;
  696. struct pci_bus *pbus;
  697. struct pci_dev *pdev;
  698. int cpu;
  699. dest = irq_data_get_affinity_mask(data);
  700. pdev = msi_desc_to_pci_dev(msi_desc);
  701. pbus = pdev->bus;
  702. hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
  703. memset(&params, 0, sizeof(params));
  704. params.partition_id = HV_PARTITION_ID_SELF;
  705. params.source = 1; /* MSI(-X) */
  706. params.address = msi_desc->msg.address_lo;
  707. params.data = msi_desc->msg.data;
  708. params.device_id = (hbus->hdev->dev_instance.b[5] << 24) |
  709. (hbus->hdev->dev_instance.b[4] << 16) |
  710. (hbus->hdev->dev_instance.b[7] << 8) |
  711. (hbus->hdev->dev_instance.b[6] & 0xf8) |
  712. PCI_FUNC(pdev->devfn);
  713. params.vector = cfg->vector;
  714. for_each_cpu_and(cpu, dest, cpu_online_mask)
  715. params.vp_mask |= (1ULL << vmbus_cpu_number_to_vp_number(cpu));
  716. hv_do_hypercall(HVCALL_RETARGET_INTERRUPT, &params, NULL);
  717. pci_msi_unmask_irq(data);
  718. }
  719. struct compose_comp_ctxt {
  720. struct hv_pci_compl comp_pkt;
  721. struct tran_int_desc int_desc;
  722. };
  723. static void hv_pci_compose_compl(void *context, struct pci_response *resp,
  724. int resp_packet_size)
  725. {
  726. struct compose_comp_ctxt *comp_pkt = context;
  727. struct pci_create_int_response *int_resp =
  728. (struct pci_create_int_response *)resp;
  729. comp_pkt->comp_pkt.completion_status = resp->status;
  730. comp_pkt->int_desc = int_resp->int_desc;
  731. complete(&comp_pkt->comp_pkt.host_event);
  732. }
  733. /**
  734. * hv_compose_msi_msg() - Supplies a valid MSI address/data
  735. * @data: Everything about this MSI
  736. * @msg: Buffer that is filled in by this function
  737. *
  738. * This function unpacks the IRQ looking for target CPU set, IDT
  739. * vector and mode and sends a message to the parent partition
  740. * asking for a mapping for that tuple in this partition. The
  741. * response supplies a data value and address to which that data
  742. * should be written to trigger that interrupt.
  743. */
  744. static void hv_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
  745. {
  746. struct irq_cfg *cfg = irqd_cfg(data);
  747. struct hv_pcibus_device *hbus;
  748. struct hv_pci_dev *hpdev;
  749. struct pci_bus *pbus;
  750. struct pci_dev *pdev;
  751. struct pci_create_interrupt *int_pkt;
  752. struct compose_comp_ctxt comp;
  753. struct tran_int_desc *int_desc;
  754. struct cpumask *affinity;
  755. struct {
  756. struct pci_packet pkt;
  757. u8 buffer[sizeof(struct pci_create_interrupt) -
  758. sizeof(struct pci_message)];
  759. } ctxt;
  760. int cpu;
  761. int ret;
  762. pdev = msi_desc_to_pci_dev(irq_data_get_msi_desc(data));
  763. pbus = pdev->bus;
  764. hbus = container_of(pbus->sysdata, struct hv_pcibus_device, sysdata);
  765. hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
  766. if (!hpdev)
  767. goto return_null_message;
  768. /* Free any previous message that might have already been composed. */
  769. if (data->chip_data) {
  770. int_desc = data->chip_data;
  771. data->chip_data = NULL;
  772. hv_int_desc_free(hpdev, int_desc);
  773. }
  774. int_desc = kzalloc(sizeof(*int_desc), GFP_KERNEL);
  775. if (!int_desc)
  776. goto drop_reference;
  777. memset(&ctxt, 0, sizeof(ctxt));
  778. init_completion(&comp.comp_pkt.host_event);
  779. ctxt.pkt.completion_func = hv_pci_compose_compl;
  780. ctxt.pkt.compl_ctxt = &comp;
  781. int_pkt = (struct pci_create_interrupt *)&ctxt.pkt.message;
  782. int_pkt->message_type.message_type = PCI_CREATE_INTERRUPT_MESSAGE;
  783. int_pkt->wslot.slot = hpdev->desc.win_slot.slot;
  784. int_pkt->int_desc.vector = cfg->vector;
  785. int_pkt->int_desc.vector_count = 1;
  786. int_pkt->int_desc.delivery_mode =
  787. (apic->irq_delivery_mode == dest_LowestPrio) ? 1 : 0;
  788. /*
  789. * This bit doesn't have to work on machines with more than 64
  790. * processors because Hyper-V only supports 64 in a guest.
  791. */
  792. affinity = irq_data_get_affinity_mask(data);
  793. for_each_cpu_and(cpu, affinity, cpu_online_mask) {
  794. int_pkt->int_desc.cpu_mask |=
  795. (1ULL << vmbus_cpu_number_to_vp_number(cpu));
  796. }
  797. ret = vmbus_sendpacket(hpdev->hbus->hdev->channel, int_pkt,
  798. sizeof(*int_pkt), (unsigned long)&ctxt.pkt,
  799. VM_PKT_DATA_INBAND,
  800. VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
  801. if (!ret)
  802. wait_for_completion(&comp.comp_pkt.host_event);
  803. if (comp.comp_pkt.completion_status < 0) {
  804. dev_err(&hbus->hdev->device,
  805. "Request for interrupt failed: 0x%x",
  806. comp.comp_pkt.completion_status);
  807. goto free_int_desc;
  808. }
  809. /*
  810. * Record the assignment so that this can be unwound later. Using
  811. * irq_set_chip_data() here would be appropriate, but the lock it takes
  812. * is already held.
  813. */
  814. *int_desc = comp.int_desc;
  815. data->chip_data = int_desc;
  816. /* Pass up the result. */
  817. msg->address_hi = comp.int_desc.address >> 32;
  818. msg->address_lo = comp.int_desc.address & 0xffffffff;
  819. msg->data = comp.int_desc.data;
  820. put_pcichild(hpdev, hv_pcidev_ref_by_slot);
  821. return;
  822. free_int_desc:
  823. kfree(int_desc);
  824. drop_reference:
  825. put_pcichild(hpdev, hv_pcidev_ref_by_slot);
  826. return_null_message:
  827. msg->address_hi = 0;
  828. msg->address_lo = 0;
  829. msg->data = 0;
  830. }
  831. /* HW Interrupt Chip Descriptor */
  832. static struct irq_chip hv_msi_irq_chip = {
  833. .name = "Hyper-V PCIe MSI",
  834. .irq_compose_msi_msg = hv_compose_msi_msg,
  835. .irq_set_affinity = hv_set_affinity,
  836. .irq_ack = irq_chip_ack_parent,
  837. .irq_mask = hv_irq_mask,
  838. .irq_unmask = hv_irq_unmask,
  839. };
  840. static irq_hw_number_t hv_msi_domain_ops_get_hwirq(struct msi_domain_info *info,
  841. msi_alloc_info_t *arg)
  842. {
  843. return arg->msi_hwirq;
  844. }
  845. static struct msi_domain_ops hv_msi_ops = {
  846. .get_hwirq = hv_msi_domain_ops_get_hwirq,
  847. .msi_prepare = pci_msi_prepare,
  848. .set_desc = pci_msi_set_desc,
  849. .msi_free = hv_msi_free,
  850. };
  851. /**
  852. * hv_pcie_init_irq_domain() - Initialize IRQ domain
  853. * @hbus: The root PCI bus
  854. *
  855. * This function creates an IRQ domain which will be used for
  856. * interrupts from devices that have been passed through. These
  857. * devices only support MSI and MSI-X, not line-based interrupts
  858. * or simulations of line-based interrupts through PCIe's
  859. * fabric-layer messages. Because interrupts are remapped, we
  860. * can support multi-message MSI here.
  861. *
  862. * Return: '0' on success and error value on failure
  863. */
  864. static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus)
  865. {
  866. hbus->msi_info.chip = &hv_msi_irq_chip;
  867. hbus->msi_info.ops = &hv_msi_ops;
  868. hbus->msi_info.flags = (MSI_FLAG_USE_DEF_DOM_OPS |
  869. MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI |
  870. MSI_FLAG_PCI_MSIX);
  871. hbus->msi_info.handler = handle_edge_irq;
  872. hbus->msi_info.handler_name = "edge";
  873. hbus->msi_info.data = hbus;
  874. hbus->irq_domain = pci_msi_create_irq_domain(hbus->sysdata.fwnode,
  875. &hbus->msi_info,
  876. x86_vector_domain);
  877. if (!hbus->irq_domain) {
  878. dev_err(&hbus->hdev->device,
  879. "Failed to build an MSI IRQ domain\n");
  880. return -ENODEV;
  881. }
  882. return 0;
  883. }
  884. /**
  885. * get_bar_size() - Get the address space consumed by a BAR
  886. * @bar_val: Value that a BAR returned after -1 was written
  887. * to it.
  888. *
  889. * This function returns the size of the BAR, rounded up to 1
  890. * page. It has to be rounded up because the hypervisor's page
  891. * table entry that maps the BAR into the VM can't specify an
  892. * offset within a page. The invariant is that the hypervisor
  893. * must place any BARs of smaller than page length at the
  894. * beginning of a page.
  895. *
  896. * Return: Size in bytes of the consumed MMIO space.
  897. */
  898. static u64 get_bar_size(u64 bar_val)
  899. {
  900. return round_up((1 + ~(bar_val & PCI_BASE_ADDRESS_MEM_MASK)),
  901. PAGE_SIZE);
  902. }
  903. /**
  904. * survey_child_resources() - Total all MMIO requirements
  905. * @hbus: Root PCI bus, as understood by this driver
  906. */
  907. static void survey_child_resources(struct hv_pcibus_device *hbus)
  908. {
  909. struct list_head *iter;
  910. struct hv_pci_dev *hpdev;
  911. resource_size_t bar_size = 0;
  912. unsigned long flags;
  913. struct completion *event;
  914. u64 bar_val;
  915. int i;
  916. /* If nobody is waiting on the answer, don't compute it. */
  917. event = xchg(&hbus->survey_event, NULL);
  918. if (!event)
  919. return;
  920. /* If the answer has already been computed, go with it. */
  921. if (hbus->low_mmio_space || hbus->high_mmio_space) {
  922. complete(event);
  923. return;
  924. }
  925. spin_lock_irqsave(&hbus->device_list_lock, flags);
  926. /*
  927. * Due to an interesting quirk of the PCI spec, all memory regions
  928. * for a child device are a power of 2 in size and aligned in memory,
  929. * so it's sufficient to just add them up without tracking alignment.
  930. */
  931. list_for_each(iter, &hbus->children) {
  932. hpdev = container_of(iter, struct hv_pci_dev, list_entry);
  933. for (i = 0; i < 6; i++) {
  934. if (hpdev->probed_bar[i] & PCI_BASE_ADDRESS_SPACE_IO)
  935. dev_err(&hbus->hdev->device,
  936. "There's an I/O BAR in this list!\n");
  937. if (hpdev->probed_bar[i] != 0) {
  938. /*
  939. * A probed BAR has all the upper bits set that
  940. * can be changed.
  941. */
  942. bar_val = hpdev->probed_bar[i];
  943. if (bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64)
  944. bar_val |=
  945. ((u64)hpdev->probed_bar[++i] << 32);
  946. else
  947. bar_val |= 0xffffffff00000000ULL;
  948. bar_size = get_bar_size(bar_val);
  949. if (bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64)
  950. hbus->high_mmio_space += bar_size;
  951. else
  952. hbus->low_mmio_space += bar_size;
  953. }
  954. }
  955. }
  956. spin_unlock_irqrestore(&hbus->device_list_lock, flags);
  957. complete(event);
  958. }
  959. /**
  960. * prepopulate_bars() - Fill in BARs with defaults
  961. * @hbus: Root PCI bus, as understood by this driver
  962. *
  963. * The core PCI driver code seems much, much happier if the BARs
  964. * for a device have values upon first scan. So fill them in.
  965. * The algorithm below works down from large sizes to small,
  966. * attempting to pack the assignments optimally. The assumption,
  967. * enforced in other parts of the code, is that the beginning of
  968. * the memory-mapped I/O space will be aligned on the largest
  969. * BAR size.
  970. */
  971. static void prepopulate_bars(struct hv_pcibus_device *hbus)
  972. {
  973. resource_size_t high_size = 0;
  974. resource_size_t low_size = 0;
  975. resource_size_t high_base = 0;
  976. resource_size_t low_base = 0;
  977. resource_size_t bar_size;
  978. struct hv_pci_dev *hpdev;
  979. struct list_head *iter;
  980. unsigned long flags;
  981. u64 bar_val;
  982. u32 command;
  983. bool high;
  984. int i;
  985. if (hbus->low_mmio_space) {
  986. low_size = 1ULL << (63 - __builtin_clzll(hbus->low_mmio_space));
  987. low_base = hbus->low_mmio_res->start;
  988. }
  989. if (hbus->high_mmio_space) {
  990. high_size = 1ULL <<
  991. (63 - __builtin_clzll(hbus->high_mmio_space));
  992. high_base = hbus->high_mmio_res->start;
  993. }
  994. spin_lock_irqsave(&hbus->device_list_lock, flags);
  995. /* Pick addresses for the BARs. */
  996. do {
  997. list_for_each(iter, &hbus->children) {
  998. hpdev = container_of(iter, struct hv_pci_dev,
  999. list_entry);
  1000. for (i = 0; i < 6; i++) {
  1001. bar_val = hpdev->probed_bar[i];
  1002. if (bar_val == 0)
  1003. continue;
  1004. high = bar_val & PCI_BASE_ADDRESS_MEM_TYPE_64;
  1005. if (high) {
  1006. bar_val |=
  1007. ((u64)hpdev->probed_bar[i + 1]
  1008. << 32);
  1009. } else {
  1010. bar_val |= 0xffffffffULL << 32;
  1011. }
  1012. bar_size = get_bar_size(bar_val);
  1013. if (high) {
  1014. if (high_size != bar_size) {
  1015. i++;
  1016. continue;
  1017. }
  1018. _hv_pcifront_write_config(hpdev,
  1019. PCI_BASE_ADDRESS_0 + (4 * i),
  1020. 4,
  1021. (u32)(high_base & 0xffffff00));
  1022. i++;
  1023. _hv_pcifront_write_config(hpdev,
  1024. PCI_BASE_ADDRESS_0 + (4 * i),
  1025. 4, (u32)(high_base >> 32));
  1026. high_base += bar_size;
  1027. } else {
  1028. if (low_size != bar_size)
  1029. continue;
  1030. _hv_pcifront_write_config(hpdev,
  1031. PCI_BASE_ADDRESS_0 + (4 * i),
  1032. 4,
  1033. (u32)(low_base & 0xffffff00));
  1034. low_base += bar_size;
  1035. }
  1036. }
  1037. if (high_size <= 1 && low_size <= 1) {
  1038. /* Set the memory enable bit. */
  1039. _hv_pcifront_read_config(hpdev, PCI_COMMAND, 2,
  1040. &command);
  1041. command |= PCI_COMMAND_MEMORY;
  1042. _hv_pcifront_write_config(hpdev, PCI_COMMAND, 2,
  1043. command);
  1044. break;
  1045. }
  1046. }
  1047. high_size >>= 1;
  1048. low_size >>= 1;
  1049. } while (high_size || low_size);
  1050. spin_unlock_irqrestore(&hbus->device_list_lock, flags);
  1051. }
  1052. /**
  1053. * create_root_hv_pci_bus() - Expose a new root PCI bus
  1054. * @hbus: Root PCI bus, as understood by this driver
  1055. *
  1056. * Return: 0 on success, -errno on failure
  1057. */
  1058. static int create_root_hv_pci_bus(struct hv_pcibus_device *hbus)
  1059. {
  1060. /* Register the device */
  1061. hbus->pci_bus = pci_create_root_bus(&hbus->hdev->device,
  1062. 0, /* bus number is always zero */
  1063. &hv_pcifront_ops,
  1064. &hbus->sysdata,
  1065. &hbus->resources_for_children);
  1066. if (!hbus->pci_bus)
  1067. return -ENODEV;
  1068. hbus->pci_bus->msi = &hbus->msi_chip;
  1069. hbus->pci_bus->msi->dev = &hbus->hdev->device;
  1070. pci_scan_child_bus(hbus->pci_bus);
  1071. pci_bus_assign_resources(hbus->pci_bus);
  1072. pci_bus_add_devices(hbus->pci_bus);
  1073. hbus->state = hv_pcibus_installed;
  1074. return 0;
  1075. }
  1076. struct q_res_req_compl {
  1077. struct completion host_event;
  1078. struct hv_pci_dev *hpdev;
  1079. };
  1080. /**
  1081. * q_resource_requirements() - Query Resource Requirements
  1082. * @context: The completion context.
  1083. * @resp: The response that came from the host.
  1084. * @resp_packet_size: The size in bytes of resp.
  1085. *
  1086. * This function is invoked on completion of a Query Resource
  1087. * Requirements packet.
  1088. */
  1089. static void q_resource_requirements(void *context, struct pci_response *resp,
  1090. int resp_packet_size)
  1091. {
  1092. struct q_res_req_compl *completion = context;
  1093. struct pci_q_res_req_response *q_res_req =
  1094. (struct pci_q_res_req_response *)resp;
  1095. int i;
  1096. if (resp->status < 0) {
  1097. dev_err(&completion->hpdev->hbus->hdev->device,
  1098. "query resource requirements failed: %x\n",
  1099. resp->status);
  1100. } else {
  1101. for (i = 0; i < 6; i++) {
  1102. completion->hpdev->probed_bar[i] =
  1103. q_res_req->probed_bar[i];
  1104. }
  1105. }
  1106. complete(&completion->host_event);
  1107. }
  1108. static void get_pcichild(struct hv_pci_dev *hpdev,
  1109. enum hv_pcidev_ref_reason reason)
  1110. {
  1111. atomic_inc(&hpdev->refs);
  1112. }
  1113. static void put_pcichild(struct hv_pci_dev *hpdev,
  1114. enum hv_pcidev_ref_reason reason)
  1115. {
  1116. if (atomic_dec_and_test(&hpdev->refs))
  1117. kfree(hpdev);
  1118. }
  1119. /**
  1120. * new_pcichild_device() - Create a new child device
  1121. * @hbus: The internal struct tracking this root PCI bus.
  1122. * @desc: The information supplied so far from the host
  1123. * about the device.
  1124. *
  1125. * This function creates the tracking structure for a new child
  1126. * device and kicks off the process of figuring out what it is.
  1127. *
  1128. * Return: Pointer to the new tracking struct
  1129. */
  1130. static struct hv_pci_dev *new_pcichild_device(struct hv_pcibus_device *hbus,
  1131. struct pci_function_description *desc)
  1132. {
  1133. struct hv_pci_dev *hpdev;
  1134. struct pci_child_message *res_req;
  1135. struct q_res_req_compl comp_pkt;
  1136. union {
  1137. struct pci_packet init_packet;
  1138. u8 buffer[0x100];
  1139. } pkt;
  1140. unsigned long flags;
  1141. int ret;
  1142. hpdev = kzalloc(sizeof(*hpdev), GFP_ATOMIC);
  1143. if (!hpdev)
  1144. return NULL;
  1145. hpdev->hbus = hbus;
  1146. memset(&pkt, 0, sizeof(pkt));
  1147. init_completion(&comp_pkt.host_event);
  1148. comp_pkt.hpdev = hpdev;
  1149. pkt.init_packet.compl_ctxt = &comp_pkt;
  1150. pkt.init_packet.completion_func = q_resource_requirements;
  1151. res_req = (struct pci_child_message *)&pkt.init_packet.message;
  1152. res_req->message_type = PCI_QUERY_RESOURCE_REQUIREMENTS;
  1153. res_req->wslot.slot = desc->win_slot.slot;
  1154. ret = vmbus_sendpacket(hbus->hdev->channel, res_req,
  1155. sizeof(struct pci_child_message),
  1156. (unsigned long)&pkt.init_packet,
  1157. VM_PKT_DATA_INBAND,
  1158. VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
  1159. if (ret)
  1160. goto error;
  1161. wait_for_completion(&comp_pkt.host_event);
  1162. hpdev->desc = *desc;
  1163. get_pcichild(hpdev, hv_pcidev_ref_initial);
  1164. get_pcichild(hpdev, hv_pcidev_ref_childlist);
  1165. spin_lock_irqsave(&hbus->device_list_lock, flags);
  1166. list_add_tail(&hpdev->list_entry, &hbus->children);
  1167. spin_unlock_irqrestore(&hbus->device_list_lock, flags);
  1168. return hpdev;
  1169. error:
  1170. kfree(hpdev);
  1171. return NULL;
  1172. }
  1173. /**
  1174. * get_pcichild_wslot() - Find device from slot
  1175. * @hbus: Root PCI bus, as understood by this driver
  1176. * @wslot: Location on the bus
  1177. *
  1178. * This function looks up a PCI device and returns the internal
  1179. * representation of it. It acquires a reference on it, so that
  1180. * the device won't be deleted while somebody is using it. The
  1181. * caller is responsible for calling put_pcichild() to release
  1182. * this reference.
  1183. *
  1184. * Return: Internal representation of a PCI device
  1185. */
  1186. static struct hv_pci_dev *get_pcichild_wslot(struct hv_pcibus_device *hbus,
  1187. u32 wslot)
  1188. {
  1189. unsigned long flags;
  1190. struct hv_pci_dev *iter, *hpdev = NULL;
  1191. spin_lock_irqsave(&hbus->device_list_lock, flags);
  1192. list_for_each_entry(iter, &hbus->children, list_entry) {
  1193. if (iter->desc.win_slot.slot == wslot) {
  1194. hpdev = iter;
  1195. get_pcichild(hpdev, hv_pcidev_ref_by_slot);
  1196. break;
  1197. }
  1198. }
  1199. spin_unlock_irqrestore(&hbus->device_list_lock, flags);
  1200. return hpdev;
  1201. }
  1202. /**
  1203. * pci_devices_present_work() - Handle new list of child devices
  1204. * @work: Work struct embedded in struct hv_dr_work
  1205. *
  1206. * "Bus Relations" is the Windows term for "children of this
  1207. * bus." The terminology is preserved here for people trying to
  1208. * debug the interaction between Hyper-V and Linux. This
  1209. * function is called when the parent partition reports a list
  1210. * of functions that should be observed under this PCI Express
  1211. * port (bus).
  1212. *
  1213. * This function updates the list, and must tolerate being
  1214. * called multiple times with the same information. The typical
  1215. * number of child devices is one, with very atypical cases
  1216. * involving three or four, so the algorithms used here can be
  1217. * simple and inefficient.
  1218. *
  1219. * It must also treat the omission of a previously observed device as
  1220. * notification that the device no longer exists.
  1221. *
  1222. * Note that this function is a work item, and it may not be
  1223. * invoked in the order that it was queued. Back to back
  1224. * updates of the list of present devices may involve queuing
  1225. * multiple work items, and this one may run before ones that
  1226. * were sent later. As such, this function only does something
  1227. * if is the last one in the queue.
  1228. */
  1229. static void pci_devices_present_work(struct work_struct *work)
  1230. {
  1231. u32 child_no;
  1232. bool found;
  1233. struct list_head *iter;
  1234. struct pci_function_description *new_desc;
  1235. struct hv_pci_dev *hpdev;
  1236. struct hv_pcibus_device *hbus;
  1237. struct list_head removed;
  1238. struct hv_dr_work *dr_wrk;
  1239. struct hv_dr_state *dr = NULL;
  1240. unsigned long flags;
  1241. dr_wrk = container_of(work, struct hv_dr_work, wrk);
  1242. hbus = dr_wrk->bus;
  1243. kfree(dr_wrk);
  1244. INIT_LIST_HEAD(&removed);
  1245. if (down_interruptible(&hbus->enum_sem)) {
  1246. put_hvpcibus(hbus);
  1247. return;
  1248. }
  1249. /* Pull this off the queue and process it if it was the last one. */
  1250. spin_lock_irqsave(&hbus->device_list_lock, flags);
  1251. while (!list_empty(&hbus->dr_list)) {
  1252. dr = list_first_entry(&hbus->dr_list, struct hv_dr_state,
  1253. list_entry);
  1254. list_del(&dr->list_entry);
  1255. /* Throw this away if the list still has stuff in it. */
  1256. if (!list_empty(&hbus->dr_list)) {
  1257. kfree(dr);
  1258. continue;
  1259. }
  1260. }
  1261. spin_unlock_irqrestore(&hbus->device_list_lock, flags);
  1262. if (!dr) {
  1263. up(&hbus->enum_sem);
  1264. put_hvpcibus(hbus);
  1265. return;
  1266. }
  1267. /* First, mark all existing children as reported missing. */
  1268. spin_lock_irqsave(&hbus->device_list_lock, flags);
  1269. list_for_each(iter, &hbus->children) {
  1270. hpdev = container_of(iter, struct hv_pci_dev,
  1271. list_entry);
  1272. hpdev->reported_missing = true;
  1273. }
  1274. spin_unlock_irqrestore(&hbus->device_list_lock, flags);
  1275. /* Next, add back any reported devices. */
  1276. for (child_no = 0; child_no < dr->device_count; child_no++) {
  1277. found = false;
  1278. new_desc = &dr->func[child_no];
  1279. spin_lock_irqsave(&hbus->device_list_lock, flags);
  1280. list_for_each(iter, &hbus->children) {
  1281. hpdev = container_of(iter, struct hv_pci_dev,
  1282. list_entry);
  1283. if ((hpdev->desc.win_slot.slot ==
  1284. new_desc->win_slot.slot) &&
  1285. (hpdev->desc.v_id == new_desc->v_id) &&
  1286. (hpdev->desc.d_id == new_desc->d_id) &&
  1287. (hpdev->desc.ser == new_desc->ser)) {
  1288. hpdev->reported_missing = false;
  1289. found = true;
  1290. }
  1291. }
  1292. spin_unlock_irqrestore(&hbus->device_list_lock, flags);
  1293. if (!found) {
  1294. hpdev = new_pcichild_device(hbus, new_desc);
  1295. if (!hpdev)
  1296. dev_err(&hbus->hdev->device,
  1297. "couldn't record a child device.\n");
  1298. }
  1299. }
  1300. /* Move missing children to a list on the stack. */
  1301. spin_lock_irqsave(&hbus->device_list_lock, flags);
  1302. do {
  1303. found = false;
  1304. list_for_each(iter, &hbus->children) {
  1305. hpdev = container_of(iter, struct hv_pci_dev,
  1306. list_entry);
  1307. if (hpdev->reported_missing) {
  1308. found = true;
  1309. put_pcichild(hpdev, hv_pcidev_ref_childlist);
  1310. list_del(&hpdev->list_entry);
  1311. list_add_tail(&hpdev->list_entry, &removed);
  1312. break;
  1313. }
  1314. }
  1315. } while (found);
  1316. spin_unlock_irqrestore(&hbus->device_list_lock, flags);
  1317. /* Delete everything that should no longer exist. */
  1318. while (!list_empty(&removed)) {
  1319. hpdev = list_first_entry(&removed, struct hv_pci_dev,
  1320. list_entry);
  1321. list_del(&hpdev->list_entry);
  1322. put_pcichild(hpdev, hv_pcidev_ref_initial);
  1323. }
  1324. /* Tell the core to rescan bus because there may have been changes. */
  1325. if (hbus->state == hv_pcibus_installed) {
  1326. pci_lock_rescan_remove();
  1327. pci_scan_child_bus(hbus->pci_bus);
  1328. pci_unlock_rescan_remove();
  1329. } else {
  1330. survey_child_resources(hbus);
  1331. }
  1332. up(&hbus->enum_sem);
  1333. put_hvpcibus(hbus);
  1334. kfree(dr);
  1335. }
  1336. /**
  1337. * hv_pci_devices_present() - Handles list of new children
  1338. * @hbus: Root PCI bus, as understood by this driver
  1339. * @relations: Packet from host listing children
  1340. *
  1341. * This function is invoked whenever a new list of devices for
  1342. * this bus appears.
  1343. */
  1344. static void hv_pci_devices_present(struct hv_pcibus_device *hbus,
  1345. struct pci_bus_relations *relations)
  1346. {
  1347. struct hv_dr_state *dr;
  1348. struct hv_dr_work *dr_wrk;
  1349. unsigned long flags;
  1350. dr_wrk = kzalloc(sizeof(*dr_wrk), GFP_NOWAIT);
  1351. if (!dr_wrk)
  1352. return;
  1353. dr = kzalloc(offsetof(struct hv_dr_state, func) +
  1354. (sizeof(struct pci_function_description) *
  1355. (relations->device_count)), GFP_NOWAIT);
  1356. if (!dr) {
  1357. kfree(dr_wrk);
  1358. return;
  1359. }
  1360. INIT_WORK(&dr_wrk->wrk, pci_devices_present_work);
  1361. dr_wrk->bus = hbus;
  1362. dr->device_count = relations->device_count;
  1363. if (dr->device_count != 0) {
  1364. memcpy(dr->func, relations->func,
  1365. sizeof(struct pci_function_description) *
  1366. dr->device_count);
  1367. }
  1368. spin_lock_irqsave(&hbus->device_list_lock, flags);
  1369. list_add_tail(&dr->list_entry, &hbus->dr_list);
  1370. spin_unlock_irqrestore(&hbus->device_list_lock, flags);
  1371. get_hvpcibus(hbus);
  1372. schedule_work(&dr_wrk->wrk);
  1373. }
  1374. /**
  1375. * hv_eject_device_work() - Asynchronously handles ejection
  1376. * @work: Work struct embedded in internal device struct
  1377. *
  1378. * This function handles ejecting a device. Windows will
  1379. * attempt to gracefully eject a device, waiting 60 seconds to
  1380. * hear back from the guest OS that this completed successfully.
  1381. * If this timer expires, the device will be forcibly removed.
  1382. */
  1383. static void hv_eject_device_work(struct work_struct *work)
  1384. {
  1385. struct pci_eject_response *ejct_pkt;
  1386. struct hv_pci_dev *hpdev;
  1387. struct pci_dev *pdev;
  1388. unsigned long flags;
  1389. int wslot;
  1390. struct {
  1391. struct pci_packet pkt;
  1392. u8 buffer[sizeof(struct pci_eject_response) -
  1393. sizeof(struct pci_message)];
  1394. } ctxt;
  1395. hpdev = container_of(work, struct hv_pci_dev, wrk);
  1396. if (hpdev->state != hv_pcichild_ejecting) {
  1397. put_pcichild(hpdev, hv_pcidev_ref_pnp);
  1398. return;
  1399. }
  1400. /*
  1401. * Ejection can come before or after the PCI bus has been set up, so
  1402. * attempt to find it and tear down the bus state, if it exists. This
  1403. * must be done without constructs like pci_domain_nr(hbus->pci_bus)
  1404. * because hbus->pci_bus may not exist yet.
  1405. */
  1406. wslot = wslot_to_devfn(hpdev->desc.win_slot.slot);
  1407. pdev = pci_get_domain_bus_and_slot(hpdev->hbus->sysdata.domain, 0,
  1408. wslot);
  1409. if (pdev) {
  1410. pci_stop_and_remove_bus_device(pdev);
  1411. pci_dev_put(pdev);
  1412. }
  1413. memset(&ctxt, 0, sizeof(ctxt));
  1414. ejct_pkt = (struct pci_eject_response *)&ctxt.pkt.message;
  1415. ejct_pkt->message_type = PCI_EJECTION_COMPLETE;
  1416. ejct_pkt->wslot.slot = hpdev->desc.win_slot.slot;
  1417. vmbus_sendpacket(hpdev->hbus->hdev->channel, ejct_pkt,
  1418. sizeof(*ejct_pkt), (unsigned long)&ctxt.pkt,
  1419. VM_PKT_DATA_INBAND, 0);
  1420. spin_lock_irqsave(&hpdev->hbus->device_list_lock, flags);
  1421. list_del(&hpdev->list_entry);
  1422. spin_unlock_irqrestore(&hpdev->hbus->device_list_lock, flags);
  1423. put_pcichild(hpdev, hv_pcidev_ref_childlist);
  1424. put_pcichild(hpdev, hv_pcidev_ref_pnp);
  1425. put_hvpcibus(hpdev->hbus);
  1426. }
  1427. /**
  1428. * hv_pci_eject_device() - Handles device ejection
  1429. * @hpdev: Internal device tracking struct
  1430. *
  1431. * This function is invoked when an ejection packet arrives. It
  1432. * just schedules work so that we don't re-enter the packet
  1433. * delivery code handling the ejection.
  1434. */
  1435. static void hv_pci_eject_device(struct hv_pci_dev *hpdev)
  1436. {
  1437. hpdev->state = hv_pcichild_ejecting;
  1438. get_pcichild(hpdev, hv_pcidev_ref_pnp);
  1439. INIT_WORK(&hpdev->wrk, hv_eject_device_work);
  1440. get_hvpcibus(hpdev->hbus);
  1441. schedule_work(&hpdev->wrk);
  1442. }
  1443. /**
  1444. * hv_pci_onchannelcallback() - Handles incoming packets
  1445. * @context: Internal bus tracking struct
  1446. *
  1447. * This function is invoked whenever the host sends a packet to
  1448. * this channel (which is private to this root PCI bus).
  1449. */
  1450. static void hv_pci_onchannelcallback(void *context)
  1451. {
  1452. const int packet_size = 0x100;
  1453. int ret;
  1454. struct hv_pcibus_device *hbus = context;
  1455. u32 bytes_recvd;
  1456. u64 req_id;
  1457. struct vmpacket_descriptor *desc;
  1458. unsigned char *buffer;
  1459. int bufferlen = packet_size;
  1460. struct pci_packet *comp_packet;
  1461. struct pci_response *response;
  1462. struct pci_incoming_message *new_message;
  1463. struct pci_bus_relations *bus_rel;
  1464. struct pci_dev_incoming *dev_message;
  1465. struct hv_pci_dev *hpdev;
  1466. buffer = kmalloc(bufferlen, GFP_ATOMIC);
  1467. if (!buffer)
  1468. return;
  1469. while (1) {
  1470. ret = vmbus_recvpacket_raw(hbus->hdev->channel, buffer,
  1471. bufferlen, &bytes_recvd, &req_id);
  1472. if (ret == -ENOBUFS) {
  1473. kfree(buffer);
  1474. /* Handle large packet */
  1475. bufferlen = bytes_recvd;
  1476. buffer = kmalloc(bytes_recvd, GFP_ATOMIC);
  1477. if (!buffer)
  1478. return;
  1479. continue;
  1480. }
  1481. /* Zero length indicates there are no more packets. */
  1482. if (ret || !bytes_recvd)
  1483. break;
  1484. /*
  1485. * All incoming packets must be at least as large as a
  1486. * response.
  1487. */
  1488. if (bytes_recvd <= sizeof(struct pci_response))
  1489. continue;
  1490. desc = (struct vmpacket_descriptor *)buffer;
  1491. switch (desc->type) {
  1492. case VM_PKT_COMP:
  1493. /*
  1494. * The host is trusted, and thus it's safe to interpret
  1495. * this transaction ID as a pointer.
  1496. */
  1497. comp_packet = (struct pci_packet *)req_id;
  1498. response = (struct pci_response *)buffer;
  1499. comp_packet->completion_func(comp_packet->compl_ctxt,
  1500. response,
  1501. bytes_recvd);
  1502. break;
  1503. case VM_PKT_DATA_INBAND:
  1504. new_message = (struct pci_incoming_message *)buffer;
  1505. switch (new_message->message_type.message_type) {
  1506. case PCI_BUS_RELATIONS:
  1507. bus_rel = (struct pci_bus_relations *)buffer;
  1508. if (bytes_recvd <
  1509. offsetof(struct pci_bus_relations, func) +
  1510. (sizeof(struct pci_function_description) *
  1511. (bus_rel->device_count))) {
  1512. dev_err(&hbus->hdev->device,
  1513. "bus relations too small\n");
  1514. break;
  1515. }
  1516. hv_pci_devices_present(hbus, bus_rel);
  1517. break;
  1518. case PCI_EJECT:
  1519. dev_message = (struct pci_dev_incoming *)buffer;
  1520. hpdev = get_pcichild_wslot(hbus,
  1521. dev_message->wslot.slot);
  1522. if (hpdev) {
  1523. hv_pci_eject_device(hpdev);
  1524. put_pcichild(hpdev,
  1525. hv_pcidev_ref_by_slot);
  1526. }
  1527. break;
  1528. default:
  1529. dev_warn(&hbus->hdev->device,
  1530. "Unimplemented protocol message %x\n",
  1531. new_message->message_type.message_type);
  1532. break;
  1533. }
  1534. break;
  1535. default:
  1536. dev_err(&hbus->hdev->device,
  1537. "unhandled packet type %d, tid %llx len %d\n",
  1538. desc->type, req_id, bytes_recvd);
  1539. break;
  1540. }
  1541. }
  1542. kfree(buffer);
  1543. }
  1544. /**
  1545. * hv_pci_protocol_negotiation() - Set up protocol
  1546. * @hdev: VMBus's tracking struct for this root PCI bus
  1547. *
  1548. * This driver is intended to support running on Windows 10
  1549. * (server) and later versions. It will not run on earlier
  1550. * versions, as they assume that many of the operations which
  1551. * Linux needs accomplished with a spinlock held were done via
  1552. * asynchronous messaging via VMBus. Windows 10 increases the
  1553. * surface area of PCI emulation so that these actions can take
  1554. * place by suspending a virtual processor for their duration.
  1555. *
  1556. * This function negotiates the channel protocol version,
  1557. * failing if the host doesn't support the necessary protocol
  1558. * level.
  1559. */
  1560. static int